2-Input Exclusive OR Gate / CMOS Logic Level Shifter with LSTTL-Compatible Inputs

MC74VHC1GT86
2-Input Exclusive OR Gate /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
Features
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MARKING
DIAGRAMS
5
5
1
SC−88A / SOT−353 / SC−70
DF SUFFIX
CASE 419A
M
The MC74VHC1GT86 is an advanced high speed CMOS 2−input
Exclusive OR gate fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT86 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT86 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
VM M G
G
1
5
5
VM M G
G
1
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
CASE 483
VM
M
G
1
= Device Code
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
High Speed: tPD = 4.8 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V
CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
PIN ASSIGNMENT
Power Down Protection Provided on Inputs and Outputs
1
Balanced Propagation Delays
2
IN A
Pin and Function Compatible with Other Standard Logic Families
3
GND
Chip Complexity: FETs = 83; Equivalent Gates = 16
These Devices are Pb−Free and are RoHS Compliant
4
OUT Y
5
VCC
IN B
1
IN A
2
GND
3
5
IN B
FUNCTION TABLE
VCC
Inputs
4
OUT Y
Figure 1. Pinout (Top View)
IN A
IN B
=1
May, 2011 − Rev. 16
A
B
Y
L
L
H
H
L
H
L
H
L
H
H
L
ORDERING INFORMATION
OUT Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2011
Output
1
Publication Order Number:
MC74VHC1GT86/D
MC74VHC1GT86
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
VCC
DC Supply Voltage
−0.5 to +7.0
V
VIN
DC Input Voltage
−0.5 to +7.0
V
−0.5 to 7.0
−0.5 to VCC + 0.5
V
−20
mA
+20
mA
+25
mA
VOUT
DC Output Voltage
VCC = 0
High or Low State
IIK
Input Diode Current
IOK
Output Diode Current
IOUT
DC Output Current, per Pin
ICC
DC Supply Current, VCC and GND
PD
Power dissipation in still air
qJA
Thermal resistance
TL
VOUT < GND; VOUT > VCC
+50
mA
SC−88A, TSOP−5
200
mW
SC−88A, TSOP−5
333
°C/W
Lead temperature, 1 mm from case for 10 seconds
260
°C
TJ
Junction temperature under bias
+150
°C
Tstg
Storage temperature
−65 to +150
°C
> 2000
> 200
N/A
V
±500
mA
VESD
ESD Withstand Voltage
ILatchup
Latchup Performance
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above VCC and Below GND at 125°C (Note 5)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Derating − SC−88A Package: –3 mW/°C from 65° to 125°C
− TSOP5 Package: −3 mW/°C from 65° to 125°C
2. Tested to EIA/JESD22−A114−A
3. Tested to EIA/JESD22−A115−A
4. Tested to JESD22−C101−A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Max
Unit
VCC
DC Supply Voltage
Characteristics
3.0
5.5
V
VIN
DC Input Voltage
0.0
5.5
V
0.0
0.0
5.5
VCC
V
−55
+125
°C
0
0
100
20
ns/V
VOUT
DC Output Voltage
TA
VCC = 0
High or Low State
Operating Temperature Range
tr , tf
Input Rise and Fall Time
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80 ° C
117.8
TJ = 90 ° C
1,032,200
TJ = 100 ° C
80
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 110° C
Time, Years
TJ = 120° C
Time, Hours
TJ = 130 ° C
Junction
Temperature °C
NORMALIZED FAILURE RATE
Device Junction Temperature versus
Time to 0.1% Bond Failures
1
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1GT86
DC ELECTRICAL CHARACTERISTICS
VCC
Symbol
Parameter
Test Conditions
(V)
Min
1.4
2.0
2.0
VIH
Minimum High−Level
Input Voltage
3.0
4.5
5.5
VIL
Maximum Low−Level
Input Voltage
3.0
4.5
5.5
VOH
Minimum High−Level
Output Voltage
VIN = VIH or VIL
VOL
Maximum Low−Level
Output Voltage
VIN = VIH or VIL
TA = 25°C
Typ
TA ≤ 85°C
Max
Min
1.4
2.0
2.0
0.53
0.8
0.8
VIN = VIH or VIL
IOH = −50 mA
3.0
4.5
2.9
4.4
VIN = VIH or VIL
IOH = −4 mA
IOH = −8 mA
3.0
4.5
2.58
3.94
VIN = VIH or VIL
IOL = 50 mA
3.0
4.5
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
Max
3.0
4.5
0.0
0.0
−55 ≤ TA ≤ 125°C
Min
Max
1.4
2.0
2.0
0.53
0.8
0.8
V
0.53
0.8
0.8
2.9
4.4
2.9
4.4
2.48
3.80
2.34
3.66
Unit
V
V
V
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
V
IIN
Maximum Input
Leakage Current
VIN = 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
1.0
20
40
mA
ICCT
Quiescent Supply
Current
Input: VIN = 3.4 V
5.5
1.35
1.50
1.65
mA
IOPD
Output Leakage
Current
VOUT = 5.5 V
0.0
0.5
5.0
10
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎ
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ÎÎÎÎ
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ÎÎÎ
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ÎÎ
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ÎÎÎÎ
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ÎÎÎ
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ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr = tf = 3.0 ns
TA = 25°C
Parameter
Test Conditions
Typ
Max
Max
Unit
tPLH,
tPHL
Maximum Propagation
Delay, Input A or B to Y
VCC = 3.3 ± 0.3 VCL = 15 pF
CL = 50 pF
5.0
6.2
11.0
14.5
13.0
16.5
15.5
19.5
ns
VCC = 5.0 ± 0.5 VCL = 15 pF
CL = 50 pF
3.1
4.2
6.8
8.8
8.0
10.0
10.0
12.0
5.5
10
10
10
Maximum Input
Capacitance
CPD
Power Dissipation Capacitance (Note 6)
Min
Max
−55 ≤ TA ≤ 125°C
Symbol
CIN
Min
TA ≤ 85°C
Min
pF
Typical @ 25°C, VCC = 5.0 V
11
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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3
MC74VHC1GT86
3.0 V
A or B
50%
GND
tPLH
Y
tPHL
VOH
50%
VOL
Figure 4. Switching Waveforms
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL *
*Includes all probe and jig capacitance
Figure 5. Test Circuit
ORDERING INFORMATION
Device
Package
M74VHC1GT86DFT1G
SC−88A / SOT−353 / SC−70
(Pb−Free)
M74VHC1GT86DFT2G
SC−88A / SOT−353 / SC−70
(Pb−Free)
M74VHC1GT86DTT1G
TSOP−5 / SOT−23 / SC−59
(Pb−Free)
Shipping†
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1GT86
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE K
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
M
B
M
N
J
C
H
K
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5
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
MC74VHC1GT86
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
D 5X
NOTE 5
2X
0.10 T
2X
0.20 T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
0.20 C A B
M
5
1
4
2
L
3
B
S
K
DETAIL Z
G
A
DIM
A
B
C
D
G
H
J
K
L
M
S
DETAIL Z
J
C
0.05
SEATING
PLANE
H
T
MILLIMETERS
MIN
MAX
3.00 BSC
1.50 BSC
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
1.25
1.55
0_
10 _
2.50
3.00
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHC1GT86/D
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