Configurable Multifunction Gate

NL7SZ97
Configurable Multifunction
Gate
The NL7SZ97 is an advanced high−speed CMOS multifunction
gate. The device allows the user to choose logic functions MUX,
AND, OR, NAND, NOR, INVERT and BUFFER. The device has
Schmitt−trigger inputs, thereby enhancing noise immunity.
The NL7SZ97 input and output structures provide protection when
voltages up to 7.0 V are applied, regardless of the supply voltage.
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Features
•
•
•
•
•
•
•
•
1
High Speed: tPD = 3.3 ns (Typ) @ VCC = 5.0 V
Low Power Dissipation: ICC = 1 mA (Maximum) at TA = 25°C
Power Down Protection Provided on inputs
Balanced Propagation Delays
Overvoltage Tolerant (OVT) Input and Output Pins
Ultra−Small Package
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
This is a Pb−Free Device
SC−88 (SOT−363)
CASE 419B
MARKING DIAGRAM
6
MK MG
G
1
MK
= Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENTS
IN B
1
6
IN C
GND
2
5
VCC
IN A
3
4
OUT Y
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 4
1
Publication Order Number:
NL7SZ97/D
NL7SZ97
IN A
OUT Y
IN B
IN C
Figure 1. Function Diagram
PIN ASSIGNMENT
FUNCTION TABLE*
1
IN B
Input
Output
2
GND
A
B
C
Y
3
IN A
L
L
L
L
4
OUT Y
L
L
H
L
5
VCC
L
H
L
H
6
IN C
L
H
H
L
H
L
L
L
H
L
H
H
H
H
L
H
H
H
H
H
*To select a logic function, please refer to “Logic Configurations
section”.
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2
NL7SZ97
LOGIC CONFIGURATIONS
VCC
B
B
Y
A
A
1
6
2
5
3
4
VCC
C
A
Y
C
Y
A
1
6
2
5
3
4
C
Y
C
Figure 2. 2−Input MUX
Figure 3. 2−Input AND (When B = “L”)
VCC
VCC
A
C
A
1
Y
A
6
2
5
3
4
B
C
Y
B
C
Y
B
Y
6
2
5
3
4
Figure 4. 2−Input OR with Input C Inverted
(When B = “H”)
C
B
Y
1
6
2
5
3
4
VCC
C
C
Y
Y
Figure 6. 2−Input OR (When A =”H”)
1
6
2
5
3
4
C
Y
Figure 7. Inverter (When A = “L” and B =
“H”)
VCC
B
B
Y
Figure 5. 2−Input AND with Input C
Inverted (When A = “L”)
VCC
B
C
Y
C
C
1
Y
1
6
2
5
3
4
Y
Figure 8. Buffer (When A = C = “L”)
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3
NL7SZ97
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
−0.5 to +7.0
V
VIN
DC Input Voltage
−0.5 to +7.0
V
DC Output Voltage
−0.5 to +7.0
V
VIN < GND
−50
mA
VOUT < GND
−50
mA
VOUT
Parameter
IIK
DC Input Diode Current
IOK
DC Output Diode Current
IO
DC Output Source/Sink Current
$50
mA
ICC
DC Supply Current Per Supply Pin
$100
mA
IGND
DC Ground Current per Ground Pin
$100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction Temperature Under Bias
+150
°C
qJA
Thermal Resistance (Note 1)
SC−88
350
°C/W
PD
Power Dissipation in Still Air at 85°C
SC−88
200
mW
MSL
FR
VESD
ILATCHUP
Moisture Sensitivity
Level 1
Flammability Rating Oxygen
Index: 28 to 34
ESD Withstand Voltage
UL 94 V−0 @ 0.125 in
Human Body Mode (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Latchup Performance Above VCC and Below GND at 125°C (Note 5)
>2000
>200
N/A
V
$500
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm2 by 1 inch, 2 ounce copper trace no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
1.65
5.5
V
Digital Input Voltage
0
5.5
V
Output Voltage
0
5.5
V
−55
+125
°C
0
0
0
No Limit
No Limit
No Limit
nS/V
VCC
Positive DC Supply Voltage
VIN
VOUT
TA
Dt/DV
Operating Free−Air Temperature (Note 6)
Input Transition Rise or Fall Rate
VCC = 2.5 V $ 0.2 V
VCC = 3.3 V $ 0.3 V
VCC = 5.0 V $ 0.5 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. The NL7SZ97 will not have degradation in its electrical spcifications or Mean−Time−Between−Failure (MTBF) when exposed to a
temperature cycle test of 140°C for 21 hours, 135°C for 750 hours and of 130°C for 175 hours.
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4
NL7SZ97
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VT+
Positive Threshold
Voltage
VT−
VH
VOH
VOL
Conditions
Negative
Threshold Voltage
Hysteresis Voltage
Minimum
High−Level Output
Voltage
Maximum
Low−Level Output
Voltage
TA = 255C
VCC
(V)
Min
1.65
0.79
1.16
2.3
1.11
3.0
4.5
5.5
Typ
Max
TA v +855C
TA = −555C to
+1255C
Min
Min
Max
Max
Unit
1.16
1.16
V
1.56
1.56
1.56
1.5
1.87
1.87
1.87
2.16
2.74
2.74
2.74
2.61
3.33
3.33
3.33
1.65
0.35
0.62
0.35
0.35
2.3
0.58
0.87
0.58
0.58
3.0
0.84
1.19
0.84
0.84
4.5
1.41
1.9
1.41
1.41
5.5
1.78
2.29
1.78
1.78
1.65
0.30
0.62
0.30
0.62
0.30
0.62
2.3
0.40
0.8
0.40
0.8
0.40
0.8
3.0
0.53
0.87
0.53
0.87
0.53
0.87
4.5
0.71
1.04
0.71
1.04
0.71
1.04
1.2
0.8
1.2
0.8
1.2
V
5.5
0.8
1.65 −
5.5
VCC
− 0.1
VCC
− 0.1
VCC
− 0.1
IOH = −4 mA
1.65
1.2
1.2
1.2
IOH = −8 mA
2.3
1.9
1.9
1.9
IOH = −16 mA
3.0
2.4
2.4
2.4
IOH = −24 mA
3.0
2.3
2.3
2.3
IOH = −32 mA
4.5
3.8
3.8
3.8
VIN w VT+MAX
IOL = 50 mA
1.65 −
5.5
0.1
0.1
0.1
IOL = 4 mA
1.65
0.45
0.45
0.45
IOL = 8 mA
2.3
0.3
0.3
0.3
IOL = 16 mA
3.0
0.4
0.4
0.4
IOL = 24 mA
3.0
0.55
0.55
0.55
IOL = 32 mA
4.5
0.55
0.55
0.55
VIN v VT−MIN
IOH = −50 mA
V
V
VIN v VT−MIN
V
VIN w VT+MAX
IIN
Input Leakage
Current
0 v VIN v
5.5 V
0 to
5.5
$0.1
$1.0
$1.0
mA
ICC
Quiescent Supply
Current
0 v VIN v VCC
5.5
1.0
10
10
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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5
NL7SZ97
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
TA = 255C
Typ
Max
Min
Max
Min
Max
Unit
1.65 − 1.95
3.2
8.6
14.4
3.2
14.4
3.2
14.4
ns
2.3 − 2.7
2.0
5.1
8.3
2.0
8.3
2.0
8.3
3.0 − 3.6
1.5
3.9
6.3
1.5
6.3
1.5
6.3
4.5 − 5.5
1.1
3.3
5.1
1.1
5.1
1.1
5.1
Parameter
VCC (V)
tPLH,
tPHL
Propagation Delay,
Any Input to Output
Y (See Test Circuit)
Input Capacitance
CPD
Power Dissipation
Capacitance
(Note 7)
TA = −555C
to +1255C
Min
Symbol
CIN
TA v +855C
Test Condition
5.0
f = 10 MHz
3.5
pF
22
pF
7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without
load. Average operating current can be obtained by the equation ICC(OPR) = CPD • VCC • fin + ICC. CPD is used to determine the no−load
dynamic power consumption: PD = CPD • VCC2 • fin + ICC • VCC.
TEST CIRCUIT AND VOLTAGE WAVEFORMS
From Output
Under Test
VLOAD
RL
Test
S1
tPLH/tPHL
Open
tPLZ/tPZL
VLOAD
tPHZ/tPZH
GND
Open
GND
CL *
RL
*CL includes probes and jig capacitance.
Figure 9. Load Circuit
Inputs
VCC
VI
tr/tf
VM
VLOAD
CL
RL
VD
1.8 V $ 0.15 V
VCC
v 2 ns
VCC/2
2 x VCC
30 pF
1 kW
0.15 V
2.5 V $ 0.2 V
VCC
v 2 ns
VCC/2
2 x VCC
30 pF
500 W
0.15 V
3.3 V $ 0.3 V
3V
v 2.5 ns
1.5 V
6V
50 pF
500 W
0.3 V
5.5 V $ 0.5 V
VCC
v 2.5 ns
VCC/2
2 x VCC
50 pF
500 W
0.3 V
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6
NL7SZ97
Timing Input
tW
Input
VI
VM
0V
VI
VM
VM
tsu
0V
Data Input
th
VM
VI
VM
0V
Figure 10. Voltage Waveforms Pulse Duration
Figure 11. Voltage Waveforms Setup and Hold
Times
VI
Input
VM
VM
VM
tPHL
Output
0V
tPHL
tPLH
Output
Output
Control
VM
Output
Waveform 1
S1 at VLOAD
(Note 8)
VOH
VOL
tPLH
VM
VM
VM
VM
0V
VM
tPZH
VOH
Output
Waveform 2
S1 at GND
(Note 9)
VOL
Figure 12. Voltage Waveforms Propagation Delay
Times Inverting and Noninverting Outputs
VI
VM
VLOAD/2
VOL + VD
VOL
tPHZ
VOH
VOH − VD
[0 V
Figure 13. Voltage Waveforms Enable and
Disable Times Low− and High−Level Enabling
8. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
9. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control
10. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 W.
11. The outputs are measured one at a time, with one transition per measurement.
12. All parameters are waveforms are not applicable to all devices.
ORDERING INFORMATION
Package
Shipping†
NL7SZ97DFT2G
SC−88
(Pb−Free)
3000 / Tape & Reel
NLV7SZ97DFT2G*
SC−88
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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7
NL7SZ97
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
2X
aaa H D
D
H
A
D
6
5
GAGE
PLANE
4
L
L2
E1
E
1
2
DETAIL A
3
aaa C
2X
bbb H D
2X 3 TIPS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
e
B
6X
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
b
ddd
TOP VIEW
M
A2
C A-B D
DETAIL A
A
6X
ccc C
A1
C
SIDE VIEW
SEATING
PLANE
c
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
6X
6X
0.30
0.66
2.50
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Email: [email protected]
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Phone: 421 33 790 2910
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NL7SZ97/D
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