5V ECL 12-Bit Parity Generator/Checker

MC10E160, MC100E160
5VECL 12-Bit Parity
Generator/Checker
The MC10E/100E160 is a 12-bit parity generator/checker. The Q
output is HIGH when an odd number of inputs are HIGH. A HIGH on
the Enable input (EN) forces the Q output LOW.
The 100 Series contains temperature compensation.
•
•
•
•
•
•
•
•
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Provides Odd-HIGH Parity of 12 Inputs
MARKING
DIAGRAMS
Shiftable Output Register with Hold
1 28
900 ps Max. D to Q/Q Output
Enable
Asynchronous Register Reset
MC10E160FN
Dual Clocks
AWLYYWW
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input to 50 KW Pulldown Resistors
PLCC−28
FN SUFFIX
CASE 776
•
• ESD Protection: Human Body Model; > 1 KV,
Machine Model; > 7 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
A
WL
YY
WW
1 28
= Assembly Location
= Wafer Lot
= Year
= Work Week
MC100E160FN
AWLYYWW
•
• Moisture Sensitivity Level 1
•
•
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 312 devices
ORDERING INFORMATION
Package
Shipping †
MC10E160FN
PLCC−28
37 Units/Rail
MC10E160FNR2
PLCC−28
500 Units/Reel
MC100E160FN
PLCC−28
37 Units/Rail
MC100E160FNR2
PLCC−28
500 Units/Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
Publication Order Number:
MC10E160/D
MC10E160, MC100E160
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D4
D3
D2
D1
25
24
23
22
D0
21
20
PIN
19
D5
26
18
Q
D6
27
17
Q
D7
28
16
VCC
15
Y
VEE
Pinout: 28-Lead PLCC
(Top View)
1
D8
2
14
Y
D9
3
13
VCCO
D10
4
12
NC
5
6
7
8
9
PIN DESCRIPTION
EN VCCO
10
11
FUNCTION
D0 − D11
ECL Data Inputs
S-IN
ECL Serial Data Input
EN
ECL Enable, active LOW
HOLD
ECL Hold, active LOW
SHIFT
ECL Shift, active HIGH
CLK1, CLK2
ECL Clock Inputs
R
ECL Reset Inputs
Q, Q
ECL Direct Output
Y, Y
ECL Register Output
VCC, VCCO
Positive Supply
VEE
Negative Supply
NC
No Connect
D11 HOLD S-IN SHIFT CLK1 CLK2 R
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
D0
D1
D2
D3
LOGIC DIAGRAM
D4
D5
D6
D7
D8
D9
D10
D11
Q
0
MUX
1 SEL
EN
HOLD
S-IN
SHIFT
CLK1
CLK2
R
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2
0
MUX
1 SEL
Y
D
R
Y
MC10E160, MC100E160
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
8
V
6
−6
V
V
50
100
mA
mA
0 to +85
°C
−65 to +150
°C
VCC
PECL Mode Power Supply
VEE = 0 V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
28 PLCC
28 PLCC
63.5
43.5
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
28 PLCC
22 to 26
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
VI VCC
VI VEE
1. Maximum Ratings are those values beyond which device damage may occur.
10E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 2)
0°C
Symbol
Characteristic
Typ
Max
82
98
3980
4070
4160
3050
3210
3370
Input HIGH Voltage
3830
3995
Input LOW Voltage
3050
3285
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 3)
VOL
Output LOW Voltage (Note 3)
VIH
VIL
IIH
Input HIGH Current
IIL
Min
25°C
CLK1, CLK2
R
All Other Inputs
Input LOW Current
Min
Typ
Max
82
98
4020
4105
4190
3050
3210
3370
4160
3870
4030
4190
3520
3050
3285
3520
200
300
150
0.5
85°C
0.3
Min
Typ
Max
Unit
82
98
mA
4090
4185
4280
mV
3050
3227
3405
mV
3940
4110
4280
mV
3050
3302
3555
mV
200
300
150
mA
mA
mA
200
300
150
0.5
0.25
0.3
0.2
mA
NOTE:
Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained.
2. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
3. Outputs are terminated through a 50 ohm resistor to VCC − 2 volts.
100E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= −5.0 V (Note 8)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
82
98
82
98
82
98
mA
VOH
Output HIGH Voltage (Note 5)
−1020
−930
−840
−980
−895
−810
−910
−815
−720
mV
VOL
Output LOW Voltage (Note 5)
−1950
−1790
−1630
−1950
−1790
−1630
−1950
−1773
−1595
mV
VIH
Input HIGH Voltage
−1170
−1005
−840
−1130
−970
−810
−1060
−890
−720
mV
VIL
Input LOW Voltage
−1950
−1715
−1480
−1950
−1715
−1480
−1950
−1698
−1445
mV
IIH
Input HIGH Current
200
300
150
mA
mA
mA
IIL
Input LOW Current
CLK1, CLK2
R
All Other Inputs
200
300
150
0.5
0.3
NOTE:
200
300
150
0.5
0.065
0.3
0.2
mA
Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained.
4. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
5. Outputs are terminated through a 50 ohm resistor to VCC − 2 volts.
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3
MC10E160, MC100E160
100E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 6)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
82
98
Min
85°C
Typ
Max
82
98
Min
Typ
Max
Unit
94
113
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 7)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 7)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage
3835
3975
4120
3835
3975
4120
3835
3975
4120
mV
VIL
Input LOW Voltage
3190
3355
3525
3190
3355
3525
3190
3355
3525
mV
IIH
Input HIGH Current
200
300
150
mA
mA
mA
CLK1, CLK2
R
All Other Inputs
IIL
Input LOW Current
200
300
150
0.5
0.3
200
300
150
0.5
0.25
0.5
0.2
mA
NOTE:
Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
7. Outputs are terminated through a 50 ohm resistor to VCC − 2 volts.
100E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= −5.0 V (Note 8)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
82
98
Min
85°C
Typ
Max
82
98
Min
Typ
Max
Unit
94
113
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 9)
−1025
−950
−880
−1025
−950
−880
−1025
−950
−880
mV
VOL
Output LOW Voltage (Note 9)
−1810
−1705
−1620
−1810
−1745
−1620
−1810
−1740
−1620
mV
VIH
Input HIGH Voltage
−1165
−1025
−880
−1165
−1025
−880
−1165
−1025
−880
mV
VIL
Input LOW Voltage
−1810
−1645
−1475
−1810
−1645
−1475
−1810
−1645
−1475
mV
IIH
Input HIGH Current
200
300
150
mA
mA
mA
CLK1, CLK2
R
All Other Inputs
IIL
Input LOW Current
200
300
150
0.5
0.3
NOTE:
200
300
150
0.5
0.25
0.5
0.2
mA
Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained.
8. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
9. Outputs are terminated through a 50 ohm resistor to VCC − 2 volts.
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4
MC10E160, MC100E160
AC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= −5.0 V (Note 10)
0°C
Symbol
Characteristic
Min
Typ
700
1100
D to Q
400
650
En to Q
300
CLK to Y
R to Y
fMAX
Maximum Toggle Frequency
tPLH
Propagation Delay to Output
tPHL
ts
th
Max
Min
Typ
700
1100
950
400
650
550
750
300
275
500
700
275
500
725
85°C
Max
Min
Typ
Max
700
1100
950
400
650
950
550
750
300
550
750
275
500
700
275
500
700
275
500
725
275
500
725
MHz
Setup Time
ps
D
1200
900
1200
900
1200
900
HOLD
600
300
600
300
600
300
S-IN
350
150
350
150
350
150
SHIFT
500
250
500
250
500
250
Hold Time
tJITTER
Random Clock Jitter (RMS)
tr
Rise/Fall Time
(20 - 80%)
Unit
ps
ps
D
tf
25°C
− 400
− 900
− 400
− 900
− 400
− 900
HOLD
100
− 300
100
− 300
100
− 300
S-IN
300
−150
300
−150
300
−150
SHIFT
200
− 250
200
− 250
200
− 250
<1
<1
<1
ps
ps
300
450
650
300
NOTE:
450
650
300
450
650
Devices are designed to meet the AC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained.
10. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
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5
MC10E160, MC100E160
Q
D
Receiver
Device
Driver
Device
Q
D
50 W
50 W
V TT
VTT = VCC − 2.0 V
Figure 1. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
−
ECLinPS Circuit Performance at Non−Standard VIH Levels
AN1405
−
ECL Clock Distribution Techniques
AN1406
−
Designing with PECL (ECL at +5.0 V)
AN1503
−
ECLinPS I/O SPICE Modeling Kit
AN1504
−
Metastability and the ECLinPS Family
AN1568
−
Interfacing Between LVDS and ECL
AN1596
−
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
−
Using Wire−OR Ties in ECLinPS Designs
AN1672
−
The ECL Translator Guide
AND8001
−
Odd Number Counters Design
AND8002
−
Marking and Date Codes
AND8020
−
Termination of ECL Logic Devices
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6
MC10E160, MC100E160
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
-N-
0.007 (0.180)
B
Y BRK
U
T L −M
M
0.007 (0.180)
M
S
N
T L −M
S
S
N
S
D
-L-
Z
-M-
D
W
X
V
28
1
G1
0.010 (0.250)
S
T L −M
S
N
S
VIEW D-D
Z
C
A
0.007 (0.180)
R
0.007 (0.180)
M
T L −M
S
N
S
M
T L −M
S
N
S
H
0.007 (0.180)
M
T L −M
N
S
K1
E
0.004 (0.100)
G
J
S
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
-T-
T L −M
S
N
0.007 (0.180)
VIEW S
S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
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7
INCHES
MIN
MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
0.025
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
0.020
2°
10°
0.410 0.430
0.040
MILLIMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.79
2.29
0.33
0.48
1.27 BSC
0.81
0.66
0.51
0.64
11.58
11.43
11.58
11.43
1.07
1.21
1.07
1.21
1.42
1.07
0.50
2°
10°
10.42 10.92
1.02
M
T L −M
S
N
S
S
MC10E160, MC100E160
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
Literature Distribution Center for ON Semiconductor
USA/Canada
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Phone: 81−3−5773−3850
Email: [email protected]
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Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
MC10E160/D
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