MC74HC390 Dual 4−Stage Binary Ripple Counter with ÷ 2 and ÷ 5 Sections High−Performance Silicon−Gate CMOS The MC54/74HC390 is identical in pinout to the LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two independent 4−bit counters, each composed of a divide−by−two and a divide−by−five section. The divide−by−two and divide−by−five counters have separate clock inputs, and can be cascaded to implement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter. Flip−flops internal to the counters are triggered by high−to−low transitions of the clock input. A separate, asynchronous reset is provided for each 4−bit counter. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or strobes except when gated with the Clock of the HC390. • • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No 7A Chip Complexity: 244 FETs or 61 Equivalent Gates LOGIC DIAGRAM CLOCK A 1, 15 ÷2 COUNTER 3, 13 http://onsemi.com J SUFFIX CERAMIC PACKAGE CASE 620−10 16 1 N SUFFIX PLASTIC PACKAGE CASE 648−08 16 1 D SUFFIX SOIC PACKAGE CASE 751B−05 16 1 ORDERING INFORMATION MC54HCXXXJ MC74HCXXXN MC74HCXXXD Ceramic Plastic SOIC PIN ASSIGNMENT CLOCK Aa 1 16 VCC RESET a 2 15 CLOCK Ab QAa 3 14 RESET b CLOCK Ba 4 13 QAb QBa 5 12 CLOCK Bb QCa 6 11 QBb QDa 7 10 QCb GND 8 9 QDb QA 5, 11 CLOCK B RESET 4, 12 ÷5 COUNTER QB 6, 10 QC 7, 9 QD FUNCTION TABLE Clock B Reset Action X X H X L Reset ÷ 2 and ÷ 5 Increment ÷2 Increment ÷5 2, 14 PIN 16 = VCC PIN 8 = GND © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 7 A X 1 L Publication Order Number: MC74HC390/D MC74HC390 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ MAXIMUM RATINGS* Symbol Parameter Value Unit – 0.5 to + 7.0 V VCC DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 50 mA PD Power Dissipation in Still Air,Plastic or Ceramic DIP† SOIC Package† 750 500 mW Tstg Storage Temperature – 65 to + 150 _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. TL Lead Temperature, 1 mm from Case for 10 Seconds _C (Plastic or SOIC DIP) 260 (Ceramic DIP) 300 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D). ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min Max Unit 2.0 6.0 V 0 VCC V – 55 + 125 _C 0 0 0 1000 500 400 ns DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC V – 55 to 25_C v 85_C v 125_C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 μA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 μA 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| v 20 μA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.40 0.40 Symbol Parameter Test Conditions Vin = VIH or VIL VOL Maximum Low−Level Output Voltage |Iout| v 4.0 mA |Iout| v 5.2 mA Vin = VIH or VIL |Iout| v 20 μA Vin = VIH or VIL |Iout| v 4.0 mA |Iout| v 5.2 mA V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 μA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 μA 6.0 8 80 160 μA NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D). http://onsemi.com 2 MC74HC390 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V – 55 to 25_C v 85_C v 125_C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 3) 2.0 4.5 6.0 5.4 27 32 4.4 22 26 3.6 18 21 MHz tPLH, tPHL Maximum Propagation Delay, Clock A to QA (Figures 1 and 3) 2.0 4.5 6.0 120 24 20 150 30 26 180 36 31 ns tPLH, tPHL Maximum Propagation Delay, Clock A to QC (QA connected to Clock B) (Figures 1 and 3) 2.0 4.5 6.0 290 58 49 365 73 62 435 87 74 ns tPLH, tPHL Maximum Propagation Delay, Clock B to QB (Figures 1 and 3) 2.0 4.5 6.0 130 26 22 165 33 28 195 39 33 ns tPLH, tPHL Maximum Propagation Delay, Clock B to QC (Figures 1 and 3) 2.0 4.5 6.0 185 37 31 230 46 39 280 56 48 ns tPLH, tPHL Maximum Propagation Delay, Clock B to QD (Figures 1 and 3) 2.0 4.5 6.0 130 26 22 165 33 28 195 39 33 ns tPHL Maximum Propagation Delay, Reset to any Q (Figures 2 and 3) 2.0 4.5 6.0 165 33 28 205 41 35 250 50 43 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns Maximum Input Capacitance — 10 10 10 pF Cin NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD 35 Power Dissipation Capacitance (Per Counter)* pF * Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V – 55 to 25_C v 85_C v 125_C Unit trec Minimum Recovery Time, Reset Inactive to Clock A or Clock B (Figure 2) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns tw Minimum Pulse Width, Clock A, Clock B (Figure 1) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 4.5 6.0 125 25 21 155 31 26 190 38 32 ns Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns tf, tf NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D). http://onsemi.com 3 MC74HC390 PIN DESCRIPTIONS OUTPUTS QA (Pins 3, 13) INPUTS Clock A (Pins 1, 15) and Clock B (Pins 4, 15) Clock A is the clock input to the ÷ 2 counter; Clock B is the clock input to the ÷ 5 counter. The internal flip−flops are toggled by high−to−low transitions of the clock input. Output of the ÷ 2 counter. QB, QC, QD (Pins 5, 6, 7, 9, 10, 11) Outputs of the ÷ 5 counter. QD is the most significant bit. QA is the least significant bit when the counter is connected for BCD output as in Figure 4. QB is the least significant bit when the counter is operating in the bi−quinary mode as in Figure 5. CONTROL INPUTS Reset (Pins 2, 14) Asynchronous reset. A high at the Reset input prevents counting, resets the internal flip−flops, and forces QA through QD low. SWITCHING WAVEFORMS CLOCK tf 90% 50% 10% 10% tr tw VCC tw Q GND tPHL 1/fmax tPLH VCC 50% RESET GND tPHL 50% Q 90% 50% 10% trec tTLH tTHL 50% CLOCK GND Figure 1. Figure 2. TEST CIRCUIT TEST POINT OUTPUT DEVICE UNDER TEST C L* *Includes all probe and jig capacitance Figure 3. http://onsemi.com 4 VCC MC74HC390 EXPANDED LOGIC DIAGRAM 1, 15 CLOCK A D 4, 12 CLOCK B D D Q C R 3, 13 Q Q C R 5, 11 Q Q C R R QB Q 6, 10 Q C Q 7, 9 Q D C D QA 2, 14 RESET TIMING DIAGRAM (QA Connected to Clock B) 0 1 2 3 4 5 6 7 8 CLOCK A RESET QA QB QC QD http://onsemi.com 5 9 0 1 2 3 4 5 6 MC74HC390 APPLICATIONS INFORMATION Each half of the MC54/74HC390 has independent ÷ 2 and ÷ 5 sections (except for the Reset function). The ÷ 2 and ÷ 5 counters can be connected to give BCD or bi−quinary (2−5) count sequences. If Output Q A is connected to the Clock B input (Figure 4), a decade divider with BCD output is obtained. The function table for the BCD count sequence is given in Table 1. To obtain a bi−quinary count sequence, the input signals connected to the Clock B input, and output QD is connected to the Clock A input (Figure 5). QA provides a 50% duty cycle output. The bi−quinary count sequence function table is given in Table 2. 1. BCD Count Sequence* Output Count QD QC 0 L L 1 L L 2 L L 3 L L 4 L H 5 L H 6 L H 7 L H 8 H L 9 H L *QA connected to Clock B input. http://onsemi.com 6 QB QA L L H H L L H H L L L H L H L H L H L H MC74HC390 2. Bi−Quinary Count Sequence** Output Count QA QD QC QB 0 1 2 3 4 8 9 10 11 12 L L L L L H H H H H L L L L H L L L L H L L H H L L L H H L L H L H L L H L H L ** QD connected to Clock A input. CONNECTION DIAGRAMS CLOCK A CLOCK B RESET 1, 15 4, 12 ÷2 COUNTER 3, 13 5, 11 ÷5 COUNTER 6, 10 7, 9 QA CLOCK A QB CLOCK B QC 1, 15 4, 12 QD 2, 14 RESET Figure 4. BCD Count ÷2 COUNTER ÷5 COUNTER 3, 13 QA 5, 11 QB 6, 10 7, 9 2, 14 Figure 5. Bi-Quinary Count http://onsemi.com 7 QC QD MC74HC390 OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 620−10 ISSUE V −A − 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. −B − L C −T − SEATING PLANE N K E M F J 16 PL 0.25 (0.010) G D 16 PL 0.25 (0.010) T A M 16 9 1 8 M T B N SUFFIX PLASTIC PACKAGE CASE 648−08 ISSUE R C DIM A B C D F G H J K L M S L S K G D 16 PL 0.25 (0.010) M −T − SEATING PLANE M J T A M D SUFFIX PLASTIC SOIC PACKAGE CASE 751B−05 ISSUE J −A − 16 1 8 P 8 PL 0.25 (0.010) M B M G K F R X 45° C −T SEATING − PLANE D16PL 0.25 (0.010) J M M T B S A S http://onsemi.com 8 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15° 0° 1.01 0.51 INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 0.250 0.270 6.35 6.85 0.145 0.175 3.69 4.44 0.015 0.021 0.53 0.39 0.040 0.070 1.02 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.008 0.015 0.21 0.38 0.110 0.130 2.80 3.30 0.295 0.305 7.74 7.50 0° 10° 0° 10° 0.020 0.040 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B − INCHES MIN MAX 0.750 0.785 0.240 0.295 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15° 0° 0.020 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F S S −A − H DIM A B C D E F G J K L M N DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 7° 0° 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7° 0° 0.229 0.244 0.010 0.019 MC74HC390 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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