Dual Timing Circuit

MC3456
Dual Timing Circuit
The MC3456 dual timing circuit is a highly stable controller capable
of producing accurate time delays, or oscillation. Additional terminals
are provided for triggering or resetting if desired. In the time delay
mode of operation, the time is precisely controlled by one external
resistor and capacitor per timer. For astable operation as an oscillator,
the free running frequency and the duty cycle are both accurately
controlled with two external resistors and one capacitor per timer. The
circuit may be triggered and reset on falling waveforms, and the output
structure can source or sink up to 200 mA or drive MTTL circuits.
DUAL TIMING CIRCUIT
SEMICONDUCTOR
TECHNICAL DATA
Direct Replacement for NE556/SE556 Timers
Timing from Microseconds through Hours
Operates in Both Astable and Monostable Modes
Adjustable Duty Cycle
High Current Output can Source or Sink 200 mA
Output can Drive MTTL
Temperature Stability of 0.005% per °C
Normally “On” or Normally “Off” Output
Dual Version of the Popular MC1455 Timer
1.0 k
3
4
2
0.1 μF
5
0.01μF
8
1/2
MC3456
1
6
R
MT1
G
20 M
7
1.0 μF
C
1N4003
−10 V
t = 1.1; R and C = 22 sec
Time delay (t) is variable by
changing R and C (see Figure 16).
1N4740
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO−14)
Load
MT2
10 k
P SUFFIX
PLASTIC PACKAGE
CASE 646
117 Vac/60 Hz
•
•
•
•
•
•
•
•
•
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3.5 k
250 V
PIN CONNECTIONS
−
10 μF
+
Figure 1. 22 Second Solid State Time Delay Relay Circuit
Discharge A
1
14
VCC
Threshold A
2
13
Discharge B
Control A
3
12
Threshold B
Reset A
4
11
Control B
Output A
5
10
Reset B
Trigger A
6
9
Output B
Gnd
7
8
Trigger B
(Top View)
ORDERING INFORMATION
Device
MC3456P
NE556D
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 4
1
Operating
Temperature Range
0° to +70°C
Package
Plastic DIP
SO−14
Publication Order Number:
MC3456/D
MC3456
VCC
14
2 (12)
Threshold
5k
+
Comp
A
−
3 (11)
Control Voltage
1 (13)
Trigger
6 (8)
+
0.01 μF
Flip
R Flop
Q
5k
+
Comp
−B
Discharge
S Inhibit/
Reset
5 (9)
7
Control
Voltage
4
8
VCC
1/2
MC3456
VO
700
7
Discharge
Threshold
6
Output
5k
Gnd
Reset
5
3
Output
VCC
ICC
VR
Gnd
1
ISink
ISource
Trigger
Ith
2.0 k
VS
2
4 (10)
Reset
Test circuit for measuring DC parameters (to set output and
measure parameters):
a) When VS w 2/3 VCC, VO is low.
b) When VS v1/3 VCC, VO is high.
c) When VO is low, Pin 7 sinks current. To test for Reset, set VO high,
c) apply Reset voltage, and test for current flowing into Pin 7. When Reset
c) is not in use, it should be tied to VCC.
Figure 2. Block Diagram (1/2 Shown)
Figure 3. General Test Circuit
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)
Symbol
Value
Unit
Power Supply Voltage
Rating
VCC
+18
Vdc
Discharge Current
Idis
200
mA
Power Dissipation (Package Limitation)
P Suffix, Plastic Package, Case 646
Derate above TA = +25°C
D Suffix, Plastic Package, Case 751
Derate above TA = +25°C
PD
625
5.0
1.0
8.0
mW
mW/°C
W
mW/°C
Operating Ambient Temperature Range
TA
0 to +70
°C
Storage Temperature Range
Tstg
−65 to +150
°C
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2
MC3456
ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = +15 V, unless otherwise noted.)
Symbol
Min
Typ
Max
Supply Voltage
Characteristics
VCC
4.5
−
16
Supply Current
VCC = 5.0 V, RL = ∞
VCC = 15 V, RL = ∞ Low State, (Note 1)
ICC
Timing Error (Note 2)
Monostable Mode (RA = 2.0 kΩ; C = 0.1 μF)
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage
Astable Mode (RA = RB = 2.0 kΩ to 100 kΩ; C = 0.01 μF)
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage
Threshold Voltage
Vth
Trigger Voltage
VCC = 15 V
VCC = 5.0 V
VT
Unit
V
mA
−
−
6.0
20
12
30
−
−
−
0.75
50
0.1
−
−
−
%
PPM/°C
%/V
−
−
−
2.25
150
0.3
−
−
−
%
PPM/°C
%/V
−
2/3
−
xVCC
−
−
5.0
1.67
−
−
V
Trigger Current
IT
−
0.5
−
μA
Reset Voltage
VR
0.4
0.7
1.0
V
Reset Current
IR
−
0.1
−
mA
Threshold Current (Note 3)
Ith
−
0.03
0.1
μA
9.0
2.6
10
3.33
11
4.0
−
−
−
−
0.1
0.4
2.0
2.5
0.25
0.75
2.75
−
−
0.25
0.35
Control Voltage Level
VCC = 15 V
VCC = 5.0 V
VCL
Output Voltage Low
(VCC = 15 V)
ISink = 10 mA
ISink = 50 mA
ISink = 100 mA
ISink = 200 mA
(VCC = 5.0 V)
ISink = 5.0 mA
VOL
Output Voltage High
(ISource = 200 mA)
VCC = 15 V
(ISource = 100 mA)
VCC = 15 V
VCC = 5.0 V
VOH
Toggle Rate RA = 3.3 kΩ, RB = 6.8 kΩ, C = 0.003 μF (Figure 17, 19)
V
V
V
−
12.5
−
12.75
2.75
13.3
3.3
−
−
−
−
100
−
kHz
Idis
−
20
100
nA
Rise Time of Output
tOLH
−
100
−
ns
Fall Time of Output
tOHL
−
100
−
ns
−
−
−
1.0
±10
0.2
2.0
−
0.5
%
ppm/°C
%/V
Discharge Leakage Current
Matching Characteristics Between Sections
Monostable Mode
Initial Timing Accuracy
Timing Drift with Temperature
Drift with Supply Voltage
NOTES: 1. Supply current is typically 1.0 mA less for each output which is high.
2. Tested at VCC = 5.0 V and VCC = 15 V.
3. This will determine the maximum value of RA + RB for 15 V operation. The maximum total R = 20 mΩ.
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3
MC3456
10
ICC , SUPPLY CURRENT (mA)
150
PW, PULSE WIDTH (ns MIN)
125
100
75
0°C
50
25°C
70°C
25
0
0
0.1
0.2
0.3
25°C
8.0
6.0
4.0
2.0
0
5.0
0.4
10
15
VT(min), MINIMUM TRIGGER VOLTAGE (X VCC = Vdc)
VCC, SUPPLY VOLTAGE (Vdc)
Figure 4. Trigger Pulse Width
Figure 5. Supply Current
10
2.0
1.8
1.6
25°C
25°C
1.0
VOL, (Vdc)
VCC −VOH (Vdc)
1.4
1.2
1.0
0.8
0.1
0.6
5.0 V ≤ VCC ≤ 15 V
0.4
0.2
0
1.0
2.0
5.0
10
20
50
0.01
1.0
100
2.0
5.0
10
20
ISource (mA)
ISink (mA)
Figure 6. High Output Voltage
Figure 7. Low Output Voltage
50
100
50
100
(@ VCC = 5.0 Vdc)
1.0
1.0
VOL, (Vdc)
10
VOL, (Vdc)
10
25°C
0.1
0.01
1.0
25°C
0.1
2.0
5.0
10
20
50
0.01
1.0
100
2.0
5.0
10
20
ISink (mA)
ISink (mA)
Figure 8. Low Output Voltage
Figure 9. Low Output Voltage
(@ VCC = 10 Vdc)
(@ VCC = 15 Vdc)
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4
MC3456
t d, DELAY TIME NORMALIZED
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0
5.0
10
15
1.010
1.005
1.000
0.995
0.990
0.985
− 75
20
− 50
− 25
0
25
50
75
100
VCC, SUPPLY VOLTAGE (Vdc)
TA, AMBIENT TEMPERATURE (°C)
Figure 10. Delay Time versus Supply Voltage
Figure 11. Delay Time versus Temperature
300
t pd , PROPAGATION DELAY TIME (ns)
t d, DELAY TIME NORMALIZED
1.015
250
200
150
0°C
100
70°C
25°C
50
0
0
0.1
0.2
0.3
VT(min), MINIMUM TRIGGER VOLTAGE (x VCC = Vdc)
Figure 12. Propagation Delay
versus Trigger Voltage
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5
0.4
125
MC3456
Control Voltage
Threshold
Comparator
Trigger
Comparator
VCC
4.7 k
830
4.7 k
Flip−Flop
1.0 k
Output
6.8k
5.0 k
Threshold
7.0 k
3.9 k
Output
10 k
c
cb
e
5.0 k
b
4.7 k
Trigger
220
Reset
Reset
Discharge
Gnd
100 k
4.7 k
5.0 k
Discharge
100
Figure 13. 1/2 Representative Circuit Schematic
GENERAL OPERATION
comparator output triggers the flip−flop so that it’s output
sets low. This turns the capacitor discharge transistor “off”
and drives the digital output to the high state. This condition
allows the capacitor to charge at an exponential rate which
is set by the RC time constant. When the capacitor voltage
reaches 2/3 VCC the threshold comparator resets the
flip−flop. This action discharges the timing capacitor and
returns the digital output to the low state. Once the flip−flop
has been triggered by an input signal, it cannot be retriggered
until the present timing period has been completed. The time
that the output is high is given by the equation t = 1.1 RA C.
Various combinations of R and C and their associated times
are shown in Figure 14. The trigger pulse width must be less
than the timing period.
A reset pin is provided to discharge the capacitor thus
interrupting the timing cycle. As long as the reset pin is low,
the capacitor discharge transistor is turned “on” and
prevents the capacitor from charging. While the reset
voltage is applied the digital output will remain the same.
The reset pin should be tied to the supply voltage when not
in use.
The MC3456 is a dual timing circuit which uses as its
timing elements an external resistor/capacitor network. It
can be used in both the monostable (one shot) and astable
modes with frequency and duty cycle, controlled by the
capacitor and resistor values. While the timing is dependent
upon the external passive components, the monolithic
circuit provides the starting circuit, voltage comparison and
other functions needed for a complete timing circuit.
Internal to the integrated circuit are two comparators, one for
the input signal and the other for capacitor voltage; also a
flip−flop and digital output are included. The comparator
reference voltages are always a fixed ratio of the supply
voltage thus providing output timing independent of supply
voltage.
Monostable Mode
In the monostable mode, a capacitor and a single resistor
are used for the timing network. Both the threshold terminal
and the discharge transistor terminal are connected together
in this mode (refer to circuit Figure 15). When the input
voltage to the trigger comparator falls below 1/3 VCC the
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6
MC3456
C, CAPACITANCE ( μ F)
100
+VCC (5.0 V to 15 V)
10
RL
Reset
4 (10)
1.0
VCC
14
5 (9)
1/2
RL
0.01
0.001
10 μs
10 ms 100 ms
td, TIME DELAY (s)
1.0
10
Threshold
MC3456
6 (8)
C
3 (11)
Trigger
7
100 μs 1.0 ms
Discharge
1 (13)
2 (12)
Output
0.1
RA
Control
Voltage
0.01 μF
Gnd
100
Pin numbers in parenthesis ( ) indicate B−Channel
Figure 15. Monostable Circuit
Figure 14. Time Delay
+VCC (5.0 to 15 V)
RL
Reset
4 (10)
Output
5 (9)
RL
Trigger
RA
VCC
14
1/2
MC3456
1 (13)
Discharge
2 (12)
Threshold
Control
Voltage
6 (8)
7
Gnd
t = 50 μs/cm
(RA = 10 kΩ, C = 0.01 μF, RL = 1.0 kΩ, VCC = 15 V)
Figure 16. Monostable Waveforms
Figure 17. Astable Circuit
t = 20 μs/cm
(RA = 5.1 kΩ, C = 0.0 1 μF, RL = 1.0 kΩ, RB = 3.9 kΩ, VCC = 15 V)
Figure 18. Astable Waveforms
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7
RB
3 (11)
0.01 μF
C
MC3456
Astable Mode
In the astable mode the timer is connected so that it will
retrigger itself and cause the capacitor voltage to oscillate
between 1/3 VCC and 2/3 VCC (see Figure 17).
The external capacitor charges to 2/3 VCC through RA and
RB and discharges to 1/3 VCC through RB. By varying the
ratio of these resistors the duty cycle can be varied. The
charge and discharge times are independent of the supply
voltage.
The charge time (output high) is given by:
discharge current (Pin 7 current) within the maximum rating
of the discharge transistor (200 mA).
The minimum value of RA is given by:
C, CAPACITANCE ( μ F)
100
t1 = 0.695 (RA+RB) C
The discharge time (output low) by:
t2 = 0.695 (RB) C
Thus the total period is given by:
T = t1 + t2 = 0.695 (RA + 2RB) C
The frequency of oscillation is then: f =
1.44
1
=
T
(RA +2RB) C
10
1.0
0.1
0.01
(RA + 2 RB)
0.001
and may be easily found as shown in Figure 19.
The duty cycle is given by: DC =
VCC (Vdc)
VCC (Vdc)
≥
I7 (A)
0.2
RA ≥
0.1
RB
RA +2RB
1.0
10
100
1.0 k
10 k
f, FREE RUNNING FREQUENCY (Hz)
Figure 19. Free Running Frequency
To obtain the maximum duty cycle, RA must be as small as
possible; but it must also be large enough to limit the
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100
MC3456
APPLICATIONS INFORMATION
Tone Burst Generator
Dual Astable Multivibrator
For a tone burst generator, the first timer is used as a
monostable and determines the tone duration when
triggered by a positive pulse at Pin 6. The second timer is
enabled by the high output of the monostable. It is connected
as an astable and determines the frequency of the tone.
This dual astable multivibrator provides versatility not
available with single timer circuits. The duty cycle can be
adjusted from 5% to 95%. The two outputs provide two
phase clock signals often required in digital systems. It can
also be inhibited by use of either reset terminal.
+ 15 V
Reset
4
RT
14
VCC
14
VCC
RA
13 Discharge
6
Trigger
10
5
Trigger
1
Output
1/2
MC3456
Discharge
2
Reset
3
Control
Threshold
7
C1−
Gnd
MC3456
9
RB
12 Threshold
1/2
8 Trigger
11 Control
Output
0.01 μF
7
0.01 mF
Gnd
C2
Gnd
1.44
f=
(RA + 2RB) C
t = 1.1 RT C1
Figure 20. Tone Burst Generator
+15 V
R1
Reset
4
10 k
14
2
1N914
10 k
1N914
5
Output
1/2
1
MC3456
Discharge
C1
Control
Voltage
0.001
6
0.001
7
8
12
1/2
MC3456
Output
13
Discharge
11
Gnd
R2
Threshold
Trigger
Trigger
3
Reset
9
Output
Threshold
10
Control
Voltage
C2
Gnd
f=
0.91
for C1 = C2
(R1 + R2) C
Duty Cycle
R2
R1 + R2
Figure 21. Dual Astable Multivibrator
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MC3456
Pulse Width Modulation
Test Sequences
If the timer is triggered with a continuous pulse train in the
monostable mode of operation, the charge time of the
capacitor can be varied by changing the control voltage at
Pin 3. In this manner, the output pulse width can be
modulated by applying a modulating signal that controls the
threshold voltage.
Several timers can be connected to drive each other for
sequential timing. An example is shown in Figure 24 where
the sequence is started by triggering the first timer which
runs for 10 ms. The output then switches low momentarily
and starts the second timer which runs for 50 ms and so forth.
+VCC (5.0 V to 15 V)
Modulation Input Voltage 5.0 V/cm
RL
Clock Input Voltage
5.0 V/cm
RA
4 (10)
Reset
VCC
Discharge
Output
Output
1 (13)
5 (9)
Threshold
1/2
MC3456
Output Voltage
5.0 V/cm
Trigger
Capacitor Voltage
5.0 V/cm
Clock
Input
14
C
2 (12)
Control
3 (11)
6 (8)
Gnd
Modulation
Input
7
t = 0.5 ms/cm
(RA = 10 kW, C = 0.02 mF, VCC = 15 V)
Figure 22. Pulse Width Modulation Waveforms
Figure 23. Pulse Width Modulation Circuit
VCC (5.0 V to 15 V)
9.1 k
27 k
VCC
Threshold
0.01 μF
1/2
Control
Discharge
Reset
VCC
Threshold
Discharge
MC3456
27 k
9.1 k
Reset
Control
1/2
Discharge
0.01 μF
Control
1/2
Trigger
Output
Output
0.001 μF
Gnd
Gnd
1.0 μF
Reset
MC3456
0.001 μF
Trigger
VCC
Threshold
MC3456
Trigger
Output
0.01 μF
50 k
Gnd
5.0 μF
5.0 μF
Load
Load
Figure 24. Sequential Timing Circuit
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10
Load
MC3456
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 646−06
ISSUE M
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
8
B
1
7
A
F
L
N
C
−T−
SEATING
PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M
M
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11
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10_
0.38
1.01
MC3456
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC PACKAGE
CASE 751A−03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
14
8
−B−
1
0.25 (0.010)
7
G
D 14 PL
0.25 (0.010)
T B
M
F
J
M
K
M
B
M
R X 45 _
C
−T−
SEATING
PLANE
P 7 PL
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MC3456/D
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