5V ECL Triple 2:1 Multiplexer

MC100EL59
5VECL Triple 2:1
Multiplexer
Description
The MC100EL59 is a triple 2:1 multiplexer with differential
outputs. The output data of the multiplexers can be controlled
individually via the select inputs or as a group via the common select
input. The flexible selection scheme makes the device useful for both
data path and random logic applications.
The 100 Series Contains Temperature Compensation
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Features
• Individual or Common Select Controls
• 500 ps Typical Propagation Delays
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
SO−20
WB SUFFIX
CASE 751D
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
•
•
•
•
•
•
•
•
with VEE = −4.2 V to −5.7 V
Q Output will Default LOW with Inputs Open or at VEE
Internal Input Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
Pb−Free = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 1.125 in,
Oxygen Index: 28 to 34
Transistor Count = 182 devices
Pb−Free Package is Available*
MARKING DIAGRAM*
20
100EL59
AWLYYWWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 3
1
Publication Order Number:
MC100EL59/D
MC100EL59
VCC
Q0
Q0
VCC
Q1
Q1
VCC
Q2
Q2
VEE
20
19
18
17
16
15
14
13
12
11
9
10
1
1
0
2
1
3
COM_SEL D0a
D0b
4
0
1
5
SEL0 D1a
0
6
7
8
D1b
SEL1
D2a
D2b SEL2
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout: 20−Lead SOIC (Top View)
Table 1. PIN DESCRIPTION
PIN
FUNCTION
D0a−D2a
D0b−D2b
SEL0−SEL2
COM_SEL
Q0−Q2; Q0−Q2
VCC
VEE
ECL Input Data a*
ECL Input Data b*
ECL Individual Select Input*
ECL Common Select Input*
ECL Differential Outputs
Positive Supply
Negative Supply
*Pins will default LOW when left open.
Table 2. TRUTH TABLE
SEL*
DATA
H
L
a
b
*Pins will default LOW when left open.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6 to 0
−6 to 0
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−20
SOIC−20
90
60
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−20
30 to 35
°C/W
Tsol
Wave Solder
265
265
°C
Pb
Pb−Free
VI VCC
VI VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
MC100EL59
Table 4. PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V (Note 1)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
130
156
130
156
130
156
mA
IEE
Power Supply Current
27
32
27
32
27
32
mA
VOH
Output HIGH Voltage (Note 2)
3915
3995
4120
3975
4045
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 2)
3170
3305
3445
3190
3295
3380
3190
3295
3380
mV
VIH
Input HIGH Voltage
3835
4120
3835
4120
3835
4120
mV
VIL
Input LOW Voltage
3190
3525
3190
3525
3190
3525
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
150
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 5. NECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −5.0 V (Note 3)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
27
32
Min
85°C
Typ
Max
27
32
Min
Typ
Max
Unit
27
32
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 4)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
VIH
Input HIGH Voltage
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage
−1810
−1475
−1810
−1475
−1810
−1475
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
150
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V.
4. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 6. AC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −5.0 V (Note 5)
−40°C
Symbol
Characteristic
tPLH
tPHL
Propagation
Delay
DATA to Q/Q
SEL to Q/Q
COM_SEL to Q/Q
tskew
Output−Output Skew
tJITTER
Cycle−to−Cycle Jitter
tr
tf
Output Rise/Fall Times Q
(20% − 80%)
Min
Typ
340
340
340
Any Dn, Dm to Q
25°C
Max
Min
690
690
690
340
340
340
Typ
100
Max
Min
690
690
690
340
340
340
200
Max
Unit
690
690
690
ps
100
TBD
540
Typ
100
TBD
200
85°C
TBD
540
200
ps
ps
540
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. VEE can vary +0.8 V / −0.5 V.
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3
MC100EL59
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC100EL59DW
SOIC−20
38 Units / Rail
MC100EL59DWG
SOIC−20
(Pb−Free)
38 Units / Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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4
MC100EL59
PACKAGE DIMENSIONS
SO−20 WB
CASE 751D−05
ISSUE G
A
20
q
X 45 _
E
h
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
C
T
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Sales Representative
MC100EL59/D
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