8-Line Multiplexer

MC10164
8-Line Multiplexer
The MC10164 is a high speed, low power eight–channel data
selector which routes data present at one–of–eight inputs to the output.
The data is routed according to the three bit code present on the
address inputs. An enable input is provided for easy bit expansion.
• PD = 310 mW typ/pkg (No Load)
• tpd = 3.0 ns typ (Data to Output)
• tr, tf = 2.0 ns typ (20%–80%)
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MARKING
DIAGRAMS
16
LOGIC DIAGRAM
CDIP–16
L SUFFIX
CASE 620
A 7
MC10164L
AWLYYWW
1
16
B 9
C 10
Enable 2
PDIP–16
P SUFFIX
CASE 648
15 Z
MC10164P
AWLYYWW
X06
1
1
X15
PLCC–20
FN SUFFIX
CASE 775
X24
X33
X411
A
WL
YY
WW
X512
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
X613
X714
TRUTH TABLE
10164
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
DIP PIN ASSIGNMENT
VCC2
1
16
VCC1
ENABLE
2
15
Z
ENABLE
C
B
A
Z
X3
3
14
X7
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
X0
X1
X2
X3
X2
4
13
X6
X1
5
12
X5
X0
6
11
X4
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
X4
X5
X6
X7
A
7
10
C
VEE
8
9
B
H
X
X
X
L
ADDRESS INPUTS
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Package
Shipping
MC10164L
CDIP–16
25 Units / Rail
MC10164P
PDIP–16
25 Units / Rail
MC10164FN
PLCC–20
46 Units / Rail
Publication Order Number:
MC10164/D
MC10164
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Symbol
Pin
Under
Test
Power Supply Drain Current
IE
8
83
IinH
2
425
Input Current
–30°C
Min
+25°C
Max
Min
+85°C
Typ
Max
Max
Unit
60
75
Min
83
mAdc
265
265
µAdc
0.5
µAdc
IinL
4
0.5
Output Voltage
Logic 1
VOH
15
–1.060
–0.890
–0.960
–0.810
–0.890
0.3
–0.700
Vdc
Output Voltage
Logic 0
VOL
15
–1.890
–1.675
–1.850
–1.650
–1.825
–1.615
Vdc
Threshold Voltage
Logic 1
VOHA
15
–1.080
Threshold Voltage
Logic 0
VOLA
15
–0.980
–0.910
–1.655
Vdc
–1.630
–1.595
Switching Times (50Ω Load)
Propagation Delay
Vdc
ns
t4+15+
t4–15–
t7+15+
t7–15–
t2+15–
t2–15+
15
15
15
15
15
15
1.5
1.5
1.9
1.9
0.9
0.9
4.9
4.9
6.5
6.5
3.5
3.5
1.5
1.5
2.0
2.0
1.0
1.0
3.0
3.0
4.0
4.0
2.0
2.0
4.7
4.7
6.2
6.2
3.1
3.1
1.6
1.6
2.2
2.2
1.0
1.0
5.0
5.0
6.7
6.7
3.3
3.3
Rise Time
(20 to 80%)
t+
15
0.9
3.3
1.1
2.0
3.3
1.2
3.6
Fall Time
(20 to 80%)
t–
15
0.9
3.3
1.1
2.0
3.3
1.2
3.6
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
Characteristic
Power Supply Drain Current
Input Current
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
–30°C
–0.890
–1.890
–1.205
–1.500
–5.2
+25°C
–0.810
–1.850
–1.105
–1.475
–5.2
+85°C
–0.700
–1.825
–1.035
–1.440
–5.2
Symbol
Pin
Under
Test
IE
8
IinH
2
IinL
4
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmin
VIHAmin
VILAmax
4
4
VEE
(VCC)
Gnd
8
1,16
8
1,16
8
1,16
Output Voltage
Logic 1
VOH
15
4,9
8
1,16
Output Voltage
Logic 0
VOL
15
9
8
1,16
Threshold Voltage
Logic 1
VOHA
15
4,9
2
8
1,16
Threshold Voltage
Logic 0
VOLA
15
9
2
8
1,16
+1.11V
Pulse In
Pulse Out
–3.2 V
+2.0 V
t4+15+
t4–15–
t7+15+
t7–15–
t2+15–
t2–15+
15
15
15
15
15
15
9
9
5
5
7,5
7,5
4
4
7
7
2
2
15
15
15
15
15
15
8
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
1,16
Switching Times
(50Ω Load)
Propagation Delay
Rise Time
(20 to 80%)
t+
15
9
4
15
8
1,16
Fall Time
(20 to 80%)
t–
15
9
4
15
8
1,16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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2
MC10164
APPLICATION INFORMATION
Figure 1 illustrates how a 1–of–64 line multiplexer can be
built with eight MC10164’s wire ORed at their outputs and
one MC10161 to drive the enables on each multiplexer,
without speed degradation over a single MC10164 being
experienced.
The MC10164 can be used wherever data multiplexing or
parallel to serial conversion is desirable. Full parallel gating
permits equal delays through any data path. The output of
the MC10164 incorporates a buffer gate with eight data
inputs and an enable. A high level on the enable forces the
output low. The MC10164 can be connected directly to a
data bus, due to its open emitter output and output enable.
FIGURE 1 — 1–OF–64 LINE MULTIPLEXER
E
A B C
MC10164
E
A
B
C
MC10164
E
A
B
MSB
Q7
Q6
E
A
B
MC10161
9
MC10164
Q1
LSB
Zout
Q3
Q2
7
Zout
C
Q5
Q4
Zout
C
MC10164
14
Zout
E
A
B
C
Q0
MC10164
E
The Bit chosen is dependent on six–bit
code present on inputs 7, 9, 14 of the
MC10161 and the A, B, C inputs of the
MC10164.
A
B
C
MC10164
E
A
B
A
B
3
Zout
C
MC10164
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Zout
C
MC10164
E
Zout
Zout
MC10164
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
0.007 (0.180)
B
Y BRK
–N–
M
T L-M
0.007 (0.180)
U
M
N
S
T L-M
S
G1
0.010 (0.250)
S
N
S
D
–L–
–M–
Z
W
20
D
1
X
V
S
T L-M
S
N
S
VIEW D–D
A
0.007 (0.180)
M
T L-M
S
N
S
R
0.007 (0.180)
M
T L-M
S
N
S
Z
0.007 (0.180)
H
M
T L-M
S
N
S
K1
K
C
E
F
0.004 (0.100)
G
J
–T–
VIEW S
G1
0.010 (0.250) S T L-M
S
N
S
0.007 (0.180)
M
T L-M
S
VIEW S
SEATING
PLANE
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
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4
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
--0.025
--0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
--0.020
2
10 0.310
0.330
0.040
---
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
--0.64
--8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2
10 7.88
8.38
1.02
---
N
S
MC10164
PACKAGE DIMENSIONS
–A–
16
9
1
8
–B–
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
S
T A
M
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5
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
--0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0
15 0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
--5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0
15 0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
10 0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
10 0.51
1.01
MC10164
Notes
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6
MC10164
Notes
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7
MC10164
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
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PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
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8
MC10164/D
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