Dual 4 to 1 Multiplexer

MC10174
Dual 4 to 1 Multiplexer
The MC10174 is a high speed dual channel multiplexer with output
enable capability. The select inputs determine one of four active data
inputs for each multiplexer. An output enable forces both outputs low
when in the high state.
• PD = 305 mW typ/pkg (No Load)
• tpd = 3.5 ns typ (Dta to output)
• tr, tf = 2.0 ns typ (20%–80%)
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MARKING
DIAGRAMS
16
LOGIC DIAGRAM
CDIP–16
L SUFFIX
CASE 620
D003
MC10174L
AWLYYWW
1
16
D015
PDIP–16
P SUFFIX
CASE 648
2 Q0
D024
MC10174P
AWLYYWW
D036
1
PLCC–20
FN SUFFIX
CASE 775
A 7
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
B9
A
WL
YY
WW
ENABLE 14
D1013
1
10174
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
DIP PIN ASSIGNMENT
D1111
15 Q1
D1212
D1310
TRUTH TABLE
ENABLE
ADDRESS INPUTS
OUTPUTS
E
B
A
Q0
Q1
H
X
X
L
L
L
L
L
D00
D10
L
L
H
D01
D11
L
H
L
D02
D12
L
H
H
D03
D13
VCC1
1
16
VCC2
Q0
2
15
Q1
DO0
3
14
ENABLE
DO2
4
13
D10
DO1
5
12
D12
DO3
6
11
D11
A
7
10
D13
VEE
8
9
B
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Package
Shipping
MC10174L
CDIP–16
25 Units / Rail
MC10174P
PDIP–16
25 Units / Rail
MC10174FN
PLCC–20
46 Units / Rail
Publication Order Number:
MC10174/D
MC10174
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Symbol
Pin
Under
Test
Power Supply Drain Current
IE
8
80
IinH
4
14
350
525
IinL
4
0.5
VOH
15
–1.060
–0.890
–0.960
–0.810
–0.890
–0.700
Vdc
–1.675
–1.850
–1.650
–1.825
–1.615
Vdc
Input Current
–30°C
Min
+25°C
Max
Min
+85°C
Typ
Max
Min
58
73
80
Max
220
330
220
330
0.5
Output Voltage
Logic 1
Output Voltage
Logic 0
VOL
15
–1.890
Threshold Voltage
Logic 1
VOHA
15
–1.080
Threshold Voltage
Logic 0
VOLA
15
t13+15+
t13–15–
t7+15–
t7–15+
t14+15–
t14–15+
15
15
15
15
15
15
1.4
1.4
1.9
1.9
1.0
1.0
5.0
5.0
6.6
6.6
3.3
3.3
1.5
1.5
2.0
2.0
1.0
1.0
3.5
3.5
5.0
5.0
2.0
2.0
4.7
4.7
6.2
6.2
3.1
3.1
1.4
1.4
2.1
2.1
0.9
0.9
5.0
5.0
6.6
6.6
3.4
3.4
–0.910
–1.655
Vdc
–1.630
–1.595
Switching Times (50Ω Load)
Propagation Delay
µAdc
µAdc
0.3
–0.980
Unit
mAdc
Vdc
ns
Rise Time
(20 to 80%)
t+
15
1.0
3.4
1.1
2.0
3.3
1.1
3.6
Fall Time
(20 to 80%)
t–
15
1.0
3.4
1.1
2.0
3.3
1.1
3.6
ELECTRICAL CHARACTERISTICS (continued)
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the
test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted
on a printed circuit board and transverse air flow
greater than 500 linear fpm is maintained. Outputs
are terminated through a 50–ohm resistor to –2.0
volts. Test procedures
rocedures are shown for only one
gate. The other gates are tested in the same manner.
Characteristic
Power Supply Drain Current
Input Current
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
–30°C
–0.890
–1.890
–1.205
–1.500
–5.2
+25°C
–0.810
–1.850
–1.105
–1.475
–5.2
+85°C
–0.700
–1.825
–1.035
–1.440
–5.2
Symbol
Pin
Under
Test
IE
8
IinH
4
14
IinL
4
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmin
VIHAmin
VILAmax
4
14
4
VEE
(VCC)
Gnd
8
1, 16
8
8
1, 16
1, 16
8
1, 16
Output Voltage
Logic 1
VOH
15
13
8
1, 16
Output Voltage
Logic 0
VOL
15
14
8
1, 16
Threshold Voltage
Logic 1
VOHA
15
8
1, 16
Logic 0
VOLA
15
Threshold Voltage
Switching Times
(50Ω Load)
Propagation Delay
13
8
1, 16
+1.11V
Pulse In
14
Pulse Out
–3.2 V
+2.0 V
15
15
15
15
15
15
8
8
8
8
8
8
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
t13+15+
t13–15–
t7+15–
t7–15+
t14+15–
t14–15+
15
15
15
15
15
15
11
11
13
13
13
13
7
7
14
14
Rise Time
(20 to 80%)
t+
15
13
14
15
8
1, 16
Fall Time
(20 to 80%)
t–
15
13
14
15
8
1, 16
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2
MC10174
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
0.007 (0.180)
B
Y BRK
–N–
M
T L-M
0.007 (0.180)
U
M
N
S
T L-M
S
G1
0.010 (0.250)
S
N
S
D
–L–
–M–
Z
W
20
D
1
X
V
S
T L-M
S
N
S
VIEW D–D
A
0.007 (0.180)
M
T L-M
S
N
S
R
0.007 (0.180)
M
T L-M
S
N
S
Z
0.007 (0.180)
H
M
T L-M
S
N
S
K1
K
C
E
F
0.004 (0.100)
G
J
–T–
VIEW S
G1
0.010 (0.250) S T L-M
S
N
S
0.007 (0.180)
M
T L-M
S
VIEW S
SEATING
PLANE
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
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3
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
--0.025
--0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
--0.020
2
10 0.310
0.330
0.040
---
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
--0.64
--8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2
10 7.88
8.38
1.02
---
N
S
MC10174
–A–
16
9
1
8
–B–
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
S
T A
M
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
--0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0
15 0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
--5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0
15 0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
10 0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
10 0.51
1.01
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
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P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: [email protected]
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Phone: 81–3–5740–2700
Email: [email protected]
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For additional information, please contact your local
Sales Representative.
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4
MC10174/D
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