Dual Binary to 1-4 Decoder (Low)

MC10171
Dual Binary to 1-4 Decoder
(Low)
The MC10171 is a binary coded 2 line to dual 4 line decoder with
selected outputs low. With either E0 or E1 high, the corresponding
selected 4 outputs are high. The common enable E, when high, forces
all outputs high.
• PD = 325 mW typ/pkg (No Load)
• tpd = 4.0 ns typ
• tr, tf = 2.0 ns typ (20%–80%)
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MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
LOGIC DIAGRAM
E0 14
MC10171L
AWLYYWW
10 Q0 3
1
16
11 Q0 2
PDIP–16
P SUFFIX
CASE 648
12 Q0 1
MC10171P
AWLYYWW
A9
1
1
13 Q0 0
PLCC–20
FN SUFFIX
CASE 775
3 Q1 3
B7
4 Q1 2
5 Q1 1
E 15
A
WL
YY
WW
6 Q1 0
E1 2
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
INPUTS
= Assembly Location
= Wafer Lot
= Year
= Work Week
DIP PIN ASSIGNMENT
TRUTH TABLE
ENABLE INPUTS
10171
AWLYYWW
OUTPUTS
VCC1
1
16
VCC2
E1
2
15
E
Q13
3
14
E0
E
E0
E1
A
B
Q10
Q11
Q12
Q13
Q00
Q01
Q02
Q03
Q12
4
13
Q00
L
L
L
L
L
L
H
L
L
L
L
L
H
X
L
L
L
L
H
L
X
L
L
H
H
L
L
X
L
H
L
H
L
L
X
L
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
Q11
5
12
Q01
Q10
6
11
Q02
B
7
10
Q03
VEE
8
9
A
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Package
Shipping
MC10171L
CDIP–16
25 Units / Rail
MC10171P
PDIP–16
25 Units / Rail
MC10171FN
PLCC–20
46 Units / Rail
Publication Order Number:
MC10171/D
MC10171
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Symbol
Pin
Under
Test
Power Supply Drain Current
IE
8
85
IinH
14
350
Input Current
–30°C
Min
+25°C
Max
Min
+85°C
Typ
Max
Max
Unit
65
77
85
mAdc
220
220
µAdc
µAdc
IinL
14
0.5
VOH
6
13
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
Vdc
Logic 0
VOL
13
–1.890
–1.675
–1.850
–1.650
–1.825
–1.615
Vdc
Logic 1
VOHA
6
13
–1.080
–1.080
Logic 0
VOLA
6
13
Output Voltage
Logic 1
Output Voltage
Threshold Voltage
Threshold Voltage
0.5
Min
0.3
–0.980
–0.980
–0.910
–0.910
–1.655
–1.655
–1.630
–1.630
Vdc
–1.595
–1.595
Switching Times (50Ω Load)
Propagation Delay
Vdc
ns
t7+6+
t7–6–
t7+13+
t7–13–
6
6
13
13
1.5
1.5
1.5
1.5
6.2
6.2
6.2
6.2
1.5
1.5
1.5
1.5
4.0
4.0
4.0
4.0
6.0
6.0
6.0
6.0
1.5
1.5
1.5
1.5
6.4
6.4
6.4
6.4
Rise Time
(20 to 80%)
t6+
t13+
6
13
1.0
1.0
3.3
3.3
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.4
3.4
Fall Time
(20 to 80%)
t6–
t13–
6
13
1.0
1.0
3.3
3.3
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.4
3.4
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2
MC10171
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
Characteristic
Power Supply Drain Current
Input Current
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
–30°C
–0.890
–1.890
–1.205
–1.500
–5.2
+25°C
–0.810
–1.850
–1.105
–1.475
–5.2
+85°C
–0.700
–1.825
–1.035
–1.440
–5.2
Symbol
Pin
Under
Test
VIHmax
IE
8
2,7,9,14,15
IinH
14
14
IinL
14
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VILmin
VIHAmin
VEE
(VCC)
Gnd
8
1, 16
8
1, 16
8
1, 16
8
8
1, 16
1, 16
8
1, 16
8
8
1, 16
1, 16
7
9
8
8
1, 16
1, 16
VILAmax
14
Output Voltage
Logic 1
VOH
6
13
Output Voltage
Logic 0
VOL
13
Threshold Voltage
Logic 1
VOHA
6
13
Threshold Voltage
Logic 0
VOLA
6
13
2,9,14,15
2,7,14,15
+0.31V
Pulse In
Pulse Out
–3.2 V
+2.0 V
t7+6+
t7–6–
t7+13+
t7–13–
6
6
13
13
2,9,14,15
2,9,14,15
2,9,14,15
2,9,14,15
7
7
7
7
6
6
13
13
8
8
8
8
1, 16
1, 16
1, 16
1, 16
Switching Times
15
15
2,7,9,14,15
15
15
(50Ω Load)
Propagation Delay
Rise Time
(20 to 80%)
t6+
t13+
6
13
7
7
6
13
8
8
1, 16
1, 16
Fall Time
(20 to 80%)
t6–
t13–
6
13
7
7
6
13
8
8
1, 16
1, 16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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3
MC10171
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
0.007 (0.180)
B
Y BRK
–N–
M
T L-M
0.007 (0.180)
U
M
N
S
T L-M
S
G1
0.010 (0.250)
S
N
S
D
–L–
–M–
Z
W
20
D
1
X
V
S
T L-M
S
N
S
VIEW D–D
A
0.007 (0.180)
M
T L-M
S
N
S
R
0.007 (0.180)
M
T L-M
S
N
S
Z
0.007 (0.180)
H
M
T L-M
S
N
S
K1
K
C
E
F
0.004 (0.100)
G
J
–T–
VIEW S
G1
0.010 (0.250) S T L-M
S
N
S
0.007 (0.180)
M
T L-M
S
VIEW S
SEATING
PLANE
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
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4
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
--0.025
--0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
--0.020
2
10 0.310
0.330
0.040
---
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
--0.64
--8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2
10 7.88
8.38
1.02
---
N
S
MC10171
PACKAGE DIMENSIONS
–A–
16
9
1
8
–B–
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
S
T A
M
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5
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
--0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0
15 0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
--5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0
15 0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
10 0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
10 0.51
1.01
MC10171
Notes
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6
MC10171
Notes
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7
MC10171
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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8
MC10171/D
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