Demonstration Note for CS5124 48 V to 5.0 V, 1.0 A Flyback Converter

CS5124DEMO/D
Demonstration Note for
CS5124 48 V to 5.0 V,
1.0 A Flyback Converter
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DEMONSTRATION NOTE
Features
• 36 to 75 VDC Input Voltage Range
• 5.0 V, 1.0 A Isolated Output
• 1″ × 1.6″ Footprint
• Up to 82% Efficiency
• Input Undervoltage Shutdown and Sleep Mode
• Remote Enable Input
• Overcurrent Protection
• Thermal Shutdown
Description
The CS5124 demonstration board is a fixed frequency,
isolated, 48 VDC to 5.0 VDC flyback converter. High
efficiency over a wide input voltage range is accomplished
by powering the CS5124 controller from a winding on the
flyback transformer. Short circuit, overload, and input
undervoltage protection are all accomplished by integrated
CS5124 circuitry. The demonstration board also
accomplishes bootstrapping, Soft Start and blanking with a
minimal number of discrete components.
Figure 1. CS5124 Demonstration Board
 Semiconductor Components Industries, LLC, 2003
January, 2003 - Rev. 3
1
Publication Order Number:
CS5124DEMO/D
CS5124DEMO/D
+48 VDC
+5.0 VDC
48 VRTN
Isolated
Return
ENABLE
Figure 2. Applications Diagram
ABSOLUTE MAXIMUM RATINGS*
Input/Output Name
Minimum
Maximum
Unit
-0.3
80
V
-
Internally Limited
A
ENABLE
-0.3
6.0
V
Isolated Return
-500
+500
VDC
+48 VDC
Output Current
*TA = 25°C
ELECTRICAL CHARACTERISTICS (TA = 25°C, 36 V to 75 V, unless otherwise specified.)
Test Conditions
Parameter
Min
Typ
Max
Unit
4.85
5.00
5.15
V
Output Voltage
0.15 A < IOUT < 1.0 A
Load Regulation
0.15 A < IOUT < 1.0 A, 36 V < VIN < 75 V
-
0.25
-
%
Line Regulation
0.15 A < IOUT < 1.0 A, 36 V < VIN < 75 V
-
0.15
-
%
Transient Regulation and Recovery Time
to within 1%
Step between 50% and 75% of maximum
load.
-
100
200
-
mV
µs
Output Ripple and Noise
75 VIN @ Full Load
(20 MHz BW)
-
200
20
-
mVp- p
mVrms
Efficiency
0.2 A Out
1.0 A Out
-
72
82
-
%
%
ENABLE (Turn-On) Threshold
-
2.30
2.63
2.76
V
ENABLE Hysteresis
-
170
185
200
mV
Sleep Mode (Turn-Of f) Threshold
-
1.50
1.83
2.30
V
Sleep Mode Hysteresis
-
35
85
150
mV
ENABLE Pin Source Current
ENABLE Pin = 0 V
-
-
1.0
mA
Sleep Mode Input Current
75 VIN
-
650
1000
µA
ENABLE/SS Time
Full Load
-
5.0
-
ms
Undervoltage Lockout (Turn-Of f)
-
28
31
33
V
Undervoltage Lockout (Turn-On)
-
31
33
35
V
Undervoltage Lockout Hysteresis
-
-
2.0
-
V
-
1.2
1.7
-
A
A
380
400
420
kHz
Overcurrent Limit Threshold
Oscillator Frequency
VIN = 36 V
VIN = 75 V
-
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CS5124DEMO/D
PIN DESCRIPTION
Pi Symbol
Pin
S b l
F
Function
ti
+48 VDC
36 to 75 VDC input.
48 VRTN
Return for +48 VDC input.
ENABLE
This pin is internally pulled up and performs the UVLO function if left open. Pull this pin to between 2.25 V
and 2.5 V to stop the converter from switching. Pull this pin to blow 1.5 V to put the converter in sleep mode.
+5.0 VDC
+5.0 VDC isolated output.
Isolated Return
Return for +5.0 VDC output and load.
OPERATING INSTRUCTIONS
Output Load
An external load is required for the demo board to run
normally at fixed frequency. If the demo board is run with
a load less than about 80 mA it will regulate the output at
5.0 V in hiccup mode.
Input Power
The converter is designed to run with an input voltage
between 36 VDC to 75 VDC. Approximately 180 mA of
current will be required for full load with a 36 V input.
L1
TP1
10 µH
ER-14.5/6
T1
R2
200 k
R1
510 k
BIAS
C1
0.1 µF
100 V
C2
1.5 µF
100 V
R5
17.4 k
Q1
ZVN3310A
TP6
R4
10 Ω
TP3
MBRD380CT
R3
47 Ω
TP2
R6
1.0 k
C3
0.022 µF
Q2
IRFR220
C4
0.47 µF
25 V
VCC
TP14
5VOUT
D2
TP7
C7
1000 pF
ENABLE
D1
BAS16LT1
DRAIN
VCC
BIAS
UVLO
SS
GND
GATE
IS
FB
U2
C7
0.01 µF
TP1
C6
0.01 µF
FB
TP9
TP8
5VOUT
IS
TP10
SS
48VRTN
R7
30.1 k
R8
0.39 Ω
U1
CS5124
36-75 VIN
C8
1000 pF
TPS5908
TP4
C5
47 µF
10 V
ISOLATED
RTN
TP12
R9
10 k
ISOLATED
RTN
TP5
48VRTN
TP13
Figure 3. Circuit Schematic
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3
CS5124DEMO/D
THEORY OF OPERATION
dead time of about 1.5 ms while C7 charges to 1.6 V. The
ramp-up time of the output voltage will last about 1-2 ms
depending on output load.
During hiccup mode the dead time will be about 1.4 ms
while C8 charges from 0.25 V to 1.6 V as shown in Figure 21.
ENABLE/UVLO
R2 and R5 form a divider for the UVLO function. If the
ENABLE pin of the supply is left open it will operate in
three modes depending on the input voltage. For VIN less
than 18 V the supply will be in sleep mode. For VIN
between approximately 18 V and 31 V the BIAS section is
operational and VCC is regulated to 8.0 V, but the PWM
section is disabled. If VIN exceeds 35 V the supply operates
normally.
C9 is included on the demonstration circuit to prevent
radiated noise from coupling to the ENABLE pin through
the ENABLE test point. This part may not be needed with
a more typical pcb layout.
The ENABLE pin can also be controlled by open
collector logic to perform an ENABLE function. When the
ENABLE pin is below 1.5 V the supply will be in sleep
mode and input current will be less than 1.0 mA.
Feedback
R7 and R9 divide the 5.0 V output to the 1.24 V reference
of U2. C6 and the Thevenin resistance of R7 and R9 set the
low frequency roll-off of U2. R6 sets the maximum current
through U2’s photodiode and adjusts gain. C3 provides
phase boost near the crossover frequency. C8 is primarily
for high frequency noise reduction.
DESIGN INFORMATION
Flyback Transformer
The transformer was designed to operate in continuous
and discontinuous conduction modes. Running in
discontinuous conduction mode at light loads allows for a
smaller core size, and by requiring a higher peak current
offers a larger current sense signal. Operating in continuous
conduction mode during at heavy loads reduces ripple
current in the output filter capacitor.
The transformer also runs at less than 50% duty cycle
under all conditions. This eliminates the need to choose the
transformer inductance to meet slope compensation criteria
and in a continuous flyback converter lower duty cycle
means lower output filter capacitor ripple.
The VCC flyback winding powers the controller and is
clamped to a voltage proportional to the secondary voltage.
If the initial turn-off spike is snubbed this winding will
provide a regulated VCC voltage. To provide VCC power
from the flyback winding rather than the bias circuit during
normal operation, the number of turns should be chosen to
to provide more than 9.0 V under operating conditions.
VCC Bias
R1 provides a pull-up to turn Q1 on and the BIAS pin
sinks current to regulate VCC or turn off Q1. When the IC is
operational, but not powered by the flyback winding, VCC
will be regulated to 8.0 V by the BIAS pin and Q1. During
normal operation, when sufficient energy to power the
controller is available from the flyback winding, VCC rises
above 8.0 V and the BIAS pin turns Q1 off.
The BIAS pin and associated components form a high
impedance node. Care should be taken during pcb layout to
avoid connections that could couple noise into this node.
Current Sensing
R8 is the current sense resistor. The turn-on spikes,
shown in Figures 16-18, are blanked internally by the
CS5124.
During heavy load conditions the primary current is
pulse by pulse limited as shown in Figure 19. Under
conditions where the current sense pin measures high
currents with fast rise-times the CS5124 second threshold
will be exceeded the converter will enter a low duty cycle
hiccup mode as shown in Figures 20 and 21. The CS5124
Demonstration Board typically reaches this condition only
when the input voltage is greater than 65 V and there is a
low impedance short across the output pins.
Flyback Transformer Design Procedure
1. Choose duty cycle less than 50% at low line. For a
400 kHz nominal operating frequency choose
TON = 1.1 µs and TOFF = 1.4 µs with 36 VIN.
2. Choose primary to secondary ratio.
1.1 s
T
V
NP
ON IN 36 V 5.2
1.4 s 5.4 V
1
TOFF VOUT
NS
3. Choose auxiliary to secondary ratio.
Soft Start & Hiccup Mode
Soft Start capacitor C7 determines the Soft Start time
during turn-on, and the dead time when the supply is
operating in hiccup mode. During Soft Start there will be a
NA VCC 0.7 V ICC RSNUB 2
VOUT 0.4 V
NS
11.7
10
mA 10 2 2.2
1
5.4 V
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CS5124DEMO/D
4. Calculate the minimum primary inductance so that the
on time at minimum load and maximum VIN is longer
than CS5124 blanking plus propagation delay time.
(see document number CS5124/D available through
the Literature Distribution Center or via our website at
http://www.onsemi.com).Minimum load is chosen to
be 60 mA.
where
T (TBLANK TPROP) Freq
(130 ns 180 ns) 400 kHz 0.124
and
PMIN V2 D 2
MIN Freq 2
752 0.1242
208 H
0.52 W 400 kHz 2
L P
(VOUT IOUT) PCS5124
Efficiency
(5.3 V 60 mA) 100 mW
52 W
0.8
5. Choose core type and design the transformer using
standard techniques. The winding sheet for the demo
board transformer is shown in Figure 4.
2/1/1999 5124 Flyback Transformer
ITEM
DESCRIPTION
CORE
Coiltronics ER 14.5, AL-2
BOBBIN
AL = 2.16E-07
MLT = 1.06
TAPE
CLIP
TRANSFORMER WINDING DATA
2
30
32
1
0.431
1.9E-04
1, 2
14
32
1
0.201
4.2E-05
1
6
31
3
0.023
7.8E-06
1
TURNS
WIRE
SIZE
# of
Wires
RNOM
LNOM
NOTES
4
10, 11, 12
7, 8, 9
LEAD
TERM
1
3
LEAD
TERM
Notes:
1. Start all windings together. (The number of turns are the total for each winding.)
2. Finish with tape.
3. A minimum of 500 V isolation is required.
Figure 4. Winding Sheet for the Demo Board Transformer
Output Filter
Figure 5 shows the output filter ripple currents at low line
and full load. The lower left section shows current supplied
to the output by the output filter while the main switch (Q2)
is on. The lower right section shows current supplied to the
output by the transformer secondary when Q2 is off (during
flyback). The upper right shows current supplied by the
transformer secondary to recharge the output filter. The
total charge in the upper right section must be equal the
(dis)charge in the lower left during steady state. The RMS
current in the output filter capacitor (C5) is ≅ 1.0 A.
Due to the high di/dt in the output filter of flyback
converters, spikes on the output are nearly impossible to
eliminate with one filter stage. In this design the output filter
sees approximately a 2.0 A step current in 50 ns. With such a
high di/dt just 3.0 nH (a typical via is 0.7 nH) of inductance
in a single stage output filter will produce a 120 mV spike.
See Figure 11. If this spike is unacceptable a second filter
stage, as shown in Figure 12, using a ferrite bead (Steward
HI0805N410R) and a ceramic capacitor can reduce the
spike to the magnitude shown in Figure x. (The feedback
connection should also be moved to connect to the 1.0 µF
filter capacitor.)
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CS5124DEMO/D
5.4 V/7.8 µH × 1.4 µs = 0.98 A
0.29 A
1.27 A
0.78 A Average to
recharge Filter Capacitor
1.0 A Out
ISECpk
1.1 µC from
Filter Capacitor
1.4 µC from Secondary
1.1 µs
SW ON
1.4 µs
SW OFF
Figure 5. Output Filter Currents
primary current can be calculated by dividing the secondary
peak current (in Figure 5) by the transformer ratio.
Ferrite Bead (0805 pkg)
1
2
Second
Filter
Stage
1 + Existing
47 µF
2
1
1.0 µF
ceramic
N
IPRIpk ISECpk S 2.27 A 6 0.45 A
30
NP
Load
The First Current Sense Threshold decreases with higher
duty cycles and should be calculated at maximum duty cycle.
2
CS5124 1st 2.9 V 170 mVs TON
60 mV
Threshold
10
2.9 V 170 mVs 1.1 s
60 mV
10
211 mV
Figure 6. Second Output Filter Stage
Current Sense Resistor Selection
The current sense resistor (R8) value is chosen to keep the
peak voltage of the current sense waveform below the
CS5124 1st Threshold during normal operation. The peak
The current sense resistor with a 20% margin is:
RSENSE 1st Threshold 211 mV 391 m
IPRIpk 1.2
0.45 V 1.2
TYPICAL PERFORMANCE CHARACTERISTICS
The figures below show typical performance of the CS5124 Demo Board. Unless noted all waveforms were taken with the
20 MHz filter option selected on the oscilloscope.
0.830
84
82
0.825
Percent (%)
Percent (%)
80
78
76
74
0.820
0.815
72
70
0.810
0.2
0.6
0.8
1.0
1.2
36
40
48
60
75
Amps (A)
Volts (V)
Figure 7. Typical Output Efficiency at 48 VIN
Figure 8. Typical Output Efficiency at 1.0 A Out
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CS5124DEMO/D
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 9. Start-up Waveforms
at 48 VIN, 1.0 A Load
Figure 10. Start-up Waveforms
at 48 VIN with 0.17A Load
Figure 11. Primary Voltage and Output Ripple
at 36 VIN, 1.0 A Out
Figure 12. Primary Voltage and Output Ripple with
Additional Filter Stage; Ferrite Bead and 1.0 F
Ceramic Capacitor-Full Bandwidth Measurement
Figure 13. Transient Response 0.17 A to 1.0 A Step
Figure 14. Transient Response 0.6 A to 1.0 A Step
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CS5124DEMO/D
TYPICAL PERFORMANCE CHARACTERISTICS
140
120
100
80
PHASE
60
40
20
GAIN
0
-20
-40
-60
102
103
104
105
Figure 15. Control Loop at 48 VIN, 0.5 A Out
Figure 16. Current Sense 36 VIN, 1.0 A Out
Figure 17. Current Sense 75 VIN,
0.15 A Out
Figure 18. Current Sense 75 VIN,
0.15 A Out Expanded
Figure 19. Current Sense 36 VIN,
Output Shorted
Figure 20. Second Threshold Operation 75 VIN,
Output Shorted (Current Sense Pulses Are
Attenuated Due to Sampling Frequency)
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CS5124DEMO/D
TYPICAL PERFORMANCE CHARACTERISTICS
3
Output Current
Current (A)
2
1
Input Current
0
5
4
3
2
1
0
Output Voltage (V)
Figure 21. Second Threshold Operation-The Last
Pulse Before Soft Start, 75 VIN, Output Shorted
Figure 22. V-I Curves During High Output
Currents and 36 VIN
3
0.15 A
Output
1.0 A
Output
Shorted
Output
(~2.5 A)
Ambient
24°C
25°C
26°C
PCB (below U1 & U2)
27°C
31°C
37°C
U1
42°C
46°C
52°C
U2
28°C
36°C
46°C
Q2
31°C
40°C
46°C
T1
30°C
45°C
67°C
D1
28°C
43°C
72°C
Location
Current (A)
Output Current
2
1
Input Current
0
5
4
3
2
1
0
Output Voltage (V)
Figure 23. V-I Curves During High Output Currents
and 75 VIN (Low Currents Near 0 VOUT
Occur During Hiccup Mode)
Figure 24. Component Temperature at 48 VIN
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CS5124DEMO/D
BILL OF MATERIALS
Item
Qty
Reference
Part
Mfg. & P/N
Distributor
1
1
C1
cer, 0.1 µF, 100 V, 1206
TDK C3216X7R2A104K
TDK
603-886-6600
2
1
C2
cer, 1.5 µF, 100 V
TDK C5750XR72A155K
TDK
3
1
C3
cer, 0.022 µF, 50 V, 0805
TDK C2012X7R1H223K
TDK
4
1
C4
0.47 µF, 25 V, 1206
TDK C3216X7R1E474K
TDK
5
1
C5
47 µF, 6.3 V
Panasonic EEFCDOJ470R
Digi-Key
800-344-4539
6
2
C6, C7
cer, 0.01 µF, 50 V, 0805
TDK C2012X7R1H103K
TDK
7
2
C8, C9
Note 1
cer, 1000 pF, 50 V, 0805
TDK C2012X7R1H102K
TDK
8
1
D1
Schottky
ON Semiconductor MBRD360
Newark
9
1
D2
Diode
ON Semiconductor BAS16LT1
Newark
10
1
L1
Inductor, 10 µH
J.W. Miller PM43-100M
Newark
11
1
Q1
MOSFET, 100 V
Zetex ZVN3310A
Digi-Key
12
1
Q2
MOSFET, 200 V, 0.8 Ω
International Rectifier IRFR220
Newark
13
1
R1
res, 510 k, 0805
Panasonic ERJ-6GEYJ514V
Digi-Key
14
1
R2
res, 200 k, 1%, 0805
Panasonic ERJ-6ENF2003V
Digi-Key
15
1
R3
res, 47 Ω, 0805
Panasonic ERJ-GEYJ470V
Digi-Key
16
1
R4
res, 10 Ω, 0805
Panasonic ERJ-GEYJ100V
Digi-Key
17
1
R5
res, 17.4 k, 0805
Panasonic ERJ-6ENF1742V
Digi-Key
18
1
R6
res, 1.0 k, 0805
Panasonic ERJ-GEYJ103V
Digi-Key
19
1
R7
res, 30.1 k, 0805
Panasonic ERJ-6ENF3012V
Digi-Key
20
1
R8
res, 0.39 Ω, 1%, 0805
Panasonic ERJ-6RQFR39V
Digi-Key
21
1
R9
res, 10 k, 1%, 0805
Panasonic ERJ-6ENF1002V
Digi-Key
22
1
T1
Transformer
Coiltronics CTX15-14514
Cooper Electronic
Technologies
561-752-5000
www.cooperet.com
23
1
U1
Current Mode Controller
ON Semiconductor CS5124-DR8
ON Semiconductor
401-885-3600
24
1
U2
Note 2
Optoisolated Feedback Amp
Texas Instruments TPS5908
Wyle
781-271-9953
Converter
Miscellaneous
1
4
TP1, 2, 4, 5
Turret Terminal
Cambion
2
10
TP3, 6-14
Single Pin Header
3
4
F1-4
Standoff
Winpoint
160-1558-02-01-00
Newark
201-01-S-3-02-T
-
Bumpons (Digi-Key) SJ5003-0-ND
1. For the Rev-0 printed circuit, C9 is a leaded component on the solder side.
2. TPS5908 is now an obsolete part and may be replaced by a TLV431 and an MOC8106.
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10
Digi-Key
CS5124DEMO/D
PCB LAYOUT
( )
Figure 25. Top (Component) Layer
Figure 26. Bottom (Solder) Layer
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CS5124DEMO/D
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
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SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: [email protected]
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2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850
Email: [email protected]
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For additional information, please contact your local
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CS5124DEMO/D
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