eval6470h schematic

5
4
3
2
1
TP1
VS
EXT_VDD
J2
1
3
5
7
9
BUSY
1
2
MISO
SDI
STCK
1
GNDMORSV-508-2P
2
4
6
8
10
D
FLAG
1
3
5
7
9
BUSY
EXT_VDD
CK
nCS
MISO
SDO
STCK
2
4
6
8
10
CON-FLAT-5X2
VDD
JP1
VREG
JP2
FLAG
EXT_VDD
CK
nCS
OPEN
CLOSED
JP3
MISO
1
VS
1
J1
VS
J3
SDO
CON-FLAT-5X2
D
CLOSED
TP2
STCK
TP3
STBY/RES
Application reference
OPTION
VS
VS
VS
R1
31k6
VDD VREG
1
10
CP
VBOOT
OSCOUT
C12
100pF/6V3
23
19
20
18
STCK
STBY_RES
FLAG
BUSY_SYNC
CS
CK
SDI
SDO
1A
2A
MORSV-508-2P
OUT1B
OUT2B
14
2
1
1B
2B
15
B
J6
TP6
GND
1
21
C13
3.3nF/6V3
D2
BZX84J-C3V6
1
2
28
L6470
EPAD
nCS
CK
SDI
SDO
1
MORSV-508-2P
ADCIN
SW
29
FLAG
BUSY
C11
100pF/6V3
OUT1A
DGND
5
4
25
3
24
22
STCK
C10
100pF/6V3
J5
OSCIN
OUT2A
ADCIN
SW
B
11
17
6
VDD
VREG
8
R6
39k
C
2
26
12
16
1
2
1
U1
OSCOUT
7
R4
39k
C5
47uF/6V3
C6
10nF/50V
VDD
R5
39k
+
C4
100nF/6V3
3
J4
N.M.
OSCIN
C3
10uF/6V3
BAV99
100uF/63V
R3
8k2
C2
100nF/6V3
VREG
VSA
VSA
VSB
VSB
+
C8
100nF/50V
2
TP5
VREG
1
+
220nF/16V
D1
C9A
100uF/63V
VDD
AGND
PGND
PGND
C7
100nF/50V
R2
200K
2
C
C15
100nF/50V
+
C9
9
13
27
3
C16
100nF/50V
TP4
VDD
1
C1
VS
TP7
FLAG
TP8
BUSY/SYNC
R9
2
470
1
RED
DL2
R7
2
FLAG
470
1
SW
BUSY
R8
100
J7
VDD
DL1
1
VDD
1
A
1
2
A
SW
C14
10nF/6V3
N.M.
Title
L6470H dSPIN Demonstration board.
Size
A4
YELLOW
Date:
5
4
3
2
Document Number
EVAL6470H
Tuesday, February 07, 2012
Rev
1.0
Sheet
1
1
of
1