AN-194: Designing Type1_2 IEEE802 3at af Powered Device Front-end and PWM controller

Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
TM
Using PD70101/PD70201 PD Front-End With Integrated
PWM Controller ICs
C OMPANY C ONFIDENTIAL
POE Overview _____________
The following document provides guidelines for
designing a PoE system Powered Device (PD)
compliant with IEEE 802.3af (IEEE802.3at Type 1) or
802.3at (Type 2) standards by using Microsemi’s
PD70101 or PD70201 PD Front End and PWM
Controller ICs. The PD70101 and PD70201 ICs are
integrated POE Powered Device (PD) Front end and
PWM controller for IEEE 802.3af and IEEE 802.3at
applications, respectively. The Front End section of
the PD70101 IC provides all necessary detection,
classification, and operating current levels compliant
with the IEEE 802.3af PoE standard. The Front end
section of the PD70201 IC provides the necessary
detection, classification, 2-event mark for “AT” flag,
and operating current levels compliant with the IEEE
802.3at Type 2 standard. The PWM controller section
of both PD70101 and PD70201 ICs integrate all
functions necessary to provide a complete DC/DC
solution for both isolated and non-isolated application
requirements.
In its simplest form, PoE consists of a power source,
referred to as Power Source Equipment (PSE), an
Ethernet cable (typically contained in an
infrastructure) with maximum length of 100 meters,
and a Powered Device (PD) which accepts both data
and power from the Power Interface (PI) of the
Ethernet cable. The PI is typically an eight pin RJ45
type connector. Per IEEE 802.3at specification,
power may be transmitted on one set of 2-pair
combinations, designated “Alternate A” or Alternate
B”. A diagram of this arrangement is shown in Figure
1.
This document includes a brief overview of PoE
functionality with respect to the applicable standards;
however it is not to be considered a substitute for the
IEEE standards. The applicable standard should
always be consulted when making decisions affecting
the design of the circuit.
Applicable Documents ______
IEEE 802.3af-2003 standard, DTE Power via MDI
IEEE802.3at-2009 standard, DTE Power via MDI
Microsemi Application Note AN193, Designing a
type1/2 IEEE 802.3af/at Powered Device Using
PD70100/PD70200 Front End ICs, catalogue
number 06-0129-080
PD70101/PD70201 datasheet, catalogue number
06-0132-058
IEEE 802.3af or IEEE 802.3at type 1 PSEs are
designed to operate with Ethernet cabling which may
include CAT3 (per TIA/EIA 568). As such they may
contain 26AWG wire. A cable of this type may impose
a 20Ω maximum power loop resistance to a PSE
operating into the maximum specified 100 meter
cable length. IEEE 802.3at type 2 PSEs are designed
to operate at higher output power levels with CAT 5 or
higher (per TIA/EIA 568) Ethernet cabling. These
cables contain 24AWG wire (or better) and may
impose a maximum 12.5Ω power loop resistance to a
PSE operating into the maximum specified 100 meter
cable length. The voltage drop and internal
temperature rise created in a 100 meter Ethernet
cable affect the voltage and current available to the
PD. A brief comparison between the AF and AT
standards for the PSE and the PD are presented in
Tables 1 and 2, respectively.
W W W. Microsemi .CO M
Introduction _______________
In addition to IEEE 802.3af/at specifications, a
compatible PSE may transmit power over all 4 pairs
for additional power available to the PD application.
For further information regarding POE please consult
Microsemi Application Note AN193, Designing a
type1/2 IEEE 802.3af/at Powered Device Using
PD70100/PD70200 Front End ICs, catalogue number
06-0129-080.
AN-194
Copyright  2010
Rev. 0.2, May, 2011
Microsemi
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
Page 1
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
TM
Using PD70101/PD70201 PD Front-End With Integrated
PWM Controller ICs
C OMPANY C ONFIDENTIAL
AF SPEC. = 350mA DC CURRENT TOTAL PER PAIR
(175mA X 2). UP TO 400mA PEAK.
AT SPEC. = 600mA DC CURRENT TOTAL PER PAIR
(300mA X 2). UP TO 686mA PEAK
1
1
2
2
4
4
5
5
7
7
8
8
3
3
6
6
PD APPLICATION
RJ45 CONNECTOR
DATA
DATA
RJ45 CONNECTOR
DATA
DATA
W W W. Microsemi .CO M
HUB OR SWITCH
DATA
DATA
DATA
DATA
POWER INTERFACE (PI)
PSE
PD DEVICE
100 METERS (MAX)
Alternative A
AF SPEC. = 350mA DC CURRENT TOTAL PER PAIR
(175mA X 2). UP TO 400mA PEAK.
AT SPEC. = 600mA DC CURRENT TOTAL PER PAIR
(600mA X 2). UP TO 686mA PEAK
HUB OR SWITCH
1
1
2
2
4
4
5
5
7
7
8
8
3
3
6
6
PD APPLICATION
DATA
DATA
RJ45 CONNECTOR
DATA
DATA
RJ45 CONNECTOR
DATA
DATA
DATA
DATA
POWER INTERFACE (PI)
PSE
PD DEVICE
100 METERS (MAX)
AN-194
Alternative B
Figure 1: Basic PoE Configuration for IEEE 802.3at Standard
Copyright  2010
Rev. 0.2, May, 2011
Microsemi
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
Page 2
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
TM
Using PD70101/PD70201 PD Front-End With Integrated
PWM Controller ICs
C OMPANY C ONFIDENTIAL
Guaranteed Power at PSE Output
15.4W
30W
PSE Output Voltage
44V to 57V
50V to 57V
Guaranteed Current at PSE Output
350mA DC with up to
400mA peaks
600mA DC with up to
686mA peaks
Maximum Cable Resistance
20Ω
12.5Ω
Physical Layer Classification
Optional
Mandatory
Supported Physical Layer Classification
Classes
Class 0 to Class 3
Class 4 - mandatory
Data Link Classification
2-Events Classification
Optional
Not required
4 pairs power feeding
Not allowed
Mandatory
Mandatory
Allowed with 2 collocated
PSEs
W W W. Microsemi .CO M
Comparison of IEEE 802.3af and IEEE 802.3at Standards for PSE
IEEE 802.3af or IEEE
PSE Requirements
IEEE 802.3at type 2
802.3at type 1
10/100 BASE-T
10/100/1000 BASE-T
(Midspans)
Communication Supported
Including Midspans (Both
10/100/1000 BASE-T
type1 and type2)
(switches)
Table 1: IEEE 802.3af and 802.3at Standards for PSE
Comparison of IEEE 802.3af and IEEE 802.3at Standards for PD
IEEE 802.3af or IEEE
PD Requirements
IEEE 802.3at type 2
802.3at type 1
Guaranteed Power at PD Input
12.95W
25.50W
PD Input Voltage
37V to 57V
42.5V to 57V
Guaranteed Current at PD Input
350mA DC with up to
400mA peaks
600mA DC with up to
686mA peaks
Maximum Cable Resistance
20Ω
12.5Ω
Physical Layer Classification
Mandatory
(no class = Class 0)
Mandatory
Supported Physical Layer Classification
Classes
Class0 to Class3
Class 4 - mandatory
AN-194
Data Link Classification
2-Events Classification
4 pairs power receiving
Optional
Mandatory
Not required
Mandatory
Allowed
Allowed
10/100 BASE-T
10/100/1000 BASE-T
(Midspans)
Communication Supported
Including Midspans (both
10/100/1000 BASE-T
type1 and type2)
(switches)
Table 2: IEEE 802.3af and 802.3at Standards for PD
Copyright  2010
Rev. 0.2, May, 2011
Microsemi
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
Page 3
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
T
Using PD70101/PD70201 PD Front-End With
Integrated PWM Controller ICs
C OMPANY C ONFIDENTIAL
PD70101/PD70201 Features
Using PD70101/PD70201: Front
End Section
Copyright  2010
Rev. 0.2, May, 2011
In an alternate two pair/four pair single IC system, the
two input diode bridge’s outputs are wired in parallel,
and the common output supplies input power (VPP
(+), VPN_IN (-)) to the PD70101/PD70201 IC, which
by means of the integrated PWM controller, drives an
isolated or non-isolated DC/DC converter (depends
on application requirements). The paralleled output
terminals from the two diode bridges are connected to
the PD70101/PD70201 IC at VPP (positive
connection, pin 32), and VPN_IN (negative
connection, pin 5). This connection requires a single
capacitor of 50nF to 120nF (68nF typically used)
connected across the positive and negative output
terminals of the paralleled diode bridges. This 68nF
capacitor meets the IEEE 802.3af/at standard
requirement for hardware detection.
The output connections from the PD70101/PD70201
Front End section are made at VPP (positive
connection, pin 32), and VPN_OUT (negative
connection, pin 8). VPN_OUT is the primary ground
connection from the integrated isolation switch of the
PD70101/PD70201 IC to the DC/DC converter. The
IC’s exposed center pad should be connected
electrically to VPN_IN (pin 5)
In addition to the PD70101/PD70201 Front End
section’s basic input/output connections, the following
components are required for a typical application:
Detection Resistor: Connect a 24.9kΩ ±1%
resistor between VPP and RDET (Pin 1). This
resistor is used to satisfy the Detection signature.
A low wattage type may be used as there is less
than a 7mW stress on this resistor while
Detection phase is active, and the resistor is
disconnected after power is on.
Reference Resistor: Connect a 243kΩ ±1%
resistor between RREF (pin 3) and VPN_IN (pin
5). This resistor should be located as close as
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 4
AN-194
The PD70101’s Front End section provides the
necessary Detection, Classification, and Isolation
Switch control functions for a PoE-powered device
conforming to IEEE 802.3af or 802.3at type 1
standards. The PD70201’s Front End section
provides the same functions as the PD70101, with an
additional higher Isolation Switch current capability,
additional 2-Events- Classification detection and AT
Flag generation conforming to IEEE 802.3at type 2
standards. Both chips are designed for minimal
external components.
W W W. Microsemi .CO M
IEEE 802.3af (IEEE802.3at Type 1)
Compliant (PD70101)
IEEE802.3at Type 2 Compliant (PD70201)
Support up to 47.7W 4 pair systems with a
single PD70201
Provides PD Detection Signature
Programmable PD Classification Signature
Supports 2 Event Classification Flag
(PD70201)
Active Low, Open Drain Power Good Signal
Integrated Isolation Switch
24.9KΩ signature resistor disconnection
when power is on
Inrush Current Limit (Soft Start)
Integrated 10.5V Start-up Supply for
integrated DC/DC controller
Internal Discharge Circuitry for up to 220µF
DC/DC Bulk Capacitor
Wide Temperature Operating Range -40°C to
+85°C
On-Chip Thermal Protection
100 kHz to 500 kHz adjustable DC-DC
switching frequency
DC/DC frequency can be synchronized to
external clock
Supports low power mode operation for
higher efficiency
Soft-start circuit to control the output voltage
rise time
Support efficient synchronous rectification
PoE Port Input UVLO with programmable
threshold and hysteresis
Internal differential amplifier simplifying nonisolated step down converter
Over load and short circuit protection
PD70101/PD70201 IC may be configured as an
alternate two or four pair system (see Figure 2) in
which one PD70101/PD70201 IC is driven from both
diode bridges (output terminals connected in parallel),
or may be configured as a four pair system (see
Figure 3) in which a single PD70101/PD70201 IC and
a single PD70100/PD70200 IC are driven individually
by one of the two diode bridges. In four pair, two IC
systems the isolation switch output terminals of the
PD70101/PD70201 IC and the PD70100/PD70200 IC
are connected together in parallel, and the two chips
VPP inputs are isolated from one another by using
two suitable diodes, each in series with VPP. For
each IC, required capacitors of 50nF to 120nF (68nF
typically used) are connected across the positive and
negative output terminals of the each diode bridge.
This configuration, as opposed to the two pair system,
allows available output power to affectively double.
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
T
Using PD70101/PD70201 PD Front-End With
Integrated PWM Controller ICs
C OMPANY C ONFIDENTIAL
requires a resistor pull-up to be functional. Pull-up
voltage on this pin cannot exceed 74V and is
recommended to be pulled up to a voltage no
higher than VPP. This pin is active low and rated
at 0.4V and 0.75mA.
Start-up Supply Output Capacitor: The
PD70101/PD70201 contains an internal low
power (2mA continuous) regulated DC output
available for use as a start-up supply for the
integrated DC/DC converter controller. This
supply output is available on the VCC pin (pin
31), and is intended to be used in conjunction
with an external bootstrapped supply, also
connected to the VCC pin. The
PD70101/PD70201’s VCC pin provides power
input to the internal supply rails for the integrated
DC/ DC controller. The bootstrapped supply input
to VCC is typically provided by means of an
auxiliary output from the DC/DC converter, but
may be provided by means of any voltage source
with a maximum output voltage of 15V (15V
provides a safe operating range for the gate drive
outputs). The internal start-up supply regulator
requires a ceramic capacitor of minimum 4.7µF,
to be connected directly between VCC (pin 31)
and VPN_OUT (pin 8).
W W W. Microsemi .CO M
practical to the PD70101/PD70201 IC. A low
wattage type may be used (there is less than
1mW stress on this resistor).
Classification Current Resistor: The value of
this resistor determines the PD current draw
during Classification Phase. Values
corresponding to IEEE compliant classification
levels are shown in Table 4. Connect this resistor
between RCLASS (pin 4) and VPN_IN (pin 5).
Power Good Pull-up: Power Good signal is
available at PGOOD (pin 2). A PGOOD flag is
generated low voltage to optionally inform the
application that the power rails for the integrated
DC/DC controller are ready, and the DC/DC has
begun soft-start. This signal can be used to
disable any external input to the
PD70101/PD70201’s ENABLE pin (pin 10) when
operating in a 4-pairs dual IC configuration.
PGOOD is an open drain pin which requires a
resistor pull-up to be functional. Pull-up voltage
on this pin cannot exceed 74V and is
recommended to be pulled up to a voltage no
higher than VPP. This pin active low and rated at
0.4V and 0.75mA.
AT Flag Pull-up (PD70201 only): AT Flag signal
is available at AT_FLAG (pin 7). An AT_FLAG is
generated low voltage to inform the application
that the PSE providing PD power is IEEE 802.3at
compliant. This is an open drain pin which
Programmed Classification Signature
RCLASS Resistance Values
Class
RCLASS Resistor
Value
0
1
2
3
Open
113Ω ±1%
64.9Ω ±1%
42.2Ω ±1%
4
30.9Ω ±1%
PD70101/PD70201 Current
Draw During Classification
Min.
Average
Max.
0
3mA
9.5mA
10.5mA 11.5mA
17.5mA 18.5mA 19.5mA
26.5mA
28mA
29.5mA
38mA
40mA
42mA
A single PD70101/PD70201 IC may be operated
with 4 pairs for extended power capability. Up to
47.7W (PD70201 operating at IEEE 802.3at input
voltage levels) is supported. The component
requirements for a single PD70101/PD70201
operating with 4 pairs are the same as single IC
applications operating with 2 pairs.
Copyright  2010
Rev. 0.2, May, 2011
A typical 2 pairs/4pairs single IC configuration is
outlined in Figure 3.
Some applications may require an indication if power
is provided on 4 pairs, or 2 pairs only. An additional
circuit may be optionally added to sense if input POE
power is provided on 2 pairs or 4 pairs. This circuit
is shown in the application example of Figure 2.
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 5
AN-194
Table 4: RCLASS Resistance Values
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
T
Using PD70101/PD70201 PD Front-End With
Integrated PWM Controller ICs
C OMPANY C ONFIDENTIAL
drive the switch circuit R4, R6, and Q1. The signal
present at the Collector of Q1 will be low if only 2
pairs are present and high if all 4 pairs are providing
power. Be aware that the output of this 4 pairs
detection circuit is at POE voltage levels, and should
not directly interface to low-level logic. If required,
the Collector of Q1 can interface directly to an
optoisolator as shown in the example.
12V
PD1 -
VPPout
R1
47K
PD1+
R2
1
POE INPUT
4
2
2
-
+
1
1
~
3
D1
3
3
POE INPUT
3
PS2711-1-M-A
1
D2 MMBD914-G
3
D3
Q1
1
2
FMMT493
R4
100K
MMBD914-G
~
-
+
1
3
D4
1
D5 MMBD914-G
1
~
4
4 PAIRS PRESENT
4
MMBD914-G
POE INPUT
D16
R3
24.9K
1
U1
100K
~
D15
OPTIONAL 4 PAIRS DETECTION CIRCUIT
W W W. Microsemi .CO M
Referencing the optional circuit of Figure 2, the
PD70101/PD70201 detection resistor, RDET, is not
used, and is replaced by two detection resistors, R3
and R5, which provide the required resistor detection
signature for each individual 2 pairs input. R3 and
R5 also provide pull up current so that the presence
of the individual 2 pairs input may be sensed and
combined into a logical OR function via diodes D1
thru D6. The output of this circuit is then used to
R6
100K
3
3
MMBD914-G
3
POE INPUT
D6
1
R5
24.9K
1
MMBD914-G
PD2+
PD2-
Figure 2. Optional 4 Pairs PSE Detection
AN-194
Copyright  2010
Rev. 0.2, May, 2011
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 6
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
T
Using PD70101/PD70201 PD Front-End With
Integrated PWM Controller ICs
VPPout
~
D1
2
C OMPANY C ONFIDENTIAL
+
1
1
2
L1
+
~
12V
4.7uH
C2
4.7uF
100V
X7R
C1
47uF
100V
C21
4.7uF
100V
X7R
C3
4.7uF
100V
X7R
C4
4.7uF
100V
X7R
C5
100n
100V
R38
2.7K
1W
R37
2.7K
1W
R1
2.7K
1W
C6
68n
100V
L2
T2
10
9
5
1
C11
68nF
100V
1
1
CSN
CSP
3
PGND
CSN
CSP
PG
VH
VPP
VL
RCLASS
5
6
1uF
21 VL
1
2
3
4
L2 AND C10 ARE OPTIONAL
1
R4
0.047
1/2W
R3
825
CSN
R5
1K
R6
1.2K
U2
4
C17
1
19
3
2
18
1
RCLP
1
4
2
PS2711-1-M-A
17
R8
9.53K
330n
R10
2.49K
D5
TL431ACDBVR
1
16
SS
15
14
13
NC
9
RFREQ
VSN
SYNC
VSP
VPNO
HYST
ATFLAG
10
12V @ 4.0 AMPS MAX
FDMS86200
VL
25
20
COMP
12
7
8
4
3
2
1
CI5104P1V00
1 2 3
CSP
23
22
DAO
NC
Q2
C16
FB
U1
PD70201
VPNI
4
3
2
1
GDRIVE
1n 2000V
24
GND
VINS
R9
30.9
PGOOD
RREF
4
C8
180uF
C10
10uF
4
SG
ENABLE
R7
243K
C7
180uF
C9
1u
25V
X7R
8 7 6 5
25
28
29
26
30
27
31
32
C15
VL
RDET
11
~
3
2
VCC
EP
1
VAUX
EP
D1
S1
D2
S2
D3
S3
D4 GATE
+
FDS86322
SG
2
1
Q1
8
7
6
5
2
~
-
+
ES1D
2
C14
R2
24.9K
D4
6
7
10U
25V
X7R
VP6014 LF
4
3
1
D3
SS16
C13
100n
C12
100n
2
+
3
DATA OUT
J1
2
1uH
D2
5
23
24
22
20
21
19
17
18
16
14
15
13
3
T1
W W W. Microsemi .CO M
DATA &
POWER IN
2
1
3
5
4
6
8
7
9
11
10
12
-
4
GDRIVE
1
C18
R19
C19
1
T3
D6
6
2
1
1
R13
49.9K
24
1u
16V
X7R
3
1u
16V
X7R
4
FA2659-AL
D7
LL4148
R14
1K
LL4148
Q3
3
R15
MMBT2907AWT1G
1
2
R12
316k
C20
1
SG
100n
16V
2
HYST
VPP
1
392K
R16
9.53K
PRIMARY
SECONDARY
1
12V
R17
47K
VPPout
R18
1
U3
/ATFLAG
4
100K
2
3
PS2711-1-M-A
Figure 3. Typical 2 or 4 Pair Configuration with a Single PD70201 IC.
In a 4 pairs dual IC system, a single
PD70101/PD70201 IC and a single
PD70100/PD70200 are placed in a PD design, each
driven by a separate diode bridge. The Isolation
Switch output at VPN_OUT is connected in parallel
for each IC, while the VPP inputs to PD70101 and
PD70100 or PD70201 and PD70200 ICs are
connected by means of series blocking diodes. The
combined output terminals drive the input filter/bulk
capacitor for the DC/DC converter. This affectively
doubles the total input power capability to the DC/DC
converter.
Under certain conditions, power available at the PI
may be on two pairs only. Dual IC configurations
where power is applied to only one of the two chips
require certain considerations for the AT_FLAG and
PGOOD signals.
Providing individual PGOOD and AT_FLAG controls
between two ICs is necessary for covering all possible
power input configurations.
The VAUX regulator output from the single
PD70100/PD70200 IC must be connected to the VCC
pin of the PD70101/PD70201 IC using a suitable
blocking diode. In addition, a blocking diode must be
added between the PD70101/PD70201 IC’s VAUX
pin (pin 31) and VCC pin (pin 30). Small, low current
30V diodes may be used for this requirement.
A typical 4 pairs, 2 IC configuration is outlined in
Figure 4.
Operation with an External (non POE) DC
Source
PD applications utilizing the PD70101/PD70201 IC
may be operated with an external power source (DC
wall adaptor). There are three methods of providing
power with an external source:
In a dual IC configuration, the PGOOD signal from the
PD70100/PD70200 is used to enable the
PD70101/PD70201’s integrated DC/DC controller
during conditions when the PD70101/PD70201’s
Front End section is not powered, and as such
requires special consideration. The
Copyright  2010
Rev. 0.2, May, 2011
1) External source connected directly to the
PD70101/PD70201 Input (VPP to VPN_IN).
Requires external source output voltage to be
40V minimum under all load conditions. The
adaptor must provide a diode in series with
VPP to block reverse current from a fully
charged bulk capacitor.
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 7
AN-194
The AT_FLAG should be connected in a wired-OR
configuration. Since the AT_FLAG output is open
drain configured, this signal may be easily wired-OR
between the PD70101/PD70201 and
PD70100/PD70200 ICs for a common AT_FLAG
output connection by simply connecting the two
AT_FLAG pins together with a common pull-up
resistor.
PD70101/PD70201’s ENABLE pin (pin 10) is active
high; it should be tied to ground when it is not used.
An example of a dual chip use of DC/DC enable
control is shown in Figure 4.
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
T
Using PD70101/PD70201 PD Front-End With
Integrated PWM Controller ICs
C OMPANY C ONFIDENTIAL
VPPout
D19
+
1
1
~
+
C29
4.7uF
100V
X7R
C28
4.7uF
100V
X7R
C36
4.7uF
100V
X7R
1
D17
MBR0530
2
2
L4
T5
10
9
5
3
1
ATFLG
VPN_IN
VPN_OUT
N/C
VPN_OUT
GDRIVE
1n 2000V
FDMS86200
1 2 3
24
C39
1uF
23
21
1
20
R20
825
VL
CSP
R36
0.047
1/2W
22
CSN
R19
1K
R21
1.2K
U5
4
VL
C30
1
19
3
2
18
1
RCLP
R31
9.53K
330n
1
4
2
PS2711-1-M-A
17
5
CSN
1
2
3
4
R32
2.49K
D13
TL431ACDBVR
1
16
SS
RFREQ
15
14
HYST
SYNC
13
12V
6
5
CSP
28
25
PGND
CSN
29
26
30
27
CSP
PG
VH
31
VPP
10
9
11
4
3
2
1
CI5104P1V00
GDRIVE
C32
10
VPP
09
R23
08
R27
49.9K
R24
316k
07
C24
1
C25
1
SG
100n
16V
T4
D9
6
2
1
24
1u
16V
X7R
3
1u
16V
X7R
4
PE68386
D8
LL4148
R22
1K
LL4148
2
PGOOD
VPN_IN
EP
6
VAUX
RCLS
4
3
2
1
1
5
RREF
12
C27
180uF
C22
10uF
Q4
3
R25
MMBT2907AWT1G
1
2
4
VPP
HYST
3
RDET
NC
1
2
R?
30.9
VSN
2
1
R?
243K
VSP
VPNO
D?
MBR0530
PD70200
EP
C?
68nF
100V
COMP
ATFLAG
12
~
~
U?
DAO
NC
7
8
R?
24.9K
U4
Q5
VL
FB
PD70201
VPNI
6
1
VCC
32
5
VINS
R34
30.9
8 7
VL
RCLASS
C26
180uF
C21
1u
25V
X7R
4
GND
ENABLE
2
D18
MBRS2H100T3G
4
+
SG
SG
RREF
11
R29
243K
D1
S1
D2
S2
D3
S3
D4 GATE
+
FDS86322
C23
PGOOD
3
Q6
8
7
6
5
2
J2
2
1uH
10u
25V
X7R
RDET
2
1
6
7
ES1D
D14
SS16
C40
100n
VAUX
EP
1
VPPout
3
C38
68n
100V
C33
EP
+
R35
820
D12
R28
24.9K
D11
C37
100n
100V
1
VP6014 LF
4
C41
4.7uF
100V
X7R
C35
100n
C34
68nF
100V
DATA OUT
12V
1uH
C31
47uF
100V
3
23
24
22
20
21
19
17
18
16
14
15
13
2
L3
MBRS2H100T3G
T6
Three examples of PD70101/PD70201 configured
with an external wall adaptor are diagrammed in
Figure 5.
3
-
DATA &
POWER IN
2
1
3
5
4
6
8
7
9
11
10
12
3) External source connected directly to the
application’s low voltage supply rails (output
side of an isolated or non-isolated power
supply). It is recommended the external
source contain a series reverse current
blocking diode and may optionally be isolated
from the application power supply’s output by
means of a switched connection.
2
~
D10
4
source in this configuration. If required, the
additional start-up circuit and enable circuit
will depend on the application requirements.
Note: When not operating with an external
adaptor, the PD70101/PD70201 IC’s external
enable pin should be tied to the GND pin (pin
23).
W W W. Microsemi .CO M
2) External source connected directly to the
PD70101/PD70201 output connection to the
application. The external source output
voltage will be dependent on the application
input requirements. Both the external source
and the PD70101/PD70201 IC’s VPP must
have series diodes to block reverse current.
If the application’s DC/DC converter contains
a bootstrapped output connection to VCC, a
suitable start-up circuit must be supplied for
the external source, as the
PD70101/PD70201’s internal start-up supply
will not function while powering the
application with an external source in this
configuration. In addition to the start-up
supply requirement, an external enable signal
is required, as the PD70101/PD70201’s
internal enable will not function while
powering the application with an external
1
R?
R?
100K
220K
392K
VPPout
R26
9.53K
R?
PRIMARY
110K
1
Q?
FMMT593
SECONDARY
1
12V
D?
BZM55C5V1
2
R?
10K
R33
47K
VPPout
R30
1
U6
/ATFLAG
4
100K
2
3
PS2711-1-M-A
Figure 4: Typical 4 pairs configuration with a PD70200 and PD70201; shows use of ENABLE pin
AN-194
Copyright  2010
Rev. 0.2, May, 2011
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 8
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
T
Using PD70101/PD70201 PD Front-End With
Integrated PWM Controller ICs
C OMPANY C ONFIDENTIAL
DATA + POWER
DATA
ISOLATED DC-DC CONVERTER EXTERAL COMPONENTS
POWER TRANSFORMER
BOOTSTRAP WINDING
2
4
-
+
1
240K
~
1
Rdet
3
Rref
4
Rclass
Vpp
VAUX
3
VCC
30.9
ENABLE
GND
VPNin
VPNout
32
APPLICATION
31
30
10
ISOLATED DC OUTPUT (-)
22
8
PRIMARY DC (-) INPUT
2
5
ISOLATED DC OUTPUT (+)
10uF
PD70201
24.9K
68nF
100V
~
W W W. Microsemi .CO M
PRIMARY DC (+) INPUT
~
4
-
+
1
3
~
DC INPUT FROM
WALL ADAPTOR
(-) INPUT
D1
(+) INPUT
CONFIGURATION #1: SOURCE CONNECTED TO PD70201 INPUT
DATA + POWER
DATA
ISOLATED DC-DC CONVERTER EXTERAL COMPONENTS
D2
PRIMARY DC (+) INPUT
POWER TRANSFORMER
BOOTSTRAP WINDING
2
4
-
+
1
240K
3
~
1
Rdet
3
Rref
4
Rclass
Vpp
32
VAUX
31
VCC
30
ENABLE
30.9
GND
5
VPNout
VPNin
ISOLATED DC OUTPUT (+)
10uF
PD70201
24.9K
68nF
100V
~
D3
APPLICATION
10
ISOLATED DC OUTPUT (-)
22
8
2
PRIMARY DC (-) INPUT
~
4
-
+
1
3
~
D4
100K
DC INPUT FROM
WALL ADAPTOR
R
5.1V
START-UP
CIRCUIT OR VCC
SUPPLY
SIZE RESISTOR "R" FOR 2.5V AT
MINIMUM VIN
(-) INPUT
2
3
1
D1
(+) INPUT
CONFIGURATION #2: SOURCE CONNECTED TO PD70201 DC-DC CONVERTER
DATA + POWER
DATA
ISOLATED DC-DC CONVERTER EXTERAL COMPONENTS
PRIMARY DC (+) INPUT
POWER TRANSFORMER
BOOTSTRAP WINDING
2
4
-
+
1
68nF
100V
240K
3
~
1
Rdet
3
Rref
4
Rclass
ISOLATED DC OUTPUT (+)
10uF
PD70201
24.9K
~
Vpp
32
APPLICATION
VAUX
31
VCC
30
GND
22
30.9
ISOLATED DC OUTPUT (-)
VPNin
VPNout
8
PRIMARY DC (-) INPUT
AN-194
2
5
~
4
-
+
1
3
~
DC INPUT FROM
WALL ADAPTOR
DIODE D1 BLOCKS APPLICATION
BULK CAPACITOR DISCHARGE
THROUGH ADAPTOR
(-) INPUT
2
3
1
D1
(+) INPUT
CONFIGURATION #3: SOURCE CONNECTED TO APPLICATION'S SUPPLY RAILS
Figure 5. External Power Input Configurations
Copyright  2010
Rev. 0.2, May, 2011
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 9
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
T
Using PD70101/PD70201 PD Front-End With
Integrated PWM Controller ICs
C OMPANY C ONFIDENTIAL
Bulk Capacitor Discharge
Soft Start Current Limit
Soft Start current limit is necessary to limit the inrush
current created by the initial charge up of input
capacitors upon system start-up. Large inrush
currents can create large voltage sags at the PI,
which in turn can cause system functions tied to event
thresholds (such as AT_FLAG) to reset to their initial
states. Soft Start current limit will significantly reduce
the voltage sag upon start-up.
The PD70101/PD70201 IC Soft Start function limits
current to a maximum of 320mA (240mA typical).
Start-up into a fully discharged bulk capacitor will
result in large power dissipation in the isolation switch
for a period of time dependent on the size of the bulk
capacitance. This occurs due to the initial voltage
drop across the isolation switch. The maximum initial
voltage drop across the isolation switch can be of
42V. In other words, the initial power dissipation of the
isolation switch can be no higher than 13.4W (42V x
320mA). The maximum power dissipated by the
isolation switch will decrease as the bulk capacitor
charges, eventually decreasing to a maximum normal
operating power dissipation of 74mW (PD70101) or
311mW (PD70201). The period of time required to
switch from Soft Start mode to normal operation mode
can be calculated using the following formula:
T=
(∆V − 0.7 ) × C
I
Whereas:
I = PD70101/PD70201 IC’s current during soft start
T=
(∆V − 1.5V ) × C
0.0228
Whereas:
C = Total Input Bulk Capacitance
DV = Initial VPP – VPN_OUT Voltage at Isolation
Switch Turn-off
Example: Assuming an initial capacitor voltage of
32V, it will take 294ms for a 220µF capacitor to
discharge to a 1.5V level.
The PD70101/PD70201 discharge circuitry can be
safely operated with a bulk capacitance of up to
220µF.
VAUX regulated output is enabled only when the
isolation switch is in normal operation mode. This
insures DC/DC controller does not start prematurely.
PGOOD Output
PD70101 and PD70201 IC provide an open drain
output indicating POE power good status. This output
is in a high impedance state until VPP – VPN_IN
voltage exceeds the isolation switch turn-on
threshold, and isolation switch moves from Soft Start
current limit mode to normal operation mode. Upon
assertion, the PGOOD output switches to ground.
When VPP – VPN_IN voltage falls below the isolation
switch turn-off threshold, the PGOOD output
reasserts back to high impedance state.
DV = Initial VPN_OUT – VPN_IN voltage at start of
soft start (DVmax = VPP)
The PD70101/PD70201 IC can safely operate with a
total bulk capacitance of 220µF.
Copyright  2010
Rev. 0.2, May, 2011
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 10
AN-194
C = Total input bulk capacitance
The PD70101/PD70201 IC provides discharge of the
application bulk capacitor when VPP – VPN_IN falling
voltage drops below the isolation switch turn-off
threshold (31V to 34V). This feature insures that the
application bulk capacitance does not discharge
through the detection resistor, which can cause the
detection signature to fail and prevent the PSE from
starting the PD. While enabled, the discharge
function provides a minimum controlled discharge
current of 23.8mA, which flows through the VPP pin,
internally through the isolation MOSFET’s body diode,
and out through the VPN_OUT pin. The discharge
circuitry monitors the voltage difference between VPP
– VPN_OUT, and remains active while the difference
voltage is 1.5V ≤ (VPP – VPN_OUT) ≤ 32V. The
maximum time to discharge can be calculated by:
W W W. Microsemi .CO M
The PD70101/PD70201 IC provides Soft Start current
limiting. A rising voltage of 36V to 42V between VPP
and VPN_IN will enable the isolation switch in Soft
Start Current Limit mode. During this time, the current
through the isolation switch is limited to 240mA
(typical). The PD70101/PD70201 IC continuously
monitors the voltage drop across the isolation switch
(VPN_OUT to VPN_IN) during Soft Start mode. When
difference between voltages VPN_OUT and VPN_IN
drops below 0.7V, the PD70101/PD70201 IC will
switch to normal operating mode, in which the
isolation switch is fully on, with over-current protection
circuitry active.
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
T
Using PD70101/PD70201 PD Front-End With
Integrated PWM Controller ICs
C OMPANY C ONFIDENTIAL
AT_FLAG Output (PD70201 only)
The AT_FLAG signal is synchronized with the
PGOOD signal. For example, PGOOD can be
asserted without asserting AT_FLAG, but AT_FLAG
cannot be asserted without asserting PGOOD.
The PD70101/PD70201 IC provides thermal
protection. Integrated thermal sensors monitor the
internal temperatures of the isolation switch and
classification current source. If the overtemperature
threshold of either sensor is exceeded, that sensor’s
respective circuit will disable.
To insure trouble free operation, it is important that
PD70101/PD70201 IC’s exposed pad is mounted to a
copper area on the PCB that provides an adequate
heatsink.
The following considerations should be made when
using the PD70101/PD70201 PWM controller:
The PD70101/PD70201’s PWM Controller section
provides all functions necessary to control both
isolated and non-isolated DC/DC topologies, including
isolated Flyback and Forward converter topologies, as
well as non-isolated Buck and Boost topologies.
9
Freq = 10x10 /RFREQ
Resistor Range = 100kΩ to 20kΩ
.
•
Copyright  2010
Rev. 0.2, May, 2011
Frequency Setting Resistor (RFREQ): The
value of this resistor determines the switching
frequency, as well as sets the pin current for both
SS and RCLP pins. The value of RFREQ is
based on the following equation:
Soft Start Charge Current: The DC/DC soft
start time is determined by the value of the
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 11
AN-194
Using PD70101/PD70201: PWM
Controller Section
Thermal Protection
W W W. Microsemi .CO M
The PD70201 IC provides an open drain output
indicating a 2 Events Classification was detected.
This output is in a high impedance state until the VPP
– VPN_IN voltage exceeds the isolation switch turnon threshold and the isolation switch moves from Soft
Start Current Limit mode to normal operation mode. It
will then assert to low, but only if a 2 Events
Classification Signature was recognized during
Classification phase described earlier. Upon
assertion, the AT_FLAG output switches to ground.
The AT_FLAG output re-asserts back to the high
impedance state when the VPP – VPN_IN voltage
falls below the isolation switch turn-off threshold.
The AT_FLAG signal is typically used for indicating
the PD application that PSE is capable of supplying
AT power levels. Often the PD application is
electrically isolated. The AT_FLAG is referenced to
the primary ground. As such, it requires an
optoisolator to provide an isolation barrier between
primary ground and application ground for electrically
isolated applications.
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
T
Using PD70101/PD70201 PD Front-End With
Integrated PWM Controller ICs
C OMPANY C ONFIDENTIAL
capacitor connected to the SS pin, and the SS
pin’s charging current. The charging current is
calculated:
ISS_CHG = 1.2V/RFREQ
The following is a design example for a 48W DC/DC
Flyback converter using the PD70201 IC. A
schematic and parts list of the 48W example can be
found in Figures 7.
•
TSS = (RFREQ x CSS x 1.1)/1.2
•
Low Power Mode Clamp Threshold: The Low
Power Mode Clamp Threshold is set by the
resistor connected between RCLP pin (pin 17)
and GND. The value is determined by the
following equation:
VCLAMP = 0.3 x (RCLP/RFREQ)
The clamp voltage determines the threshold
below which the DC/DC converter enters low
power skip mode (LPM). This threshold is
typically set as a percentage of the peak inductor
current at maximum output load and minimum
input voltage. VCLAMP voltage equates to a
percentage of peak current by the following:
Vmax := 57
Maximum Input Voltage
Vout := 12
Output Voltage
Pout := 48
Maximum Output Power
Eff := .90
Estimated Efficiency
Fsw := 200k
Switching Frequency
Vaux := 12
Auxillary Output Voltage
Tamb := 70
Ambient Operating Temperature
Estimated Secondary Diode Drop:
Sync Transistor: FDMS86322; RDSon = 0.008 at 25°C
During start up, it starts with LPM mode until
Vcomp voltage goes higher than 0.2V and/or
VCLAMP ≤ 1.11x(VCOMP-0.25V), (VCOMP≥0.25V).
Connecting the RCLP pin to ground disables LPM
mode during normal operation.
VPP UVLO: The PD70101/PD70201 ICs offer a
VPP monitoring UVLO function. The UVLO
function is dependent on the voltage present at
the VINS pin (pin 11), and will switch states
based on a 1.2V threshold. Hysteresis may be
programmed in by means of a resistor connected
between HYST pin (pin 12) and VINS pin.
Components are determined as follows:
Minimum Input Voltage
Synchronous Rectification is used in place of a
blocking diode; choose FDMS86322 N-FET.
IPK (MAX) = maximum peak inductor current set by
the current sense resistor (assumes VRCS = 0.12V
at maximum peak current).
•
Vmin := 32
Flyback operation in DCM is best for output
power less than 30W; therefore the design will be
a CCM design.
•
ILPM = [(0.9 x VCLAMP)/1.2] x IPK (MAX);
Design Requirements:
Iout :=
Pout
Iout = 4
Vout
Kt := 1.58
Multiplier for 100°C
rdson := 0.008⋅ Kt
ddrop := Iout ⋅ rdson
•
ddrop = 0.051
Transformer Turns Ratio:
Transformer Turns Ratio is driven by Vmin, Vout,
the secondary diode drop, and the controller’s
maximum duty cycle. Per the datasheet,
maximum duty cycle for the PD70201 = 46%.
Dmax := 0.46
VHYST = HYST Pin Output High (5V typ.)
Tratio :=
VRISING = Upper Voltage Threshold
Vout + ddrop
Dmax ⋅ Vmin
−
Vout + ddrop
Vmin
Set R3 such that (VHYST – 1.2)/R3 ≤ 10uA
Tratio = 0.442
R1 = R3 x (Vh/VHYST)
R2 = 1/[(VRISING/(1.2 x R1)) – (1/R1) – (1/R3)]
Secondary to Primary (Ns/Np) Turns Ratio
For our design, we will increase the Turns Ratio
to 0.444. 0.444 gives a Np/Ns Turns Ratio of
2.25:1, a more practical value.
•
Required Primary Inductance:
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 12
AN-194
Vh = Desired Hysteresis
Copyright  2010
Rev. 0.2, May, 2011
W W W. Microsemi .CO M
The time required for soft start to complete is
determined by the time required for the SS pin
voltage to transition from 0 to 1.1V (min). This
can be calculated with the following equation:
Design Example
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
T
Using PD70101/PD70201 PD Front-End With
Integrated PWM Controller ICs
C OMPANY C ONFIDENTIAL
Krf := 0.7
•
Based on the calculations above, the following
can be given to a transformer manufacturer for
transformer fabrication:
Primary Voltage Range:
Vmin = 32
Vmax = 57
Krf is the ratio of inductor ripple to inductor average current
Secondary Voltage & Power:
Vout = 12
2
 Vout + ddrop 

Tratio


Lpri :=

 Vout + ddrop  ⋅  Vout + ddrop  + Eff ⋅ Vmin
Krf ⋅ Fsw ⋅ Pout ⋅ Vmin + 
 


Tratio
Tratio


 


2
Transformer Specifications:
Eff ⋅ Vmin ⋅ 
Pout = 48
Auxilliary Voltage & Power:
Vaux = 12
−5
Lpri = 3.054 × 10
Paux = 1.2
5
Fsw = 2 × 10
Nominal Primary Inductance (allows for +/- 15%):
Dmin :=
−5
Lnom := Lpri ⋅ 1.15
W W W. Microsemi .CO M
Minimum required primary inductance is based on
the desired ripple factor (Krf), which is defined as
the percentage of peak to peak inductor ripple
current versus inductor average current. This
number sets the point in which the primary
inductance changes from CCM to DCM operation.
A good rule of thumb is to set this number
between 0.5 to 1.4. For our design, we will set it
to 0.7.
Lnom = 3.512 × 10
Switching Frequency
Vout + ddrop
Vout + ddrop + Tratio⋅ Vmax
Dmin = 0.323
Maximum Primary Operating Volt-Seconds:
•
Transformer Primary/Secondary Currents:
Vsecmax :=
Average Input Current:
Fsw
−5
Vsecmax = 9.193 × 10
Open Circuit Primary Inductance (+/- 15%):
Pout
Iinavg :=
Dmin ⋅ Vmax
Iinavg = 1.667
Eff ⋅ Vmin
−5
Lnom = 3.512 × 10
Turns Ratio:
Average Primary Current:
Iinavg
Ipriavg:=
Naux :=
Ipriavg = 3.623
Dmax
Vaux
Nsec/Npri:
Primary Ripple:
Naux/Nsec:
Ipriripple := Ipriavg⋅ Krf
Turns Ratio Calculation for Aux Winding
Vout
Ipriripple = 2.536
Tratio = 0.444
Npri/Nsec:
1
Tratio
= 2.252
Naux = 1
Winding Currents:
Peak Primary Current:
Ipripk :=
Ipriripple
2
+ Ipriavg
Ipripk = 4.891
•
Primary Circuit RMS Current:
2

Ipriripple 
2

Iprirms := Dmax ⋅ Ipripk − ( Ipripk⋅ Ipriripple) +
3


Secondary Circuit RMS Current:
Isecpk :=
Ipripk
Isecpk = 11.016
Tratio
Isecrms :=



( 1 − Dmax) ⋅ Isecpk −  Isecpk ⋅


2
2
Ipriripple 
+
2 
Tratio 
Tratio ⋅ 3 
Ipriripple 
Isecrms = 6.118
Copyright  2010
Rev. 0.2, May, 2011
Ipriavg = 3.623
Ipripk = 4.891
Isecrms = 6.118
Primary Clamp Equations:
The maximum transformer primary voltage seen
across the VDS of the primary transistor during the
off period will be greater than the maximum input
voltage by a factor of the secondary voltage
reflected by the transformer’s turns ratio plus the
voltage generated by the leakage inductance of
the primary. Because of this, a suitable clamp is
required to insure the primary voltage does not
exceed the transistor’s maximum VDS. There are
many types of clamps available to the designer;
each has it’s merits and drawbacks. For this
design the more common RCD clamp will be
used. An example of an RCD clamp is outlined in
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 13
AN-194
Iprirms = 2.507
Iprirms = 2.507
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
T
Using PD70101/PD70201 PD Front-End With
Integrated PWM Controller ICs
C OMPANY C ONFIDENTIAL
figure 7. The first step is to select a maximum
VDS transistor rating. The reflected voltage is
found:
Desired Clamp Capacitor Ripple Voltage:
Vcripple := Vclamp ⋅ 0.1
Clamp Coefficient:
 Vout + ddrop  + Vmax

Tratio


Vd := 
Vd = 84.141
Kccalc = 1.598
Resistor Calculation:
Vd=the reflected voltage across the transistor
Based on the above equation, the transistor
selection will need to have a VDS rating
considerably larger than 85V. 100V does not
leave margin for voltage overshoot, and would
require significant power loss to achieve, so a
150V transistor will be used.
Next, the maximum clamp voltage and a clamping
coefficient is calculated using the chosen VDS
rating de-rated by 15%. The clamping coefficient
is simply the ratio
Tratio⋅ Vclamp
( Vout + ddrop)
2
2

2
Tratio ⋅ Fsw ⋅ Lleak ⋅ Ipripk
Rclmp = 837.011
Resistor Power Dissipation:
2
Prclmp := 0.5⋅ Fsw ⋅ Lleak ⋅ Ipripk ⋅
Kccalc
Kccalc − 1
Prclmp = 2.246
Vclamp = 43.359
Cclmp :=
Clamp Coeffient based on selected Turns Ratio:
Kccalc :=
( Kccalc − 1) ⋅ 2 ⋅ Kccalc ⋅ ( Vout + ddrop)
Capacitor Calculation:
Clamp Voltage Limit (with BVdss derated):
Vclamp := BVdss ⋅ 0.85 − Vd
Rclmp :=
W W W. Microsemi .CO M
Reflected Mosfet Drain Voltage:
Kccalc ⋅ ( Vout + ddrop)
Tratio⋅ Rclmp ⋅ Fsw ⋅ Vcripple
−8
Cclmp = 5.974 × 10
Kccalc = 1.598
Clamp Current Calculation:
Maximum Transistor Stress Voltage:
Vstress := Vd + Vclamp
Vstress = 127.5
Trst :=
Tratio⋅ Lleak ⋅ Ipripk
Tratio⋅ Vclamp − ( Vout + ddrop)
BVdss ⋅ 0.85 = 127.5
Using Leakage inductance estimated at 1% of the
primary inductance, and the values calculated
above, the final RC values are calculated:
Leak L Reset Time:
Iclmprms := Ipripk⋅
Estimated Leakage Inductance:
Lleak := Lnom ⋅ 0.01
Leakage is set at 1% of total primary inductance
−7
Trst = 1.059 × 10
Trst ⋅ Fsw
3
Iclmprms = 0.411
Based on the above equations, the clamp resistor
will need to be 3 X 2.7K Ohm, 1W 5% resistors in
parallel. The capacitor will need to be a .068µF,
100V capacitor.
Clamp Voltage Limit:
Vclamp = 43.359
Vstress = 127.5
Iclmprms = 0.411
A 200V, 1A ES1D Diode is selected.
Note that the above component selections will
require final tweaking at the prototype stage.
Copyright  2010
Rev. 0.2, May, 2011
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 14
AN-194
Using the clamp current and maximum stress
voltage the diode is selected. A fast diode is
desired.
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
T
Using PD70101/PD70201 PD Front-End With
Integrated PWM Controller ICs
C OMPANY C ONFIDENTIAL
•
Primary FET Requirements:
Falling Gate Current and Turn-off Time:
Igf1 :=
Igf2 :=
Iprirms = 2.507
Igf1 = 1.41935
Rlo + Rg
Vcc − Vgsmiller
∆toff :=
A FDMS86200 FET by Fairchild has a VDS rating
of 150V, maximum continuous IDS rating of 9.6A,
and a specified RDSon of 18mΩ at 25°C.
•
Vcc − [ 0.5⋅ ( Vgsmiller + Vth ) ]
Igf2 = 1.30645
Rlo + Rg
Qgs
Igf1
Qgd
+
−9
∆toff = 7.93701× 10
Igf2
Valley Current:
Ivalley := Ipriavg −
Primary FET Power Dissipation:
Ipriripple
Ivalley = 2.30496
2
Operational Primary RMS Current:
W W W. Microsemi .CO M
The primary FET will be chosen based on
maximum primary RMS current, and maximum
VDS stress. Note that the maximum stress has
already been accounted for; we will chose a 150V
FET based on the primary RMS Current and
RDSon.
Selected Transistor: FDMS86200
Chosen RDSon (at 100°C):
RDSon := .03
Chosen θja:
θja := 50
Iprirms = 2.48022
Conduction Loss:
2
Chosen Ambient T:
Pcond := Iprirms ⋅ RDSon
Tamb = 70
Turn On Switch Loss:
Tj := 100
Chosen Max. Junction T:
BVdss = 150
Transistor BVdss:


Ivalley⋅  Vmin +
Pswon :=
Transistor Power Limit:
Tj − Tamb
Pswon = 0.06515
Qgs := 2.9n
Turn Off Switch Loss:
Transistor Qgs2:
Transistor Qgd:
Qgd := 7.7n
θja
Transistor gate resistance:
Pswoff :=
Vout + ddrop 
Tratio
6
Plimit = 0.6
Plimit :=
Pcond = 0.18454
Vclamp = 43.3591
Ipripk⋅ ( Vmin + Vclamp ) ⋅ ∆toff
Rg := 1.2
 ∆ton

⋅ Fsw
2
⋅ Fsw
Pswoff = 0.28634
Total Power Loss:
Transistor gate voltage at start of miller effect:
Vgsmiller := 3.9
Transistor gate threshold voltage:
Vth := 2.5
Transistor gate drive max voltage:
Vcc := 12
Gate drive on resistance:
Rhi := 10
Gate drive off resistance:
Rlo := 5
Plosstot := Pcond + Pswon + Pswoff
In the above calculations, RDSon is derated at
100°C. Values for Vth, Qgd and Rg are available
in most MOSFET datasheets. Qgs2 is the
switching gate charge; if not specified, it may be
estimated using the Vgs vs Gate charge graph
(found in all MOSFET datasheets) by determining
the equivalent charge between Vth and Vgsmiller.
Rising Gate Current and Turn-on Time:
Ig1 :=
Rhi + Rg
Vcc − Vgsmiller
∆ton :=
Rhi + Rg
Qgs
Ig1
+
Copyright  2010
Rev. 0.2, May, 2011
Qgd
Ig2
•
Ig1 = 0.78571
Ig2 = 0.72321
−8
∆ton = 1.43378× 10
Synchronous FET Requirements:
The output synchronous FET is chosen by
calculating the maximum DS voltage created
during the primary on time (sync FET is off), and
the maximum secondary RMS current. To derate the FET, DS voltage is increased by 30%
and DS current is increased by 50% for proper
FET selection.
Microsemi
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AN-194
Ig2 :=
Vcc − [ 0.5⋅ ( Vgsmiller + Vth ) ]
Plosstot = 0.53603
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Using PD70101/PD70201 PD Front-End With
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The output filter capacitor is chosen based on the
desired output voltage ripple, output voltage
undershoot (droop) during load step, and the
RMS ripple current the capacitor must endure.
Maximum Primary Reflected Voltage across FET:
Vsecref := Vmax ⋅ Tratio + Vout
Vsecref = 37.308
Vsecref ⋅ 1.3 = 48.5
Desired Output Ripple: Vripple := 0.1
Irect := Isecrms ⋅ 1.5
Desired Closed-Loop Bandwidth: Fc := 4k
Irect = 9.177
A FET is chosen with a VDS of 60V or higher, and
a current capability of 9 Amps or greater. Chosen
is the FDMS86322. This FET has an RDSon
(25°C) of 0.007 at 13A, and a maximum VDS of
80V.
W W W. Microsemi .CO M
Maximum FET Current (de-rated):
Desired Output Droop Load Step: Vdroop := 0.6
Load Step: Istep := Iout ⋅ 0.9
Isecpk = 11.016
•
Synchronous FET Power Dissipation:
Ioutavg :=
ddropcalc := Isecrms ⋅ rdson
ddropcalc = 0.077
rdson = 0.013
Iinavg
Ioutavg = 3.754
Tratio
Voltage drop across the transistor
Isecrms = 6.118
Rdson at 100°C
Rectifier Power Loss:
Icoutrms :=
Prect := Isecrms ⋅ ddropcalc
Prect = 0.473
Cesr :=
Rectifier Junction Temp:
Tamb = 70
Cout :=
Thetajarect := 50
Package theta ja
Jtrect := Thetajarect⋅ Prect + Tamb
2
2
Isecrms − Ioutavg
Icoutrms = 4.831
Vripple
Isecpk
Istep
2 ⋅ π ⋅ Vdroop ⋅ Fc
−3
Cesr = 9.077 × 10
−4
Cout = 2.387 × 10
Jtrect = 93.654
Chosen Output Capacitor:
•
Sense Resistor Calculation:
The sense resistor is chosen based on the
maximum peak current expected, and the voltage
threshold where the controller starts to limit
current. For the PD70201, the current limit
threshold voltage is 1.2V with a gain of 5 current
sense amplifier, so the resistor is sized such that
the operating peak primary current develops at
approximately 90% of this value. 1.1V is
approximately 90% of 1.2V.
Coutact := 360u
Cesract := 0.008
For the output capacitor, we will choose 2x Sanyo
OSCON 25SVPF180M capacitors in parallel.
These are 180µF, 25V capacitors with an ESR of
16m Ohm and a maximum ripple capability of
4.65ARMS.
•
Vthreshold := 1.1
Sense Resistor Value (accounts for X5 gain):
Vthreshold
Rsns = 0.04596
Ipripk⋅ 5
2
Prsns := Iprirms ⋅ Rsns
Prsns = 0.2827
The above takes into account Av = 5 for the current sense amplifier.
A 47mΩ 1/2W resistor will meet the requirment.
•
Output Capacitor Calculation:
Copyright  2010
Rev. 0.2, May, 2011
The input filter is used to reduce the voltage
fluctuations seen at the DC/DC converter input
due to the large peak currents involved. There
are several approaches to providing an input
filter; the input filter can consist of a simple input
capacitor (usually several capacitors in parallel
due to the large ripple currents), or can be a more
complex LC filter. For this design, we will choose
an LC filter as our input filter. The input to the LC
filter will be a common aluminum electrolytic; the
output of the LC filter will consist of smaller
ceramic capacitors to absorb the ripple current.
Microsemi
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11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 16
AN-194
Rsns :=
Input Filter Calculation:
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®
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Using PD70101/PD70201 PD Front-End With
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C OMPANY C ONFIDENTIAL
Our design requires the ripple voltage on VPP to
be 50mV or less. We will first choose a suitable
ripple voltage at the primary, and then size the
input capacitor to achieve that ripple voltage. The
input capacitor will need to absorb most of the
primary ripple current, so it’s ripple handling
capability is critical. Ceramic capacitors have
very good ripple current capability and are a good
choice for the input capacitor for this design.
Filter Attenuation Desired:
First we will determine the maximum ripple
current seen by the capacitor, and use this use
this current to select a suitable input capacitor
based on our selected primary ripple of 320mV:
Lin1 :=
2
Filter Cutoff Frequency for Required Attenuation:
Fo :=
1
2
2
InputfilterIrms = 0.01837
For this design we will use a 4.7µH inductor. This
inductor needs to handle the maximum Primary
RMS current at low line, and should be sized with
a minimum DCR to increase efficiency.
Cinputrms ⋅ Dmax
Finally, we will need to check our filter for stability.
In order for the filter to be stable, the filter output
impedance must be less than the input
impedance of the DC-DC converter. The input
impedance is calculated at DC for a first order
check. The filter output impedance is compared
at two frequency points: DC (which is simply the
DCR of the inductor), and at the resonant point
where peaking occurs due to the filter Q:
−5
Cmin = 1.34888× 10
For this design, we will choose 4x 4.7µF 100V
ceramic capacitors in parallel. 4 capacitors are
chosen to account for capacitor tolerance
variation. The ceramic capacitors chosen (1812
case size) have a ripple capability at 100 kHz of
greater than 2A for a 20°C case temperature rise.
2
Zinsmpsdc :=
Vmin ⋅ Eff
Pout
The capacitors chosen will meet more than this
requirement.
Zinsmpsdc = 19.2
Next, we will determine the voltage developed
across our chosen input capacitors:
Zoutfilterdc := DCR
Converter Input Impedance at DC
Filter Output Impedance at DC
Zoutfilterdc = 0.045
Actual capacitance - 20% tolerance
Filter Output Impedance at resonant point:
Cinesr := 1.2m
deltavin :=
Lin1 = 4.22172× 10
InputfilterIrms := A ⋅ Cinputrms
Vinripple := 0.32
Cminact := 15u
−6
2
4π ⋅ Fo ⋅ Cminact
Iprirms − Iinhigh
Fsw ⋅ Vinripple
4
Fo = 2 × 10
Required Lin vs Cin:
Cinputrms = 1.873
Cmin :=
A ⋅ Fsw
Cinputrms ⋅ Dmax
Fsw ⋅ Cminact
+ Ipriavg⋅ Cinesr
Zoutfiltermax :=
(Cinact ⋅ESR2 + Linact) ⋅(Cinact ⋅DCR2 + Linact)
2
Cinact ⋅ ( ESR + DCR)
deltavin = 0.29202
2
Zoutfiltermax = 6.804
Next we will chose an inductor based on the
desired attenuation. For this design, we will
attenuate the input current by 40dB:
Control Loop Calculations:
Control loop calculations are made by
determining the modulator and filter gain and
phase at the desired crossover frequency, and
then selecting feedback components to increase
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 17
AN-194
The calculated output impedance of our filter at
DC is 45mΩ; at the resonant point it is 6.8Ω.
Both of these values are less than the Converter
DC input impedance of 19.2Ω; our filter values will
not cause stability issues.
•
Copyright  2010
Rev. 0.2, May, 2011
W W W. Microsemi .CO M
Cinputrms :=
A := 0.01
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
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Using PD70101/PD70201 PD Front-End With
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C OMPANY C ONFIDENTIAL
Gxo := 20⋅ log ( H ( 2 ⋅ π ⋅ i⋅ Fc )
Gxo = −5.179
)
Gain at crossover point (dB)
Pxo := arg( H ( 2 ⋅ π ⋅ i⋅ Fc ) ) ⋅
Pxo = −88.008
180
π
Phase shift at crossover point (Degrees)
Calculation of Right Hand Plane Zero:
Rload :=
Once the gain and phase are known, the loop
must be closed such that the gain at the
crossover frequency is equal to 1 (0dB), and the
phase margin is greater than 45°.
Vout
Iout
2
Fzrhp :=
( 1 − Dmax) ⋅ Rload
4
Fzrhp = 4.372 × 10
2
2π Dmax ⋅ Lnom ⋅ Tratio
3
Fzrhp ⋅ 0.2 = 8.744 × 10
This number must be
greater than the proposed
crossover frequency.
Our proposed crossover frequency is 4kHz; we
have plenty of margin.
The modulator and filter gain-phase of our
regulator utilizes the following transfer function:
In most isolated designs, the feedback loop is
closed by means of an optocoupler which bridges
the primary/secondary isolation barrier. The
optocoupler is chosen to account for the isolation
requirements and the input/output current gain
(noted as a percentage, “CTR”, which translates
to the percentage of input LED current transferred
to the output). For our design, the optocoupler
will drive the PD70201’s COMP pin directly. The
optocoupler components are selected as follows:
W W W. Microsemi .CO M
(or decrease) the gain for unity gain at the
crossover point. First, the modulator and filter
must be evaluated to determine the frequency
location of the Right Hand Plane Zero (inherent in
CCM Flyback designs), and assure that the
chosen crossover frequency is less than 20% of
that frequency:
Optocoupler Calculations:
Ipripk
Kcc :=
Current Control Factor
1.2
1
ωz1 :=
Optocoupler: NEC PS2711-1-M-A
Vdd := 5.0
Vdd = PD70201's VL typical output voltage
Rpullup := 1k
Capacitor ESR zero
Cesract ⋅ Coutact
Vf := 1
Rpullup added to increase Optocoupler pole
frequency
Vcesat := 0.3
Tf := 5u
2
( 1 − Dmax) ⋅ Rload
ωz2 :=
Dmax ⋅ Lnom ⋅ Tratio
ωp :=
Rl := 100
RHP zero
2
These values are fall time test conditions found in the
datasheet; used for estimating the pole capacitance;
Tf = fall time, RI = test load.
CTRmax := 2.00
( 1 + Dmax)
CTRmin := 1.00
Load pole
Rload⋅ Coutact
Ioptomin :=
Vro :=
Dmax
1 − Dmax
⋅ Vmin
Reflected output voltage
Vdd − 1.2
−3
Ioptomin = 3.8 × 10
Rpullup
 Vdd − Vcesat 
 + 500u
 Rpullup 
Ioptomax := 
−1
H ( s ) :=
Kcc ⋅ Rload⋅ Vmin ⋅ Tratio
2 ⋅ Vro + Vmin
⋅
s  
s 

1 +
 ⋅ 1 −

ωz1
ωz2



1+
Ioptomin assumes 1.2 max regulation input for PD70201;
Ioptomax adds maximum Error Amp Comp pin current
capability.
s
Optoisolator Characteristic Pole Capacitor:
ωp
Tf
−8
Cpole = 2.273 × 10
2.2⋅ Rl
ωpopto :=
Iledmin :=
1
Rpullup⋅ Cpole
fpopto :=
ωpopto
3
= 7.003 × 10
2⋅ π
Ioptomin
CTRmax
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
−3
Iledmin = 1.9 × 10
Page 18
AN-194
Cpole :=
Solving for H at the crossover frequency:
Copyright  2010
Rev. 0.2, May, 2011
−3
Ioptomax = 5.2 × 10
Designing a Type-1/2 IEEE 802.3at/af Powered Device
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Using PD70101/PD70201 PD Front-End With
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C OMPANY C ONFIDENTIAL
Cpcalc :=
1
2 ⋅ π ⋅ Rpullup⋅ fp431
− 8 Calculated Pole Capacitor
Cpcalc = 1.137 × 10
−8
Cpole = 2.273 × 10
Optoisolator Pole Capacitor
TL431 Calculations:
Actual Compensation Values Used:
Reference Resistors:
Rled := 825
Vref := 2.5
Cz := 330n
Iref := 4u
Iresistordivider := 1m
Rlowercalc :=
Cp := 22.7n
Vref
Actual resistor used
TL431/Optoisolator Transfer Function:
( Vout − Vref )
Iresistordivider + Iref
Rupper := 9.53k
3
Ruppercalc = 9.462 × 10
 s ⋅ Rupper⋅ Cz +
 s ⋅ Rupper⋅ Cz
G ( s ) := −
Actual resistor used


+ Iref ⋅ Rupper + Vref
 Rlower

Voutcalc := 
Finally, the chosen values are used in the
TL431/optocoupler Transfer Function:
3
Rlowercalc = 2.5 × 10
Iresistordivider
Rlower := 2.49k
Ruppercalc :=
If Cpole less than 5x Cpcalc, use
Cpole in the Transfer Function
W W W. Microsemi .CO M
On the secondary side, the optocoupler must be
driven with an error amplifier that regulates the
output voltage. Most designs utilize a common
TL431 shunt regulator, due to it’s ability to
regulate without requiring additional input power
for operation. The compensation components, as
well as the DC setting resistors will be placed
around the TL431. First, the DC setting resistors
are calculated:
Vref
Voutcalc = 12.106
1
 Rpullup ⋅ CTRtyp

 ⋅
⋅
  1 + s ⋅ Rpullup⋅ Cp  Rled
Bias Resistor:
Rbias :=
Next, the compensation components are
selected:
1
Rled⋅ Iledmin + Vf
Ibias
3
Rbias = 1.284 × 10
431 Compensation (Type Two):
Gxo = −5.179
Modulator and Filter gain at Fc (dB)
 Gxo 


20 
Gc := 10
Gc = 0.551
G431 :=
1
Gc
Gtot431 ( s ) := H ( s ) ⋅ G ( s )
Modulator and Filter gain at FC (mag)
Compensation Zero; set to 1/4 Load Pole
fp431 := 14k
Compensation Pole; set to 1/4 ESR zero
Ibias := 2m
431 bias for regulation
CTRtyp := 1.5
Optoisolator CTR typical
AN-194
CTRtyp⋅ Rpullup
G431
Rledcalc = 826.267
Czcalc :=
A Bode Plot of the overall loop gain is shown in
Figure 6.
= 1.815 Required feedback gain
fz431 := 54
Rledcalc :=
The two functions are multiplied together to
achieve the overall loop gain:
LED Resistor
1
2 ⋅ π ⋅ Rupper⋅ fz431
−7
Czcalc = 3.093 × 10
Copyright  2010
Rev. 0.2, May, 2011
Calculated Zero Capacitor
Microsemi
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Page 19
Designing a Type-1/2 IEEE 802.3at/af Powered Device
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T
Using PD70101/PD70201 PD Front-End With
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C OMPANY C ONFIDENTIAL
Overall Loop Gain TL431 Compensation
W W W. Microsemi .CO M
100
0
− 100
10
100
1×10
3
1×10
4
1×10
5
1×10
6
Frequency
Gain
Phase
Figure 6. Loop Bode Plot
Synchronous Gate Drive:
Copyright  2010
Rev. 0.2, May, 2011
When selecting the components for the
synchronous FET gate drive, first the transformer
should be selected based on the maximum voltmicroseconds of the SG pin drive output.
Maximum volt-microseconds is calculated:
AN-194
The PD70201 provides a dedicated output driver
for a Synchronous FET. This output is available
on the SG pin (pin 25). To adhere to the isolation
requirements, the SG output is transformer
coupled to the Synchronous FET. A coupling
capacitor is required in series with the primary to
reset the magnetizing inductance. The
transformer will saturate without it. The LC tank
circuit formed by the coupling capacitor and the
transformer magnetizing inductance can generate
oscillations during sudden changes in duty cycle.
A damping resistor in series with the coupling
capacitor should be used to damp oscillations.
On the secondary side, a DC restoration and fast
gate turn-off circuits are provided to keep the gate
drive voltage constant over varying duty cycle,
and to insure fast transistor turn off.
Referencing Figure 9, DC restoration is provided
via Capacitor C20, and Diode D7. The fast turnoff circuit consists of R14, Q3 and D6. Resistor
R11 limits the synchronous MOSFET’s turn-on
rate of rise, and is optional (can be used to limit
EMI).
VCCmax := 15
Dmin = 0.323
Vgdusecmax :=
Duty Cycle at High Line
( 1 − Dmin) ⋅ VCCmax
Fsw
Microsemi
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−5
Vgdusecmax = 5.081 × 10
Page 20
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
T
Using PD70101/PD70201 PD Front-End With
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C OMPANY C ONFIDENTIAL
Because of the capacitor in series with the
primary, the drive voltage is bipolar. The
calculated maximum volt-microsecond value may
divided by 2 for transformer selection due to the
bipolar drive.
Once the primary side capacitor is determined,
the series damping resistor is found:
Cc1act := 1.0u
Lm
Cc1act
A total series resistance of 34Ω is required. This
resistance includes the PD70201’s drive resistance of
10Ω, meaning an additional resistance of 24Ω must
be added. Resistor power is calculated assuming the
transformer magnetizing current is dominant:
Once the transformer is selected, the two
coupling capacitor values are calculated. The
coupling capacitor values will determine the
amount of ripple voltage seen at the gate of the
synchronous FET; total gate ripple will be the sum
of the individual capacitor ripple voltages.
drcurrentpk :=
To size the coupling capacitors, first determine
the maximum ripple we will allow each capacitor
to contribute to the overall gate ripple voltage.
(~1% of the maximum gate drive voltage is
chosen for our design). Next, factor in the values
for synchronous FET gate charge, and the current
flowing in the pull down resistor, R14:
⋅
drcurrentpk = 0.137
( 1 − Dmin)
3
drcurrentrms = 0.065
2
drvpwr:= drcurrentrms ⋅ 24
FDMS86322 Gate Charge
Vdrv := 12
Nominal Gate Drive Voltage
∆Vc1 := 0.1
Desired Ripple Across Primary Cap
∆Vc2 := 0.1
Desired Ripple Across Secondary Cap
Rgs := 1k
Gate Resistor
D := 0.95
Off Time Duty Cycle (increased
to account for transients)
drvpwr = 0.102
Calculated Resistor Power
Our chosen resistor is 24Ω, 1W. This is a standard
value.
The following pages contain a schematic and bill of
material for the above example.
Magnetizing Inductance
5
Fsw = 2 × 10
Cc2 :=
 ( 1 − Dmin) 

Fsw 
Lm 
Vdrv
drcurrentrms := drcurrentpk
Qg := 31n
Lm := 296u
⋅ 2 = 34.409
Qg
∆Vc2
Switching Frequency
( Vdrv − 0.7) ⋅ D
+
∆Vc2 ⋅ Rgs ⋅ Fsw
−7
Cc2 = 8.467 × 10
Secondary Side Capacitor
Qg
∆Vc1
( Vdrv − 0.7) ⋅ D
+
∆Vc1 ⋅ Rgs ⋅ Fsw
−7
Cc1 = 9.611 × 10
+
(
2
3
Vdrv⋅ D − D
AN-194
Our design will use a 1µF capacitor on the
secondary side. On the primary side:
Cc1 :=
W W W. Microsemi .CO M
The magnetizing inductance will affect the
transient response of the isolated drive signal.
Generally a lower inductance will produce a faster
response time. Our selected transformer has a
magnetizing inductance of 296uH.
Primary Side Capacitor
)
∆Vc1 ⋅ 4 ⋅ Lm ⋅ Fsw
2
Primary Side Capacitor
We will use a 1uF capacitor on the primary side.
Copyright  2010
Rev. 0.2, May, 2011
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 21
VP6014 LF
Copyright  2010
Rev. 0.2, May, 2011
DATA &
POWER IN
T1
23
24
22
20
21
19
17
18
16
14
15
13
4
D4
DATA OUT
-
2
1
3
5
4
6
8
7
9
11
10
12
2
~
~
3
+
1
2
~
+
R7
243K
~
3
D1
R2
24.9K
VPP
8
7
6
5
4
3
2
1
EP
1
R16
9.53K
R12
316k
VPNO
ATFLAG
NC
VPNI
RCLASS
RREF
PGOOD
RDET
EP
+
1
C12
100n
1
392K
R15
2
4.7uH
L1
C1
47uF
100V
VPPout
U1
PD70201
C2
4.7uF
100V
X7R
1
R13
49.9K
17
18
19
20
1
1
C3
4.7uF
100V
X7R
SG
21 VL
22
23
24
100n
16V
C18
VSN
VSP
COMP
DAO
FB
GND
VL
SG
C21
4.7uF
100V
X7R
1uF
C16
VL
1
25
C13
100n
C4
4.7uF
100V
X7R
C14
10U
25V
X7R
C5
100n
100V
R37
2.7K
1W
CSN
CSP
D3
SS16
1
R38
2.7K
1W
Microsemi
2
24
VPPout
R4
0.047
1/2W
R19
1 2 3
FDMS86200
C6
68n
100V
8 7 6 5
ES1D
D2
SG
Q2
4
2
1
R1
2.7K
1W
2
3
1
5
T2
3
1
1
3
4
R5
1K
100K
R18
2
1
T3
6
7
10
9
U3
Q1
2
1
R3
825
FDS86322
D1
S1
D2
S2
D3
S3
D4 GATE
4
6
PS2711-1-M-A
U2
8
7
6
5
GDRIVE
1u
16V
X7R
C20
1
2
3
4
R17
47K
PS2711-1-M-A
3
4
12V
SECONDARY
FA2659-AL
1n 2000V
PRIMARY
1u
16V
X7R
C19
VL
C15
C OMPANY C ONFIDENTIAL
Figure 7. PD70201 48W Example Design
R9
30.9
C11
68nF
100V
1
29
Using PD70100/PD70200 Front-End ICs
CSN
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
4
32
VPP
NC
9
VCC
VINS
31
VAUX
ENABLE
10
CSP
27
CSP
30
12
HYST
11
VH
HYST
25
PGND
28
PG
SYNC
13
26
CSN
RFREQ
14
SS
15
RCLP
16
®
1
2
/ATFLAG
D7
LL4148
2
C7
180uF
+
3
5
-
TM
330n
C9
1u
25V
X7R
R14
1K
D5
TL431ACDBVR
1
4
C17
R6
1.2K
C8
180uF
+
2
R10
2.49K
1
LL4148
D6
L2
1uH
2
C10
10uF
1
Q3
MMBT2907AWT1G
GDRIVE
4
3
2
1
12V @ 4.0 AMPS MAX
CI5104P1V00
4
3
2
1
J1
Page 22
L2 AND C10 ARE OPTIONAL
1
R8
9.53K
12V
2
3
Designing a Type-1/2 IEEE 802.3at/af Powered Device
W W W. Microsemi .COM
AN-194
L1
L2
Q1
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Microsemi
1
1
1
23
24
25
Copyright  2010
Rev. 0.2, May, 2011
CAP ALU 47µF 100V 20%
Panasonic
CAP CER 4.7µF 100V 20% X7R ^1210 SMT
CAPAX
CAP CRM 100nF 100V 10%^^X7R 1206 SMT
EPCOS
Capacitor, 180µF, 16m Ohm ESR, 4.65A ripple current Sanyo
CAP CRM 1µF 25V 10% X7R, 1206
TAIYOYUDEN
CAP X7R 10µF 16V 10% 1206
TDK
CAP CRM 68nF 100V 10%^^X7R 1206 SMT
AVX
CAP CRM 100nF 25V 10%^^X7R 0805 SMT
Murata
Capacitor, X7R, 10µF, 25V, 20% 1206
TAIYOYUDEN
CAP CRM 1nF/2000V 10%++X7R 1206 SMT
AVX
Capacitor,X7R, 1µF, 25V, 10% 0603
Murata
Capacitor, X7R, 330nF, 16V, 10% 0603
TAIYOYUDEN
Capacitor, X7R, 100nF, 16V, 10% 0603
TAIYOYUDEN
CAP CRM 1µF 16V 10%^^X7R 0603 SMT^^
Vishay
CAP CRM 1µF 16V 10%^^X7R 0603 SMT^^
Vishay
DIO bridge 100V 2.0A, SDB-1 case
Fairchild
DIO FAST SWI 200V 1A
Fairchild
Diode Schottky 1A 60V SMA
Fairchild
IC Adj Prec Shunt Reg 2.5V ^^1% SOT-23-5 SMT
Texas Instruments
DIO FAST SWI 75V 300mA^^4nS SOD80C MiniMELF Vishay
DIO FAST SWI 75V 300mA^^4nS SOD80C MiniMELF Vishay
PIN HEADER 4 PIN 0.156"^^TIN, WITH LOCKING
CviLux
WALL
INDUCTOR PWR 4.7µH 20%, 45mΩ, 2.2A
Wurth
Power Inductor 1µH SMT
Wurth
FET, N-Channel, 80V, 13A
Fairchild
C1
C2,C3,C4, C21
C5
C7,C8
C9
C10
C6,C11
C12,C13
C14
C15
C16
C17
C18
C19
C20
D1,D4
D2
D3
D5
D6
D7
J1
1
4
1
2
1
1
2
2
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CI5104P1V00
7440700047
7440690010
FDS86322
Page 23
EEU-FC2A470
1210X475J101SNT
B37872K1104K62
25SVPF180M
TMK316B7105ML-T
C3216X7R1C106K
12061C683KAT2A
GRM216R71E104KA01
TMK316AB7106KL-T
1206GC102KAT1A
GRM188R71E105KA12D
EMK107B7334KA-T
EMK107B7104KA-T
VJ0603Y105KXJT
VJ0603Y105KXJT
DF01S
ES1D
SS16
TL431ACDBVR
LL4148
LL4148
Manµfacturer Manufacturer Part
Number
C OMPANY C ONFIDENTIAL
Using PD70100/PD70200 Front-End ICs
Description
®
Item Number Quantity Part
Reference
Bill of Materials - PD70201 Example Design
TM
Designing a Type-1/2 IEEE 802.3at/af Powered Device
W W W. Microsemi .COM
AN-194
1
1
1
1
2
47
48
49
50
51
Copyright  2010
Rev. 0.2, May, 2011
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
T2
T3
U1
U2,U3
T1
Microsemi
Coilcraft
Microsemi
NEC
BOTHHAND
VP6014 LF
Custom build
FA2659-AL
PD70201
PS2711-1-M-A
Page 24
Fairchild
FDMS86200
ON Semiconductor
MMBT2907AWT1G
Panasonic
ERJ-1TYJ272U
Panasonic
ERJ6EKF2492V
Panasonic
ERJ3EKF8250V
Panasonic
ERJL1DKF47MU
Panasonic
ERJ3EKF1001V
Samsung
RC1608F1201CS
Panasonic
ERJ3EKF2433V
Panasonic
ERJ3EKF9531V
Panasonic
ERJ3EKF30R9V
Vishay
CRCW06032K49FKEA
Panasonic
ERJ3GEYJ4R7V
Panasonic
ERJ3EKF3163V
Panasonic
ERJ3EKF4992V
Panasonic
ERJ3GEYJ104V
Rohm
MCR10EZHFX3923
Rohm
MCR10EZPF 1242
Panasonic
ERJ3GEYJ473V
Panasonic
ERJ6GEYJ104V
Panasonic
ERJ8GEYJ240U
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
R1,R37,R38
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
1000 BASE –T SINGLE PORT VOICE OVER IP
MAGNETICS MODULE SMT
48W transformer
Transformer, Gate Drive, 1:1 turns ratio, 269µH
IC, POE PD Front End and PWM Controller
Optoisolator, CTR = 100 to 200
FET, N-Channel, 150V, 9A
TRN PNP 60V 600mA SOT323 SMT 250mW
MMBT2907AW^
RES 2.7K Ohms, 1W 5%, 2512 SMT
RES TK FLM 24.9K 100mW1% 0805
RES 825, 62.5mW 1%^^0603 SMT MTL FLM
RES .047 OHM 1/2W 1% 2010 SMD
RES 1.00K 62.5mW 1%^^0603 SMT MTL FLM
RES TCK FLM 1.2K 62.5mW 1%^^0603 SMT
RES 243K 62.5mW 1%0603 SMT MTL FLM
RES 9.53K 0.1W 1%^^0603 SMT MTL FLM
RES 30.9 62.5mW 1%0603 SMT MTL FLM
RES 2.49K 62.5mW 1%^^0603 SMT MTL FLM
Resistor, 4.7 Ohm, 5% 1/16W 0603
RES 316K 62.5mW 1%0603 SMT MTL FLM
RES 49.9K 62.5mW 1% 0603^^SMT
RES TCK FLM 10K 125mW 1%^^0805 SMT
RES 392K 125mW 1%^^0805 SMT MTL FLM
RES TK FLM 12.4K 125mW^^1% 0805
Resistor, 47K, 5%, 1/16W 0603
Resistor, SMT 100K, 5%, 1/16W 0805
Resistor, SMT, 24Ω, 5%, 1/4W, 1206
Q2
Q3
1
1
26
27
Manµfacturer Manufacturer Part
Number
C OMPANY C ONFIDENTIAL
Using PD70100/PD70200 Front-End ICs
Description
®
Item Number Quantity Part
Reference
Bill of Materials - PD70201 Example Design
TM
Designing a Type-1/2 IEEE 802.3at/af Powered Device
W W W. Microsemi .COM
AN-194
Designing a Type-1/2 IEEE 802.3at/af Powered Device
®
TM
Using PD70100/PD70200 Front-End ICs
C OMPANY C ONFIDENTIAL
W W W. Microsemi .CO M
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Revision History
Revision Level / Date
0.2/ May, 2011
Para. Affected
Description
Originate
© 2010 Microsemi Corp.
All rights reserved.
For support contact: [email protected]
Visit our web site at: www.microsemi.com
Catalog Number: PD70101/201_AN_194
AN-194
Copyright  2010
Rev. 0.2, May, 2011
Microsemi
Analog Mixed Signal Group
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 25
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