Micronote 1816 - Device Selection and Optimizing of Half Bridge RF Generators (159.39 kB)

```Application Note 1816
May 2011
Device Selection and Optimizing of Half Bridge RF Generators
George J Krausse III, Vice President, MOS RF
Microsemi Power Products Group
405 SW Columbia St., Bend, OR 97702 USA
[email protected]
The following Application Note is a SPICE Model tutorial on Half Bridge Topologies and device selection. We will
also discuss their relative performance with matched and reactive loads. This tutorial is based on new Large Signal
RF Spice Models developed at Microsemi PPG. The circuits include all significant strays at appropriate values. This
format allows us to explore operational elements that are exceedingly difficult, if not impossible, to measure
accurately even in a laboratory environment. In addition, it provides a valuable tool for the understanding of circuit
operation under varying load conditions and device type.
N Channel – N Channel Half Bridge
The Half Bridge Topology is used for this Device Characterization. Figure 1 illustrates the classical N Channel - N
Channel Half Bridge RF Generator. The High Side Switch X2 and the Low Side Switch X1 form the two active
devices in the Half Bridge. X1 and X2 commutate in an alternating fashion providing a pseudo Square Wave drive
to the input of the RF Network, at V5. The RF network provides an impedance match from the Drain Impedance of
X1, X2 of Figure 1. The match is 3Ω to the 50Ω load. During the evaluation, different devices will be examined.
This will necessitate changes in the network in order to provide an appropriate drain load match. This L Match
network is resonant at the frequency of the device evaluation.
This resonant network only performs the impedance translation at the design frequency. The common design
formulas account only for a resistive source and load. Since the output devices have parasitic capacitance, after the
network is designed, the series value of L4 may be adjusted to account for this capacitance. A value of L4 ≈ 0% to
25% higher than the calculated value is sometimes required to bring the network to peak efficiency.
Gate Driver
Table 1
Low Frequency Loop
V1
163
L1
10nH
V4
Tran Generators = PULSE
7
12
V3
1
L2
.15nH
R1
.15
7
20
IV4
7
4
4
4
4
1
1
10
L4
96n
V5
1
1
3
Resonant and
Matching Network
L3
5nH
7
X2
ARF460AB
V2
1
1
R2
.03
3
14
3
14
15
IV8
13
X1
ARF460AB
10
8
8
R5
50
*
WR5
17
WR2
C1
.02uF
2
V6
8
C3
319p
3
L5
.15nH
R3
.15
6
C2
.1u
*
*
IV1
WV1
Circuit Performance
High Frequency
Loop
5
WR4
*
5
R4
.01
2
V7
2
2
V8
Tran Generators = PULSE
2
2
Vsupply
+197V
Pout
2036W
Pin
2351W
PLoss
315W
Eff
86.6%
Pulse Gate Drive
PW=27ns
Ths
45°C
Tj X2
100°C
TjX1
100°C
Drain Z=3Ω
Out Z=50Ω
1
L6
10nH V9
RF Output Network
Figure 1. N - N Channel Half Bridge
Figure 1 illustrates an N-N Channel Half Bridge circuit Topology. The circuit contains two current loops. A low
frequency loop is highlighted in yellow. The High Frequency Loop is highlighted in red. These loops are illustrated
with near-minimum stray inductance. Great care should be taken to achieve inductance values near the illustrated
values of Figure 1. If we allow L2 to reach 100nH or greater, performance will be severely degraded. The
inductance of the Inner Loop, L3, is an extremely Critical Stray Component. Values greater than a few nH can cause
stability problems and excessive harmonics.
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Application Note 1816
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Given the preceding Half-Bridge Design discussion, we have evaluated several ARF devices in this topology using a
Spice circuit simulation based or our new device models, and correlated the performances with previous bench work
by the author. Circuit Parameters have been adjusted for the Highest Efficiency and Highest Power Output while
limiting the MOSFETs junction temperature to a maximum of ≈ 100°C and limiting the Drain to Voltage to VDS
Maximum. We have set the heat sink temperature at 45°C.
Figure 2 shows the resulting output of the simulations from 2MHz to 40MHz for each of the devices that were
selected for this Application Note.
Figure 2. RF Output Power vs. Frequency
In Figure 2 we see that the device with the dashed line plot seems very different than the other four devices. The
ARF300-ARF301 Half Bridge is limited in power by the characteristics of the P Channel device, the ARF301. The
proper drain load for the ARF301 is about 8Ω, for the ARF300 it is about 3Ω. The ARF300 is the device with the
lowest RDS(on) the ARF461 is the highest at 2Ω. The advantage of the ARF301 is the simplified drive circuit in Half
Bridge configurations, see Note 1.
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Application Note 1816
May 2011
Table 2
Data for Figure 3
Number
Figure 3. Loads vs. Configuration, N-N Sine, see Note 1.
Base
Line
1
2
3
4
5
6
7
8
Rs
Xs
Reactive
50
0
jXs
100
69.5
40
28.1
25
28.1
40
69.5
0
431nH
352.6nH
174.5nH
0
709pF
390pF
317pF
0
36.7
30
14.9
0
-14.9
-30
-36.7
Each of the loads illustrated in Figure 3 and the inset Table 2, present a 2:1 VSWR mismatch to 50Ω. They are
equally spaced every 45° around a 2:1 VSWR load circle. In the circuit of Figure 1, the 50Ω load is transformed by
the output matching network (L5+L6 and C2) to approximately 3Ω at the Drains of transistors X1 and X2. A load
other than 50Ω is “mismatched” and its effect on the circuit is quite different. From a reliability standpoint, keeping
the load between 3-4 on the left and at or below 7 on the right is the preferred operating space. In addition,
minimizing the time spent at or above 175°C is advisable.
An output load impedance lower than 50Ω will be transformed to a higher impedance load at the devices. The
transistors can more easily supply the full output voltage to this higher impedance. Consequently, the output power
is less and the junction temperature is lower. Load impedance greater than 50Ω on the output is transformed though
the matching network to an impedance lower than 3Ω at the transistor junction. This causes the devices to be
overloaded and mistuned. This puts the full voltage on this lower impedance, creating more output power at lower
efficiency, which in turn causes the rise in junction temperature. Figure 3 clearly demonstrates the importance of
maintaining a proper load on the output of the RF Generator. The addition of a fast protection circuit to limit power