AX5043 Use with a TCXO Reference Clock

APPLICATION NOTE AND9317/D
AX5043
Use with a TCXO Reference
Clock
Revision 2
2
Table of Contents
1. Introduction................................................................................................ 3
2. Connection of Clipped Sine Wave TCXOs ..................................................... 4
3. Connection of CMOS TCXOs ......................................................................... 6
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Introduction
1.
Introduction
This application note describes how to design an optimal connection between different
TCXO types and AX5043.
If this connection is not designed in an optimal way, the AX5043 RF Synthesizer may
produce higher phase noise than necessary, resulting in reduced selectivity in RX and
lower attainable output power for a given regulatory regime in TX.
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Connection of Clipped Sine Wave TCXOs
2.
Connection of Clipped Sine Wave TCXOs
For TCXOs having clipped sine wave outputs an external circuitry consisting of two
capacitors C1 and C2 as well as a resistor R are recommended. Component sizes as well
as register settings are given in the tables.
The voltage at node Vp should be the TCXO output signal without significant additional
distortion. The voltage at Vn should be a DC value equivalent to the mean value of the
waveform at Vp.
TCXO
C1
C2
Vn
Vp
R
external
Pin
CLK16P
Pin
CLK16N
internal
 3pF
 3pF
Ibias
 600k
M1
Figure 1 Configuration for a clipped sine wave output TCXO
Component
C1
C2
R
Value
1 nF
1 nF
1 k
Table 1 Component values
Register
Analog
Parameter
Value
0xF10
Ibias
0x04
0xF11
Ibias autoreg.
0x00
0x184
XTALCAP
0x00
Table 2 Register settings
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Connection of Clipped Sine Wave TCXOs
Vn
Vp
Figure 2 Voltages at nodes Vp and Vn
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Connection of CMOS TCXOs
3.
Connection of CMOS TCXOs
For TCXOs having CMOS outputs it is recommended to use a capacitive divider (C1 and
C2) to reduce the signal swing at the input pin CLK16P to between 1.5-2V peak-to-peak.
Pin CLK16N should be left open, to allow the internal circuitry to work as a fast inverter.
Component sizes as well as register settings are given in the tables.
The voltage at Vp should be the TCXO output signal without significant additional
distortion and with a peak-to-peak swing no larger than 2V. The voltage at Vn should be
the inverted waveform.
TCXO
Vtcxo
C1
C2
Vp
external
Pin
CLK16P
Vn
Pin
CLK16N
internal
 3pF
 3pF
Ibias
 600k
M1
Figure 3 Configuration for a clipped sine wave output TCXO
Component
C1
C2
Value
10 pF
6.8 pF
Table 3 Component values
Register
Analog
Parameter
Value
0xF10
Ibias
0x0F
0xF11
Ibias autoreg.
0x00
0x184
XTALCAP
0x00
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Connection of CMOS TCXOs
Table 4 Register settings
Vn
Vtcxo
(impact of
8pF
oscilloscope
probe visible)
Figure 4 Voltages at nodes Vtcxo and Vn
Vp
(8pF
oscilloscope
probe load
approx. halfs
the signal
swing)
Vn
Figure 5 Voltages at nodes Vp and Vn
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