AND9396/D PFC Converter + 3-phase Inverter IPM Application Note using the STK5MFU3C1A-E www.onsemi.com 1. Product synopsis This application note provides practical guidelines for designing with APPLICATION NOTE the STK5MFU3C1A‐E. The STK5MFU3C1A‐E is an Intelligent Power Module (IPM) for 3‐phase motor drives containing a single PFC boost stage, a three‐phase inverter stage, gate drivers for the PFC and inverter stages and a thermistor. It uses ON Semiconductor’s Insulated Metal Substrate (IMS) Technology. SIP3B The key functions are outlined below: Highly integrated power module containing a single boost PFC stage and inverter power stage for a high voltage 3‐phase inverter in a single in‐line (SIP) package. Output stage uses IGBT/FRD technology and implements Under Voltage Protection (UVP) and Over Current Protection (OCP) with a fault detection output flag. Internal bootstrap diodes are provided for the high‐side drivers. Thermistor for substrate temperature measurement. All control inputs and status outputs have voltage levels compatible with microcontrollers. Single VDD power supply due to internal bootstrap circuit for high‐side gate driver circuit. Mounting holes for easy assembly of heat sink with screws A simplified block diagram of a motor control system is shown in Figure 1. Gate Driver for Inverter AC Gate Driver for PFC Intelligent Power Module MCU Motor Figure 1. Motor Control System Block Diagram © Semiconductor Components Industries, LLC, 2016 May 2016 - Rev. 1 1 Publication Order Number: AND9396/D AND9396/D 2. Product description Table1 gives an overview of the device. For package drawing, please refer to Chapter 6. Device Package Voltage (VCEmax.) Current (Ic) Peak current (Ic) Isolation voltage Input logic Shunt resistor STK5MFU3C1A‐E SIP3B – horizontal pins 600V 30A 60A 2000V High‐active single shunt / external Table 1. Device Overview VDD (27) PFCL (1) Bootstrap VBU (9) Bootstrap VBV (6) Bootstrap VBW (3) VP1 (12) PFCIN(23) VP2 (13) W (4) V (7) U (10) PFC Driver HVGND (15) N (16) Level Shifter HINU (17) HINV (18) HINW (19) LINU (20) LINV (21) LINW (22) Level Shifter Logic VDD Level Shifter Logic VDD undervoltage shutdown Logic FAULT/TH (24) ITRIP (26) VITRIP Reset after delay PTRIP (25) GND (28) VPFCTRIP Figure 2. Internal Block Diagram Three bootstrap circuits generate the voltage needed for driving the high‐side IGBTs. The boost diodes are internal to the part and sourced from VDD (15V). There is an internal level shift circuit for the high‐side drive signals allowing all control signals to be driven directly from GND levels common with the control circuit such as the microcontroller without requiring external isolation with optocouplers. www.onsemi.com 2 AND9396/D 3. Performance test guidelines The methods used to test some datasheet parameters are shown in Figures 3 to 7. 3.1. Switching time definition and performance test method trr 10% 90% VCE 90% 10% Io td(ON) 10% td(OFF) tr tf tOFF tON IN Figure 3. Switching Time Definition Ex) Low side U phase VBU VP2 VBS=15V U VBV VBS=15V V U VBW VCC CS VBS=15V W VDD Io VDD=15V Input signal N LINU GND HVGND, ITRIP Figure 4. Evaluation Circuit (Inductive load) IPM VP2 HINU HINV HINW Ho CS LINU LINV LINW Input signal Driver VCC U,V,W Lo Io N Input signal Io Figure 5. Switching Loss Measurement Circuit www.onsemi.com 3 AND9396/D IPM VP2 HINU HINV HINW Ho CS Driver LINU LINV LINW Input signal VCC U,V,W Lo Io N Input signal Io Figure 6. Reverse Bias Safe Operating Area Measurement Circuit IPM VP2 HINU HINV HINW Ho CS Driver LINU LINV LINW Input signal VCC U,V,W Lo Io N Input signal Io Figure 7. Short Circuit Safe Operating Area Measurement Circuit www.onsemi.com 4 AND9396/D 3.2. Thermistor characteristics A thermistor is built‐in between FAULT/TH and GND. This is used to sense the internal substrate temper‐ ature. It has the following characteristics: Parameter Resistance Resistance Temperature Range Symbol R25 Condition Tc=25°C Min 99 Typ. 100 Max 101 Unit kΩ R100 Tc=100°C 5.18 ‐40 5.38 5.60 kΩ +125 °C Table 2. NTC Thermistor Specification Thermistor resistance value ‐ Case temperature Thermistor resistance value[kΩ] 10000 min 1000 typ max 100 10 1 -50 0 50 100 150 Case temperature [˚C] Figure 8. NTC Thermistor Resistance versus Temperature www.onsemi.com 5 AND9396/D Tc [°C] ‐40 ‐39 ‐38 ‐37 ‐36 ‐35 ‐34 ‐33 ‐32 ‐31 ‐30 ‐29 ‐28 ‐27 ‐26 ‐25 ‐24 ‐23 ‐22 ‐21 ‐20 ‐19 ‐18 ‐17 ‐16 ‐15 ‐14 ‐13 ‐12 ‐11 ‐10 ‐9 ‐8 ‐7 ‐6 ‐5 ‐4 ‐3 ‐2 ‐1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resistance value [kΩ] Min Typ Max 4191.52 4397.12 4612.34 3904.30 4092.87 4290.13 3638.69 3811.72 3992.58 3392.92 3551.75 3717.65 3165.38 3311.24 3463.47 2954.60 3088.60 3228.35 2759.25 2882.40 3010.74 2578.10 2691.31 2809.21 2410.02 2514.14 2622.49 2253.99 2349.78 2449.39 2109.07 2197.23 2288.84 1974.40 2055.56 2139.84 1849.20 1923.93 2001.49 1732.73 1801.57 1872.97 1624.34 1687.77 1753.51 1523.41 1581.88 1642.43 1429.20 1483.10 1538.88 1341.42 1391.11 1442.51 1259.58 1305.41 1352.78 1183.25 1225.53 1269.20 1112.02 1151.04 1191.30 1045.53 1081.54 1118.67 983.42 1016.66 1050.92 925.39 956.08 987.69 871.14 899.48 928.65 820.40 846.58 873.51 772.93 797.11 821.97 728.49 750.83 773.79 686.88 707.52 728.72 647.89 666.97 686.55 611.35 628.99 647.07 577.04 593.34 610.04 544.86 559.93 575.36 514.67 528.60 542.85 486.34 499.21 512.38 459.73 471.63 483.79 434.77 445.77 457.01 411.31 421.48 431.86 389.25 398.65 408.25 368.50 377.19 386.06 348.97 357.01 365.20 330.58 338.01 345.57 313.25 320.12 327.11 296.94 303.29 309.74 281.57 287.43 293.39 267.08 272.50 278.00 253.42 258.43 263.50 240.54 245.16 249.84 228.39 232.65 236.97 216.91 220.85 224.83 206.08 209.71 213.38 195.85 199.20 202.58 186.18 189.27 192.38 177.05 179.89 182.76 168.41 171.03 173.67 160.24 162.65 165.08 Tc [°C] 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Resistance value [kΩ] Min Typ Max 152.51 154.73 156.96 145.20 147.23 149.28 138.27 140.14 142.02 131.72 133.43 135.16 125.51 127.08 128.66 119.63 121.07 122.51 114.05 115.37 116.69 108.77 109.97 111.17 103.75 104.85 105.95 99.00 100.00 101.00 94.40 95.40 96.40 90.04 91.03 92.03 85.90 86.89 87.88 81.97 82.96 83.94 78.25 79.22 80.20 74.71 75.68 76.65 71.35 72.31 73.27 68.16 69.10 70.05 65.13 66.06 67.00 62.25 63.17 64.09 59.51 60.42 61.33 56.91 57.80 58.70 54.43 55.31 56.19 52.07 52.93 53.80 49.83 50.68 51.53 47.70 48.53 49.37 45.67 46.48 47.31 43.73 44.53 45.34 41.89 42.67 43.47 40.13 40.90 41.68 38.46 39.21 39.98 36.86 37.60 38.35 35.34 36.06 36.80 33.89 34.60 35.31 32.50 33.19 33.90 31.18 31.86 32.55 29.92 30.58 31.26 28.72 29.37 30.03 27.57 28.20 28.85 26.47 27.09 27.72 25.42 26.03 26.64 24.42 25.01 25.62 23.46 24.04 24.63 22.55 23.11 23.69 21.67 22.22 22.79 20.84 21.37 21.92 20.04 20.56 21.10 19.27 19.78 20.31 18.54 19.04 19.55 17.83 18.32 18.82 17.16 17.64 18.13 16.52 16.99 17.46 15.91 16.36 16.83 15.32 15.76 16.21 14.75 15.18 15.63 14.21 14.63 15.06 Tc [°C] 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 Table 3. NTC Thermistor Resistance Values www.onsemi.com 6 Resistance value [kΩ] Min Typ Max 13.69 14.10 14.52 13.19 13.59 14.00 12.71 13.10 13.51 12.25 12.64 13.03 11.81 12.19 12.57 11.39 11.76 12.13 10.99 11.34 11.71 10.60 10.95 11.30 10.23 10.57 10.91 9.87 10.20 10.54 9.53 9.85 10.18 9.20 9.51 9.83 8.88 9.18 9.50 8.57 8.87 9.18 8.28 8.57 8.87 8.00 8.28 8.58 7.73 8.01 8.29 7.47 7.74 8.02 7.22 7.48 7.75 6.98 7.23 7.50 6.75 7.00 7.26 6.52 6.77 7.02 6.31 6.55 6.80 6.10 6.34 6.58 5.90 6.13 6.37 5.71 5.93 6.17 5.53 5.74 5.97 5.35 5.56 5.78 5.18 5.38 5.60 5.01 5.21 5.42 4.85 5.05 5.26 4.70 4.89 5.09 4.55 4.74 4.94 4.41 4.59 4.79 4.27 4.45 4.64 4.14 4.32 4.50 4.01 4.18 4.36 3.89 4.06 4.23 3.77 3.93 4.10 3.66 3.82 3.98 3.55 3.70 3.86 3.44 3.59 3.75 3.33 3.48 3.64 3.24 3.38 3.53 3.14 3.28 3.43 3.05 3.19 3.33 2.96 3.09 3.23 2.87 3.00 3.14 2.79 2.92 3.05 2.71 2.83 2.96 2.63 2.75 2.88 2.55 2.67 2.80 2.48 2.60 2.72 2.41 2.52 2.64 AND9396/D 4. Protection functions This chapter describes the protection functions. Over‐current protection Short circuit protection Under voltage lockout (UVLO) protection Cross conduction prevention 4.1. Over‐current protection (OCP) The STK5MFU3C1A‐E module uses an external shunt resistor for the OCP functionality. As shown in Figure 9, the emitters of all three low‐side IGBTs are brought out a single module pin. The external OCP circuit consists of a shunt resistor and a RC filter network. Inverter part PFC part IPM IPM VP2 VP1 Driver PTRIP Shunt ITRIP PFCL U V W GND Shunt Driver GND OCP circuit N OCP circuit HVGND Figure 9. Over‐current Protection Circuit The OCP function is implemented by comparing the ITRIP and PTRIP input voltages with an internal reference voltage of 0.49V (typ) for inverter part and ‐0.31V (typ) for PFC part. If the absolute value of the voltage on either terminal exceeds the trip levels, an OCP fault is triggered. For single shunt applications, this voltage is the same as the voltage across the respective shunt resistors. Note: The current value of the OCP needs to be set by correctly sizing the external shunt resistor to be less than the module’s maximum current rating. When an OCP fault is detected, all internal gate drive signals for the IGBTs become inactive and the fault signal output is activated. The FAULT signal has an open drain output, so when there is a fault, the output is pulled low. A RC filter is used on the ITRIP and PTRIP inputs to prevent an erroneous OCP detection due to normal switching noise or recovery diode current. The time constant of the RC filter should be set to a value between 1.5μ to 2μs. In any case the time constant must be shorter than the IGBTs short current safe operating area (SCSOA). Please refer to data sheet for SCSOA. The resulting OCP level due to the filter time constant is shown in Figure 10. www.onsemi.com 7 AND9396/D Figure 10. Filter Time Constant For optimal performance all traces around the shunt resistor need to be kept as short as possible. Figure 11 shows the sequence of events in case of an OCP event. HIN/LIN/PFCIN Protection state Set Reset DRVH/DRVL/DRPFC Normal operation Over current Over current detection IGBT turn off Output Current Ic (A) Over current reference voltage Voltage of Shunt resistor RC circuit time constant Fault output Fault output Figure 11. Over‐current Protection Timing Diagram www.onsemi.com 8 AND9396/D 4.2. Under Voltage Lockout Protection The UVLO protection is designed to prevent unexpected operating behavior as described in Table 4. Both High‐side and Low‐side have undervoltage protection. The low‐side UVLO condition is indicated on the FAULT output. During the low‐side UVLO state the FAULT output is continuously driven low. A high‐side UVLO condition is not indicated on the FAULT output. VDD Voltage (typ. Value) Operation behavior < 12.5V As the voltage is lower than the UVLO threshold the control circuit is not fully turned on. A perfect functionality cannot be guaranteed. 12.5 V – 13.5 V IGBTs can work, however conduction and switching losses increase due to low voltage gate signal. 13.5 V – 16.5 V Recommended conditions 16.5 V – 20.0 V IGBTs can work. Switching speed is faster and saturation current higher, increasing short-circuit broken risk. > 20.0 V Control circuit is destroyed. Absolute max. rating is 20 V. Table 4. Module Operation according to VDD Voltage The sequence of events in case of a low‐side UVLO event (IGBTs turned off and active fault output) is shown in Figure 12. Figure 13 shows the same for a high‐side UVLO (IGBTs turned off and no fault output). LIN/PFCIN Protection state Reset Set Reset Control supply voltage VD Under voltage reset Under voltage trip Normal operation Output Current Ic (A) After the voltage level reaches UV reset, the circuits start to operate when next input is applied . IGBT turn off Fault output Fault output Figure 12. Low‐side UVLO Timing Diagram www.onsemi.com 9 AND9396/D HIN Reset Protection state Set Reset Control supply voltage VD Under voltage reset Under voltage trip Normal operation Output Current Ic (A) After the voltage level reaches UV reset, the circuits start to operate when next input is applied . IGBT turn off Fault output Keeping high level output ( No Fault output ) Figure 13. High‐side UVLO Timing Diagram 4.3. Cross conduction prevention The STK5MFU3C1A‐E module implements cross‐conduction prevention logic at the gate driver to avoid simultaneous drive of the low‐side and high‐side IGBTs as shown in Figure 14. Figure 14. Cross‐conduction Prevention www.onsemi.com 10 AND9396/D If both high‐side and low‐side drive inputs are active (HIGH) the logic prevents both gates from being driven as shown in Figure 15 below. HIN LIN Shoot-Through Prevention HVG Normal operation Normal operation LVG VDD Fault output Keeping high level output ( No Fault output ) Figure 15. Cross‐conduction Prevention Timing Diagram Even if cross‐conduction on the IGBTs due to incorrect external driving signals is prevented by the circuitry, the driving signals (HIN and LIN) need to include a “dead time”. This period where both inputs are inactive between either one becoming active is required due to the internal delays within the IGBTs. Figure 16 shows the delay from the HIN‐input via the internal high‐side gate driver to high‐side IGBT, the delay from the LIN‐input via the internal low‐side gate driver to low‐side IGBT and the resulting minimum dead time which is equal to the potential shoot through period: Figure 16. Shoot‐through Period www.onsemi.com 11 AND9396/D 5. PCB design and mounting guidelines This chapter provides guidelines for an optimized design and PCB layout as well as module mounting recommendations to appropriately handle and assemble the IPM. 5.1. Application (schematic) design + Noise filter & low impedance HF path 28 27 +15V GND Bridge diode RFCIN 22 LINW 21 LINV 20 LINU 19 HINW 18 HINV 17 HINU VBV V LINV VBU U Shunt R N Figure 17. Application Circuit www.onsemi.com 12 Vz < 18V U Prevention of overvoltage due to surge voltage HINU 10 HINV Power GND 9 LINU HINW Signal GND and Power GND should be connected at one point (not solid pattern). V Noise filter & low impedance HF path LINW 3.3kΩ Prevention of malfunction by influence of the external wiring 7 PFCIN VP2 ITRIP 6 W + FAULT/TH 33uF/25V PTRIP VP1 16 4 + 23 W HVGND 12 13 Shunt R 15 + 100Ω ITRIP 100nF/25V 25 24 Signal GND 3 + 20kΩ 26 PTRIP Low pass filter for prevention of malfunction due to noise Inductor 1 VDD VBW ITRIP 100pF PFCL 0.47-2.2uF/630V Snu bber Signal GND 100nF/25V Vz < 18V Prevention of overvoltage due to surge voltage 100uF/25V Figure 17 gives an overview of the external components and circuits used when designing with the STK5MFU3C1A‐E module. Limit surge voltage and overvoltage from ringing PTRIP AND9396/D 5.2. Pin by pin design and usage notes This section provides pin by pin PCB layout recommendations and usage notes. A complete list of module pins is given in Chapter 6. VP2 DC Power supply terminal for the inverter block. Voltage spikes could be caused by longer traces to this terminal due to the trace inductance, therefore this trace is recommended to be as short as possible. In addition a snubber capacitor should be connected as close as possible to VP2 terminal to stabilize the voltage and absorb voltage surges. N This is the common terminal for the emitters of low side IGBTs for the inverter and connects to the power GND through an external shunt resistor VP1 This is the PFC output and connects to VP2 pin as positive DC‐link power supply. HVGND This pin is connected with the emitter of the PFC boost IGBT. PFCL This is the connection for the switched end of the boost inductor. This pin is connected to the collector of the PFC IGBT and the anode of the PFC rectifier. The other end of the boost inductor is connected to the rectified AC mains input. U, V, W These are the output pins for connecting the 3‐phase motor. They share the same GND potential with each of the high‐side control power supplies. Therefore they are also used to connect the GND of the bootstrap capacitors. These bootstrap capacitors should be placed as close to the module as possible. This pin provides power to the low‐side gate drivers, the protection circuits and the VDD bootstrap circuits. The voltage between this terminal and GND is monitored by the UVLO circuit. GND This pin is the reference voltage for the pre‐driver. To avoid the malfunction by noise, it should be careful that the power circuit current does not flow through this terminal. VBU, VBV The VBx pins are internally connected to the positive supply of the high‐side drivers. VBW The supply needs to be floating and electrically isolated. The boot‐strap circuit shown in Figure 18 forms this power supply individually for every phase. Due to integrated boot resistor and diode (RB & DB) only an external boot capacitor (CB) is required. CB is charged when the following two conditions are met. ① Low‐side signal is input ② Motor terminal voltage is low level The capacitor is discharged while the high‐side driver is activated. Thus CB needs to be selected taking the maximum on time of the high‐side and the switching frequency into account. www.onsemi.com 13 AND9396/D DB CB Driver RB VDD Driver Figure 18. Bootstrap Circuit HINU, LINU HINV, LINV HINW, LINW PFCIN The voltages on the high‐side drivers are individually monitored by the under voltage protection circuit. If there is a UVLO fault on any given phase, the output on that phase is disabled. Typically a CB value of less or equal 47uF (±20%) is used. If the CB value needs to be higher, an external resistor (20Ω or less) should be used in series with the capacitor to avoid high currents which can cause malfunction of the IPM. These pins are the control inputs for the power stages. The inputs on HINU/HINV/HINW control the high‐side transistors of U/V/W, the inputs on LINU/LINV/LINW control the low‐side transistors of U/V/W, and the input on PFCIN controls the transistors of PFC respectively. The input logic is active HIGH. An external microcontroller can directly drive these inputs without need for isolation. Simultaneous activation of both low‐side and high‐side is prevented internally to avoid shoot‐through at the power stage. However, due to IGBT switching delays the control signals must include a dead‐time. The equivalent input stage circuit is shown in Figure 19. IN 33k GND Figure 19. Internal Input Circuit www.onsemi.com 14 AND9396/D For fail safe operation the control inputs are internally tied to GND via a 33kΩ (typ) resistor. An additional external low‐ohmic pull‐down resistor with a value of 2.2kΩ‐3.3kΩ is recommended to prevent erroneous switching caused by noise induced in the wiring. The output might not respond when the width of the input pulse is less than 1µs (both ON and OFF). This pin is an active low fault output (open‐drain). It is used to indicate an internal fault condition of the module. The structure is shown in Figure 20. The internal sink current IoSD during an active fault is nominal 2mA @ 0.1V. Depending on the interface supply voltage the external pull‐up resistor (RP) needs to be selected as shown below. For the commonly used supplies : Pull up voltage = 15V ‐> RP >= 20kΩ Pull up voltage = 5V ‐> RP>= 6.8kΩ FAULT/TH VDD FAULT/TH Thermistor RP GND Figure 20. FAULT/TH Connection For a detailed description of the fault operation refer to Chapter 4. Note: The Fault signal does not permanently latch. After the protection event ended and the fault clear time(min. 1ms) passed, the module's operation is automatically re‐started. Therefore the input needs to be driven low externally as soon as a fault is detected. Also, an internal thermistor to sense the substrate temperature is connected between this pin and GND. By connecting an external pull‐up resistor and measuring the midpoint voltage, the module temperature can be monitored. Please refer to heading 3.2 for details of the thermistor. Note: This is the only means to monitor the substrate temperature indirectly. ITRIP PTRIP These pins are used to enable an OCP function. The ITRIP is for inverter part, the PTRIP is for PFC part. When the voltage of these pins exceeds a reference voltage, the OCP function operates. For details of the OCP operation refer to Chapter 4. www.onsemi.com 15 AND9396/D 5.3. Heat sink mounting and torque If a heat sink is used, insufficiently secure or inappropriate mounting can lead to a failure of the heat sink to dissipate heat adequately. The following general points should be observed when mounting IPM on a heat sink: 1. Verify the following points related to the heat sink: There must be no burrs on aluminum or copper heat sinks. Screw holes must be countersunk. There must be no unevenness in the heat sink surface that contacts IPM. There must be no contamination on the heat sink surface that contacts IPM. 2. Highly thermal conductive silicone grease needs to be applied to the whole back (aluminum substrate side) uniformly, and mount IPM on a heat sink. If the device is removed, grease must be applied again. 3. For a good contact between the IPM and the heat sink, the mounting screws should be tightened gradually and sequentially while a left/right balance in pressure is maintained. Either a bind head screw or a truss head screw is recommended. Please do not use tapping screw. We recommend using a flat washer in order to prevent slack. The standard heat sink mounting condition of the STK5MFU3C1A‐E is as follows. Item Recommended Condition Pitch 70.0±0.1mm (Please refer to Package Outline Diagram) diameter : M4 Screw Bind machine screw, Truss machine screw, Pan machine screw Plane washer Washer The size is D:9mm, d:4.3mm and t:0.8mm JIS B 1256 Material: Aluminum or Copper Warpage (the surface that contacts IPM ) : 50 to 100 μm Heat sink Screw holes must be countersunk. No contamination on the heat sink surface that contacts IPM. Temporary tightening : 20 to 30 % of final tightening on first screw Temporary tightening : 20 to 30 % of final tightening on second screw Torque Final tightening : 0.79 to 1.17Nm on first screw Final tightening : 0.79 to 1.17Nm on second screw Silicone grease. Thickness : 100 to 200 μm Grease Uniformly apply silicon grease to whole back. Thermal foils are only recommended after careful evaluation. Thickness, stiffness and compressibility parameters have a strong influence on performance. Table 5. Heat Sink Mounting www.onsemi.com 16 AND9396/D Figure 21. Mount IPM on a heat sink Figure 22. Size of washer Figure 23. Uniform Application of Grease Recommended Steps to mount an IPM on a heat sink 1st: Temporarily tighten maintaining a left/right balance. 2nd : Finally tighten maintaining a left/right balance. 5.4. Mounting and PCB considerations In designs in which the PCB and the heat sink are mounted to the chassis independently, use a mechanical design which avoids a gap between IPM and the heat sink, or which avoids stress to the lead frame of IPM by an assembly that slipping IPM is forcibly fixed to the heat sink with a screw. Figure 24. Fix to Heat Sink Maintain a separation distance of at least 1.5 mm between the IPM case and the PCB. In particular, avoid mounting techniques in which the IPM substrate or case directly contacts the PCB. www.onsemi.com 17 AND9396/D Do not mount IPM with a tilted condition for PCB. This can result in stress being applied to the lead frame and IPM substrate could short out tracks on the PCB. If stress is given by compulsory correction of a lead frame after the mounting, a lead frame may drop out. Since the use of sockets to mount IPM can result in poor contact with IPM leads, we strongly recommend making direct connections to PCB. Mounting on a PCB 1. Align the lead frame with the holes in the PCB and do not use excessive force when inserting the pins into the PCB. To avoid bending the lead frames, do not try to force pins into the PCB unreasonably. 2. Do not insert IPM into PCB with an incorrect orientation, i.e. be sure to prevent reverse insertion. IPMs may be destroyed or suffer a reduction in their operating lifetime by this mistake. 3. Do not bend the lead frame. 5.5. Cleaning IPM has a structure that is unable to withstand cleaning. Do not clean independent IPM or PCBs on which an IPM is mounted. www.onsemi.com 18 AND9396/D 6. Package Outline The package of STK5MFU3C1A‐E is SIP3B. (Single‐inline‐package) 6.1. Package outline and dimension SIP23 70x31.1 CASE 127DG ISSUE O Figure 25. Package Outline www.onsemi.com 19 AND9396/D 6.2. Pin Out Description Pin 1 3 4 6 7 9 10 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name PFCL VBW Description PFC Inductor Connection to IGBT and Rectifier node High Side Floating Supply voltage for W phase W phase output W Internally connected to W phase high side driver ground VBV High Side Floating Supply voltage for V phase V phase output V Internally connected to V phase high side driver ground VBU High Side Floating Supply voltage for U phase U phase output U Internally connected to U phase high side driver ground VP1 Positive PFC Output Voltage VP2 Positive Bus Input Voltage HVGND Negative PFC Output Voltage N Low Side Emitter Connection HINU Logic Input High Side Gate Driver ‐ Phase U HINV Logic Input High Side Gate Driver ‐ Phase V HINW Logic Input High Side Gate Driver ‐ Phase W LINU Logic Input Low Side Gate Driver ‐ Phase U LINV Logic Input Low Side Gate Driver ‐ Phase V LINW Logic Input Low Side Gate Driver ‐ Phase W PFCIN Logic Input PFC Gate Driver FAULT/TH Fault Output / Thermistor PTRIP Current Protection pin for PFC ITRIP Current Protection pin for Inverter VDD +15V Main Power Supply GND Negative Main Power Supply Note : Pins 2, 5, 8, 11, 14 are not present. www.onsemi.com 20 AND9396/D 7. Evaluation Board The evaluation board consists of the minimum required components such as snubber capacitor and bootstrap circuit elements of STK5MFU3xx series. ACIN1 IPM VDD C11 VSS + 220uF C10 0.1uF 27. VDD R23 3.3kΩ R17 R18 R19 R20 R21 R22 C14 100pF C15 C16 C17 C18 C19 C20 ACIN2 C7 R9 4. W 20kΩ 26. ITRIP 25. PTRIP FAULT/TH 24. FAULT/TH Connector R10 PFCIN R16 HIN1 R15 HIN2 R14 HIN3 R13 LIN1 R12 LIN2 R11 LIN3 + W 22uF 6. VBV C5 + V 7. V 9. VBU C9 R8 C4 0.1uF C8 PFCTRIP Bridge diode 1. PFCL 3. VBW C12 ITRIP + 28. GND VEXT C13 PC C6 + U 10. U R7 0Ω 12. VP1 23. PFCIN P 13. VP2 17. HINU C3 15. HVGND 18. HINV 2.2uF C1 N + + 470uF 470uF R5 R6 15mΩ Shunt R (PFC) 19. HINW 20. LINU 21. LINV R4 C2 R1 16. N R2 R3 22. LINW 100Ω 50mΩ Shunt R (INV) N Test pin Faston terminal (Tab) Figure 26. Evaluation Board Schematic Surface Back side Length : 152mm Rigid double‐sided substrate (Material : FR‐4) Side : 165mm Both sides resist coating Thickness : 1.6mm Copper foil thickness : 70um Figure 27. PCB Layout (TOP view) www.onsemi.com 21 AND9396/D Top view Bottom view Figure 28. Top and Bottom Views of Evaluation Board www.onsemi.com 22 AND9396/D ACIN2 ACIN1 C1 C2 - C3 IC1 N P R1 DB1 R2 R3 + C4 C5 C6 C7 C8 C9 R7 CN1 N C12 VSS PC VDD VEXT C11 C13 ITRIP R9 PFCTRIP FAULT/TH W R8 R4 R5 R6 R10 R11 R12 R13 R14 R15 R16 LIN3 LIN1 HIN2 V HIN1 HIN3 U LIN2 C14 C15 C16 C17 C18 C19 * IC1, DB1, R10‐23, C10, C14‐20 are arranged on backside. C20 PFCIN R17 R18 R19 R20 R21 R22 R23 Figure 29. Transparent View from Top Side U, V, W : 3 phase inverter output VDD : Control power supply VSS : Signal GND PC : Rectified AC Voltage input HINx, LINx, PFCIN : Control signal input ITRIP : Over current protection for Inverter PFCTRIP : Over current protection for PFC VEXT : FAULT/TH pull‐up Apply the logic I/O voltage FAULT/TH : Fault output, Thermistor ACIN1, ACIN2 : Bridge diode AC voltage input +, ‐ : Bridge diode output R1‐6 : Shunt resistor, 3 parallel connection R7 (, C12) : RC filter for ITRIP R8 (, C13) : RC filter for PFCTRIP R10‐16, C14‐20 : Low pass filter for signal input Prevention malfunction by noise R17‐23 : Pull‐down to VSS for signal input Prevention malfunction by external wiring C4‐6 : Boot strap capacitor Blue : Arranged on surface Purple : Arranged on back side * C10 is arranged on back position of C12 and C13. www.onsemi.com 23 AND9396/D AC power supply ACIN2 ACIN1 C1 C2 - C3 IC1 N P R1 DB1 R2 R3 Inductor + C4 C5 C6 C7 C8 C9 R7 CN1 N C12 VSS PC VDD VEXT C11 C13 ITRIP R9 PFCTRIP FAULT/TH W R8 R4 R5 R6 R10 R11 R12 R13 R14 R15 R16 LIN3 LIN1 HIN2 V Motor HIN1 HIN3 U LIN2 Logic R17 R18 R19 R20 R21 R22 R23 C14 C15 C16 C17 C18 C19 C20 PFCIN DC 15V Figure 30. Connection Example Operating procedure Step1: Connect IPM, the three power supplies, logic parts, inductor and the motor to the evaluation board, and confirm that each power supply is OFF at this time. Step2: Apply DC15V to VDD and the logic I/O voltage to VEXT. Step3: Perform a voltage setup according to specifications, and apply AC power supply between ACIN1 and ACIN2. Step4: The IPM will start when signals are applied. The low‐side inputs must be switched on first to charge up the bootstrap capacitors. Note : When turning off the power supply part and the logic part, please carry out in the reverse order to above steps. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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