LV8760T/LV8761V Application Note

LV8760T/LV8761V
Bi-CMOS LSI
Forward/Reverse H-bridge Driver
Application Note
http://onsemi.com
Overview
The LV8760T /LV8761V are an H-bridge driver that can control four operation modes (forward, reverse,
brake, and standby) of a motor. The low on-resistance, zero standby current, highly efficient IC is optimal for
use in driving brushed DC motors for office equipment.
Function
 Forward/reverse H-bridge motor driver: 1 channel
 Built-in current limiter circuit
 Built-in thermal protection circuit
 Built-in short-circuit protection function
 Unusual condition warning output pin (LV8761V only)
 Short-circuit protection circuit selectable from latch-type or auto reset-type (LV8761V only)
Typical Applications
 MFP (Multi Function Printer)
 PPC (Plain Paper Copier)
 LBP (Laser Beam Printer)
 Photo Printer
 Scanner
 Industrial
 Cash Machine
 Entertainment
Pin Assignment
20 VCC
OUTB 2
RNF 5
VM 6
VM 7
OUTA 8
OUTA 9
PS 10
17 IN2
16 IN1
15 REG5
34 VREF
NC 4
33 NC
NC 5
32 NC
OUTB 6
31 NC
OUTB 7
30 IN2
RNF 8
29 IN1
VM 10
18 VREF
LV8760T
RNF 4
35 SCP
NC 3
RNF 9
19 SCP
OUTB 3
36 EMM
Packages are not to scale.
LV8761V
PGND 1
VCC 1
PGND 2
28 NC
27 REG5
VM 11
26 CP1
OUTA 12
25 CP2
OUTA 13
24 NC
NC 14
23 GND
14 CP1
NC 15
22 NC
13 CP2
NC 16
21 VG
PS 17
20 NC
12 VG
11 GND
GND 18
19 EMOT
Top view
TSSOP20J (225mil)
Semiconductor Components Industries, LLC, 2013
December, 2013
SSOP36J (275mil)
1/36
LV8760T/LV8761V Application Note
Package Dimensions
Unit: mm (typ)
TOP VIEW
BOTTOM VIEW
6.5
20
0.5
6.4
4.4
11
10
1
0.65
Exposed Die-Pad
0.15
0.22
(1.0)
0.08
SIDE VIEW
1.2max
(0.33)
SANYO : TSSOP20J(225mil)
SIDE VIEW
TOP VIEW
BOTTOM VIEW
15.0
36
(3.5)
0.5
5.6
7.6
(4.0)
1 2
0.3
0.8
0.2
0.1
(1.5)
SIDE VIEW
1.7 MAX
(0.7)
SANYO : SSOP36J(275mil)
Caution: The package dimension is a reference value, which is not a guaranteed value.
Recommended Soldering Footprint
(Unit:mm)
Reference symbol
TSSOP20J
SSOP36J
(225mil)
(275mil)
eE
5.80
7.00
e
0.65
0.8
b3
0.32
0.42
l1
1.00
1.00
X
(4.3)
(4.0
Y
(2.8)
(3.5)
2/36
GND
VCC
EMOT
(LV8761V only)
PS
REG5
VG
SCP
Short-circuit
protection circuit
Oscillation
circuit
LVS
TSD
Reference
voltage
circuit
Charge pump
CP2
EMM
(LV8761V only)
CP1
VM
OUTA
OUTB
IN1
IN2
Output control
logic
Ｍ
Current
limiter
circuit
RNF
VREF
ＰGND
LV8760T/LV8761V Application Note
Block Diagram
Output preamplifier stage
Output preamplifier stage
3/36
LV8760T/LV8761V Application Note
Selection Guide
Part Number
LV8760T
LV8761V
Short-circuit protection
Latch-type
Latch-type/Auto reset-type, Warning output
Package
TSSOP20J (225mil) with Exposed Die-Pad
SSOP36J (275mil) with Exposed Die-Pad
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Supply voltage
Symbol
Unit
V
VCC max
6
V
IO peak
Output continuous current
IO max
Allowable power dissipation
Ratings
38
Output peak current
Logic input voltage
Conditions
VM max
tw  20ms, duty 5%
VIN
Pd max
4
A
3
A
-0.3 to VCC+0.3
V
LV8760T *
3.3
W
LV8761V *
3.15
W
Operating temperature
Topr
-20 to +85
C
Storage temperature
Tstg
-55 to +150
C
* Specified circuit board: 90mm90mm1.6mm, glass epoxy 2-layer board (2S0P), with backside mounting.
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage
under high temperature, high current, high voltage, or drastic temperature change, the reliability of the IC may
be degraded. Please contact us for the further details.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Recommended Operating Conditions at Ta  25C
Parameter
Supply voltage range
Symbol
Conditions
Ratings
min
typ
Unit
max
VM
9
35
3
5.5
V
VREF input voltage
VCC
VREF
V
0
V
Logic input voltage
VIN
0
VCC-1.8
VCC
V
Electrical Characteristics at Ta = 25°C, VM = 24V, VCC = 5V, VREF = 1.5V
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
General
A
Standby mode current drain 1
IMst
PS = “L”
1
Standby mode current drain 2
ICCst
PS = “L”
1
A
1.3
mA
mA
Operating mode current drain 1
IM
PS = “H”, IN1 = “H”, with no load
Operating mode current drain 2
ICC
VREG
PS = “H”, IN1 = “H”, with no load
VREG output voltage
VCC low-voltage cutoff voltage
Low-voltage hysteresis voltage
Thermal shutdown temperature
1
3
4
4.75
5
5.25
VthVCC
2.5
2.7
2.9
V
VthHIS
120
150
180
mV
155
170
185
C
IO = -1mA
V
TSD
Design guarantee *
TSD
Design guarantee *
Ron1
Ron2
IO = 3A, sink side
IO = -3A, source side
IOleak
VO = 35V
Rising time
tr
10% to 90%
200
500
ns
Falling time
tf
90% to 10%
200
500
ns
Thermal hysteresis width
C
40
Output block
Output on resistance
Output leakage current
Input output delay time

0.2
0.25
0.32
0.40

50
A
tpLH
IN1 or IN2 to OUTA or OUTB (L  H)
550
700
ns
tpHL
IN1 or IN2 to OUTA or OUTB (H  L)
550
700
ns
28.7
29.8
V
250
500
s
165
kHz
Charge pump block
Step-up voltage
VGH
VM = 24V
Rising time
tONG
VG = 0.1F
Oscillation frequency
Fcp
28.0
115
140
Continued on next page.
4/36
LV8760T/LV8761V Application Note
Continued from preceding page
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
Control system input block
Logic pin input current 1
Logic pin input current 2
IINL
VIN = 0.8V adaptive pin : PS
IINH
IINL
IINH
8
VIN = 5V adaptive pin : PS
56
80
104
A
VIN = 0.8V adaptive pin : IN1, IN2
5.6
8
10.4
A
VIN = 5V adaptive pin : IN1, IN2
35
50
65
A
2.0
Logic pin input H-level voltage
VINH
adaptive pin : PS, IN1, IN2
Logic pin input L-level voltage
VINL
adaptive pin : PS, IN1, IN2
10.4
A
5.6
V
0.8
V
Current limiter block
VREF input current
IREF
Current limit comparator
Vthlim
A
-0.5
VREF = 1.5V
0.285
0.3
0.315
V
A
threshold voltage
Short-circuit protection block
SCP pin charge current
Iscp
Comparator threshold voltage
Vthscp
EMO output saturation voltage
Vemo
SCP = 0V
Io = 500μA
3.5
5
6.5
0.8
1
1.2
V
0.3
0.4
V
(LV8761V only)
* Design guarantee value and no measurement is made.
5/36
1
0.8
0.6
0.4
0.2
0
‐0.2
‐0.4
‐0.6
‐0.8
‐1
Iccst (μA)
IMst (μA)
LV8760T/LV8761V Application Note
5
10
15
20
25
30
1
0.8
0.6
0.4
0.2
0
‐0.2
‐0.4
‐0.6
‐0.8
‐1
35
3
VM(V)
Figure 1 Standby mode current drain1
vs VM Voltage
1.4
4
1.2
3.5
Icc (mA)
IM (mA)
4.5
5
5.5
3
0.8
0.6
0.4
2.5
2
1.5
1
0.2
0.5
0
0
5
10
15
20
25
30
3
35
IREF (μA)
5.5
5.4
5.3
5.2
5.1
5
4.9
4.8
4.7
4.6
4.5
5
10
15
20
25
30
3.5
4
4.5
5
5.5
Vcc(V)
Figure 4 Operating mode current drain2
vs Vcc Voltage
VM(V)
Figure 3 Operating mode current drain1
vs VM Voltage
VREG (V)
4
Vcc(V)
Figure 2 Standby mode current drain2
vs Vcc Voltage
1
0
‐0.01
‐0.02
‐0.03
‐0.04
‐0.05
‐0.06
‐0.07
‐0.08
‐0.09
‐0.1
3
35
3.5
4
4.5
5
5.5
4
5
Vcc(V)
Figure 6 VREF input current
vs Vcc Voltage
VM(V)
Figure 5 VREG output voltage
vs VM Voltage
90
80
70
60
50
40
30
20
10
0
60
50
40
IIN (μA)
IIN (μA)
3.5
30
20
10
0
0
1
2
3
VIN(V)
Figure 7 Logic pin input current1
vs VIN Voltage
4
5
0
1
2
3
VIN(V)
Figure 8 Logic pin input current2
vs VIN Voltage
6/36
LV8760T/LV8761V Application Note
0.4
0.6
0.5
0.3
Ron (Ω)
Ron (Ω)
0.4
0.2
0.1
Ron2
0
1
2
3
0.2
Ron2
0.1
Ron1
0
0.3
Ron1
0
4
‐20
0
Iout (A)
40
60
80
100
Temperature (℃)
Figure 9 Output on Resistance
vs Output Current
Figure 10 Output on Resistance（Io=3A)
vs Temperature
3.00 0.18
2.80 0.17
0.16
2.60 VthHIS (V)
VthVcc (V)
20
2.40 2.20 2.00 0.15
0.14
0.13
0.12
‐20
0
20
40
60
80
100
‐20
0
Temperature (℃)
20
40
60
80
100
Temperature (℃)
Figure 11 Vcc low-voltage cutoff voltage
vs Temperature
Figure 12 Low-voltage hysteresis voltage
vs Temperature
6.5
1.20 6
1.10 Vthscp (V)
Iscp (μA)
5.5
5
4.5
1.00 0.90 4
0.80 3.5
3
3.5
4
4.5
5
5.5
‐20
0
20
40
60
80
100
Temperature (℃)
Vcc(V)
Figure 13 SCP pin charge current
vs Vcc Voltage
Figure 14 SCP Comparator threshold
voltage vs Temperature
0.7
0.6
Vemo (V)
0.5
0.4
0.3
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1
Io(mA)
Figure 15 EMO output saturation voltage
vs Output current
7/36
LV8760T/LV8761V Application Note
Pin Functions
Pin No.
Pin
LV8760T LV8761V
Name
Pin Function
16
29
IN1
Output control signal input pin 1.
17
30
IN2
Output control signal input pin 2
－
36
EMM
Short-circuit protection circuit mode
Equivalent Circuit
VCC
switching pin.
10kΩ
100kΩ
GND
10
17
PS
Power save signal input pin.
VCC
50kΩ
10kΩ
10kΩ
50kΩ
GND
18
34
VREF
Reference voltage input pin for output
VCC
current limit setting.
500Ω
GND
19
35
SCP
Short-circuit protection circuit,
detection time setting capacitor
VCC
connection pin.
500Ω
GND
20
1
VCC
Power supply connection pin for
control block.
Continued on next page.
8/36
LV8760T/LV8761V Application Note
Continued from preceding page.
Pin No.
Pin
LV8760T LV8761V
Name
Pin Function
6, 7
10,11
VM
Motor power-supply connection pin.
8, 9
12,13
OUTA
OUTA output pin.
4, 5
8,9
RNF
Current sense resistor connection
2, 3
6,7
OUTB
OUTB output pin.
1
2
PGND
Power ground.
14
26
CP1
Charge pump capacitor connection
13
25
CP2
12
21
VG
Equivalent Circuit
pin.
pin.
Charge pump capacitor connection
pin.
Charge pump capacitor connection
pin.
15
27
REG5
Internal reference voltage output pin.
VM
74kΩ
2kΩ
25kΩ
GND
－
19
EMOT
Unusual condition warning output pin.
VCC
500Ω
GND
11
18,23
GND
Ground.
9/36
LV8760T/LV8761V Application Note
DC Motor Driver Operation
1. The recommended order of power supply
It is recommendable that the power supplies are turned on in the following order.
VCC power supply order → VM power supply order → PS pin = High→IN1/IN2 pin control
It becomes the above-mentioned opposite for power supply OFF.
VCC is the controller power supply and VM is the motor power supply. Output FET is controllable safely by
powering VCC first to define the state of output FET before powering VM.
If VM is powered first before VCC, output FET cannot be controlled and the operation becomes unstable.
However, the above-mentioned order is presented only as a recommendation, and noncompliance is not going
to be the cause of over-current or IC destruction.
Also, there are some other cautions to be addressed for the order of power supply.
(1) When VM = 0V and VCC is powered and PS = IN1 (or IN2) = H, even if the control signal is applied to drive
output FET, since the output pin is 0V, the short protector circuit detects error state and the output is latched-off.
Therefore, make sure to power VCC/VM first and turn on control input (PS, IN1, IN2), then turn on the output.
(2) When the PS pin is set High, the charge pump circuit operates and the VG pin voltage is boosted from the
VM voltage to the VM + REG5 voltage.
The charge pump output (VG) is used to drive gate of the upper FET. If the output is turned on while VG is not
sufficiently boosted, the performance of the upper FET decreases, which lowers output voltage. As a result,
short protector circuit may operate. Hence, make sure to secure a wait time equivalent to “tONG” or longer
after PS turns High.
The output latch-off caused by over current can be cancelled by applying PS signal or re-powering VCC.
Figure 16. The turning on recommendation order timing chart
10/36
LV8760T/LV8761V Application Note
2. Output control logic table
Control Input
PS
IN1
Output
IN2
OUTA
Mode
OUTB
L
*
*
OFF
OFF
Standby
H
L
L
OFF
OFF
Output OFF
H
H
L
H
L
CW (Forward)
H
L
H
L
H
CCW (Reverse)
H
H
H
L
L
Brake
Output waveform example (No load)
Figure 17. Forward ↔ Output off switching
No load, PS=High, IN2=Low
Vcc=5V, VM=24V, VREF=1.5V
0.5ms/div
IN1
5V/div
OUTA
10V/div
OUTB
10V/div
0.5μs/div
0.5μs/div
IN1
5V/div
Off
High
OUTA
10V/div
IN1
5V/div
High
tpLH
Off
Low
OUTA
10V/div
tpHL
Low
Low
OUTB
10V/div
Standby
Off
Forward
Forward
High
Off
OUTB
10V/div
Standby
Synchronous Rectification
When changing the motor rotation from Forward mode to Standby mode, IC does not turn off at once. The
counterpart FET is turned on first, and then the current is attenuated rapidly. (Synchronous Rectification)
Afterwards, when the zero current level is detected, the load current is prevented from being reversed by
turning off the synchronous rectifier.
Synchronous rectifier control reduces power dissipation during PWM operation.
11/36
LV8760T/LV8761V Application Note
Figure 18. Reverse ↔ Brake switching
No load, PS=High, IN2=High
Vcc=5V, VM=24V, VREF=1.5V
0.5ms/div
IN1
5V/div
OUTA
10V/div
OUTB
10V/div
0.5μs/div
0.5μs/div
IN1
5V/div
OUTA
10V/div
Low
High
Low
Brake
OUTA
10V/div
Low
Low
OUTB
10V/div
tpHL
Reverse
IN1
5V/div
High
OUTB
10V/div
tpLH
Brake
Reverse
12/36
LV8760T/LV8761V Application Note
Output waveform example (DC motor load)
Figure 19. Forward ↔ Output Off switching
DC_motor load, PS=High, IN2=Low
Vcc=VREF=5V, VM=24V, RNF=GND
20ms/div
IN1
5V/div
High
OUTA
10V/div
OUTB
10V/div
Low
Start current
Off
Motorcurrent
0.5A/div
Forward
20ms/div
10μs/div
EMF
Off
IN1
5V/div
IN1
5V/div
OUTA
10V/div
OUTA
10V/div
OUTB
10V/div
Off
High
Off
Low
Off
Synchronous Rectification
ZOOM
Motorcurrent
0.5A/div
Forward
Off
OUTB
10V/div
Motorcurrent
0.5A/div
Forward
Off
DC motor starts operation, high current flows. However, as the motor rotation continues, the current is reduced
due to the back electromotive force generated in the motor.
Given that the motor supply voltage is Vm, the back electromotive force of the motor is EMF, and the coil
resistance is Ra, the motor current is obtained as follows:
Im = (Vm-EMF)/Ra
13/36
LV8760T/LV8761V Application Note
Figure 20. Forward ↔ Brake switching
DC_motor load, PS=High, IN1=High
Vcc=VREF=5V, VM=24V, RNF=GND
20ms/div
20ms/div
IN2
5V/div
Low
OUTA
10V/div
High
OUTB
10V/div
Low
Start current
IN2
5V/div
High
OUTA
10V/div
Low
OUTB
10V/div
Low
Motorcurrent
0.5A/div
Motorcurrent
0.5A/div
Ibk
Brake
Forward
Forward
Brake
You can put a brake on the DC motor by turning on both of the lower FETs of the H-Bridge while the motor
is under rotation.
Here, the brake current Ibk = EMF/Ra flows against, which is generated from the EMF occurred during motor
rotation.
Figure 21. Forward ↔ Reverse switching
IN1 and IN2 are input by the reversed phase
DC_motor load, PS=High
Vcc=VREF=5V, VM=24V, RNF=GND
IN1
5V/div
High
High
Low
Low
OUTA
10V/div
OUTB
10V/div
IN1
5V/div
High
High
Low
Low
Motorcurrent
0.5A/div
Reverse
Forward
OUTA
10V/div
OUTB
10V/div
Motorcurrent
0.5A/div
Forward
Reverse
When the counterpart FET is turned on while the DC motor is under rotation, rotation will change rapidly
because the rotation direction is switched. Since Vm voltage is powered reversely in addition to the EMF,
reverse current Irev = (EMF+Vm)/Ra flows against the opposite direction.
Since reverse current Irev is about double the startup current, the current may exceed the ratings depends on
applied loads. Hence, it is recommended to set brake mode when you switch the rotational direction of motors.
14/36
LV8760T/LV8761V Application Note
3. PWM (Pulse Width Modulation) control
LV8760T/LV8761V can perform H-Bridge direct PWM control to IN1, and IN2 by inputting PWM signal.
The maximum frequency of PWM signal is 200 kHz. However, dead zone is generated when On-Duty is
around 0%. Make sure to select optimum PWM frequency according to the target control range.
Figure22.Input‐OutputCharacteristicsofH‐Bridge(Referencedata)
Forward/Reverse↔Brake
Vcc=5V,VM=24V,VREF=1.5V
Output voltage(V)
25
-100
20
15
10
-50
5
0
‐5 0
‐10
‐15
‐20
Measurementconnectiondiagram
VM
（24V)
50
100kHz
20kHz
‐25
PWM On-duty(%)
Reverse
100
200kHz
OUTB
OUTA
240Ω
Forward
1KΩ
1KΩ
10
V
8
2.2µF
Output voltage(V)
6
-20
2.2µF
4
2
0
-10
‐2 0
‐4
‐6
‐8
10
20
200kHz
100kHz
20kHz
‐10
PWM On-duty(%)
15/36
LV8760T/LV8761V Application Note
4. Current Limit control
Limit current
Output current
OUTA
OUTB
toff
CHARGE
SLOW
Figure 23. Current limit control timing chart
Figure 24. Output transistor operation sequence
Output FET control function
IN1 = High, IN2 = Low (Forward)
Output control
CHARGE
input
U1
ON
U2
OFF
L1
OFF
L2
ON
IN1 = Low, IN2 = High (Reverse)
Output control
CHARGE
input
U1
OFF
U2
ON
L1
ON
L2
OFF
BRAKE
OFF
OFF
ON
ON
BRAKE
OFF
OFF
ON
ON
16/36
LV8760T/LV8761V Application Note
5. Setting the current limit value
Current limit control is feasible by connecting current sensing resistor between RNF and GND and powering
reference voltage to VREF.
The current limit value is determined by the following formula:
Ilimit [A] = (VREF [V] /5) /RNF [])
Given that VREF = 1.5V, RNF = 0.22, the current limit is obtained as follows:
Ilimit = 1.5V/5/0.22 = 1.36A
When output current reaches to the current limit setting value, current control is performed by chopping output
FET as Figure 24 shows: 1→2→3→2→1→…
After the chopping drive, when the mode switches from CHARGE to Brake mode, the upper and the lower FET
are turned off to prevent penetration current. The off period is set between 200 and 300nsec. During off period,
the current is regenerated through parasitic diode generated between drain and source of the FET because the
lower FET (L1 side) is off.
6. Setting the Braking time
Braking operation time can be set by connecting a capacitor between SCP and GND pins.
The value of the capacitor can be determined by the following formula:
Tscp  C  Vthscp / Iscp [sec]
Vthscp: Comparator threshold voltage (1V typical)
Iscp: SCP charge current (5A typical)
Timer latch-up: Tscp
When a capacitor with a capacitance of 100pF is connected across the SCP and GND pins, for example,
Tscp is calculated as follows:
Tscp = 100pF  1V/5A = 20s
This setting is the same as the following time setting required to turn off the outputs when an output
short-circuit occurs as explained in the section entitled "Output Short-circuit Protection Function."
7. Blanking time
If, when exercising PWM current control over the motor current, the mode is switched from decay to charge,
the recovery current of the parasitic diode may flow to the current sensing resistance, causing noise to be
carried on the current sensing resistance pin, and this may result in false over current detection. To prevent
this false detection, a blanking time is provided to prevent the noise occurring during mode switching from
being received. During this time, the mode is not switched from charge to decay even if noise is carried on
the current sensing resistance pin.
The blanking time, tBLANK (μs),is approximately
tBLANK2μs
10μs/div
5μs/div
Coilcurrent
0.5A/div
Blankingtime
Chargemode
OUTA
10V/div
OUTA
10V/div
OUTB
10V/div
OUTB
10V/div
SCP
1V/div
SCP
1V/div
Brakemode
Figure25.Currentlimitoperation
Vcc=5V,VM=24V,VREF=1.5V
RNF=0.22Ω,SCP=105pF
Figure26.Blankingtime Vcc=5V,VM=24V,VREF=1.5V
RNF=0.4V,SCP=105pF
17/36
LV8760T/LV8761V Application Note
Output short-circuit protection function
The LV8760T/LV8761V incorporates an output short-circuit protection circuit that turns off the output to
prevent the IC from fatal damage when the output is short-circuited due to short-to-power or short-to-ground
fault.
1. Short-circuit state detection operation
VM-Output pin short
High current flows as follows:
VM power supply→ lower FET→ RNF resistor.
When the voltage of RNF becomes high, the
mode switches from Charge to Brake. However
since the lower FET is on, comparison is
performed to the Vds of the lower FET and
short detection reference voltage. As a result,
protector circuit operates and the output is
turned off.
Output pin-GND short
High current flows as follows:
The upper FET → GND
After the Vds of the upper FET and short
detection reference voltage is compared.
As a result, protector circuit operates and the
output is turned off.
Output pin-Output pin short
High current flows as follows:
VM power supply→ the upper FET→ the lower
FET→RNF resistor.
When the voltage of RNF becomes high, the
mode switches from Charge to Brake.
Therefore, the flow of the current is stopped
and short state is not detected. After the Brake
mode is over, the upper FET turns on again and
high current flows, but brake is set immediately.
Since such operation is repeated, short state is
not detected.
Without use of current limit function
(RNF-GND short), since the mode is not
switched to brake with high current, short state
is detected and the output is turned off by
protector circuit.
18/36
LV8760T/LV8761V Application Note
2. Output short-circuit protection detect current
Short protector operates when abnormal current flows into the output transistor.
However, please note that there is a temperature property in the detection current.
Ta = 25°C (typ), RNF-GND short (Reference value)
Output FET
LV8760T/LV8761V
Upper-side FET
5A
Lower-side FET
5A
Figure 27. Detection Current vs Temperature (Reference data)
Detection current (A)
6
5
4
3
Upper-side
2
Lower‐side
1
0
‐20
0
20
40
60
80
100
Temperature (℃)
3. Short-circuit Protection Mode
There are 2 operation modes for short protector circuit: 1. [Latch-type] latches output off state. 2. [Auto
reset-type] repeats on/ off of output. LV8760T includes Latch-type only. LV8761V includes selectable
Latch-type and Auto reset-type.
LV8760T
LV8761V
Control Pin
Short-circuit Protection Mode
－
Latch type (fix)
EMM (36pin) = Low
Latch type
EMM (36pin) = High
Auto reset type
19/36
LV8760T/LV8761V Application Note
4. Latch-type (LV8760T/LV8761V common)
The short-circuit protection circuit is activated when it detects the output short-circuit state. If the short-circuit
state continues for the internally preset period ( 4s), the protection circuit turns off the output from which
the short-circuit state has been detected. Then it turns the output on again after a lapse of the timer latch
time described later. If the short-circuit state is still detected, it changes all the outputs to the standby mode
and retains the state. The latched state is released by setting the PS to L.
Output ON
Output ON
H-bridge
output state
Output OFF
Standby state
Threshold voltage
4μs
SCP voltage
Short-circuit
detection state
Short- Release
circuit
Short-circuit
Internal counter
1st counter
start
1st counter 1st counter
stop
start
1st counter
end
2nd counter
start
2nd counter
end
Figure 28. Short-circuit protection Latch-type timing chart
5. How to set the SCP pin constant (timer latch-up setting)
The user can set the time at which the outputs are turned off when short-circuit occurs by connecting a
capacitor across the SCP and GND pins. The value of the capacitor can be determined by the following
formula:
Timer latch-up: Tscp
Tscp  C  Vthscp/Iscp [sec]
Vthscp: Comparator threshold voltage (1V typical)
Iscp: SCP charge current (5A typical)
When a capacitor with a capacitance of 100pF is connected across the SCP and GND pins, for example,
Tscp is calculated as follows:
Tscp = 100pF  1V/5A = 20μs
20/36
LV8760T/LV8761V Application Note
6. Auto Reset Type (LV8761V only)
In LV8761V, short circuit protection mode becomes Auto reset type at EMM = high.
The sequences up to the detection of an output short-circuit state are identical to those which are explained
in Section 1, "Protection Function Operation (Latch Type).
After output is turned off on detection of an output short-circuit condition, the internal counter starts counting
and repeats turning on and off the output as shown in the figure below.
This state continues until the over current state is eliminated.
Exceeding the
over-current
detection
current
ON
OFF
Detection current
sequences
2ms (TYP)
ON
OFF
ON
Output current
SCP voltage
Figure 29. Short-circuit protection Auto Reset type timing char
7. Unusual Condition Warning Output Pin: EMOT (LV8761V only)
The LV8761V is provided with the EMOT pin which notifies the CPU of an unusual condition if the protection
circuit operates by detecting an abnormal condition of the IC. This pin is of the open-drain output type and
requires a pull-up resistor when to be used.
The EMOT pin is placed in the ON state when one of the following conditions occurs.
1. Shorting-to-power or shorting-to-ground occurs at the output pin and the output short-circuit protection
circuit is activated.
2. The IC junction temperature rises and the thermal protection circuit is activated.
The EMOT pin is set to the OFF state when the relevant protection operation is eliminated.
21/36
LV8760T/LV8761V Application Note
Figure30.Short‐circuitProtection(Latch‐type)
OUTA‐GNDshort
Vcc=5V,VM=24V,RNF=0.22Ω,SCP=105pF
PS=High,IN1=High,IN2=Low
10μs/div
Figure31.Short‐circuitProtection(Latch‐type)
OUTB‐VMshort
Vcc=5V,VM=24V,RNF=0.22Ω,SCP=105pF
PS=High,IN1=High,IN2=Low
10μs/div
On
Off
High
Off
Off
Low
Off
Off
EMOT
(LV8761V)
5V/div
High
On
EMOT
(LV8761V)
5V/div
*Low
OUTA
10V/div
Off
Off
OUTA
10V/div
OUTB
10V/div
Off
Off
OUTB
10V/div
Low
SCP
0.5V/div
(1)(2)
(3)(4)
(1)OUTA‐GNDshort.
(2)Short‐circuitstatedetection.
Theoutputisturnedoff.
(3)Theoutputisturnedonagain.
(4)Theoutputoffstateislatched.
WarningOutput(EMOT)isturnedon.
Figure32.
Short‐circuitProtection
(Autoreset‐type:LV8761V)
OUTA‐GNDshort
Vcc=5V,VM=24V
RNF=0.22Ω,SCP=105pF
PS=High,IN1=High,IN2=Low
1ms/div
SCP
0.5V/div
(1)(2)
(3)(4)
(1)OUTB‐VMshort.
*Thevoltageincreasesasaresult ofcurrent
toRNFresistor.Consequentlythemodeshifts
from charge to brake mode. Therefore,
OUTA=Low.
(2)Short‐circuitstatedetection.
Theoutputisturnedoff.
(3)Theoutputisturnedonagain.
(4)Theoutputoffstateislatched.
WarningOutput(EMOT)isturnedon.
EMOT
5V/div
OUTA
10V/div
OUTB
10V/div
SCP
0.5V/div
20μs/div
20μs/div
EMOT
5V/div
EMOT
5V/div
OUTA
10V/div
OUTA
10V/div
OUTB
10V/div
OUTB
10V/div
SCP
0.5V/div
SCP
0.5V/div
22/36
LV8760T/LV8761V Application Note
Charge Pump Circuit
When the PS pin is set High, the charge pump circuit operates and the VG pin voltage is boosted from the
VM voltage to the VM + REG5 voltage. If the VG pin voltage is not boosted sufficiently, the output cannot
be controlled, so be sure to provide a wait time of tONG or more after setting the PS pin High before
starting to drive the motor.
.
Figure 33. Charge Pump circuit timing char
VG voltage is used to drive upper output FET and REG5 voltage is used to drive lower output FET.
Since VG voltage is equivalent to the addition of VM and REG5 voltage, VG capacitor should allow higher
voltage.
The capacitor between CP1 and CP2 is used to boost charge pump. Since CP1 oscillates with 0V↔REG5
and CP2 with VM↔VM+REG5, make sure to allow enough capacitance between CP1 and CP2.
Since the capacitance is variable depends on motor types and driving methods, please check with your
application before you define constant to avoid ripple on VG voltage.
(Recommended value)
VG: 0.1μF
CP1-CP2: 0.1μF
Figure34.ChargePumpOperation
Oscillationfrequency
Vcc=5V,VM=24V
PS=High
CP1‐CP2=0.1μF
VG=0.1μF
5μs/div
VG
5V/div
CP2
5V/div
CP1
5V/div
23/36
LV8760T/LV8761V Application Note
Figure35.ChargePumpOperation
tONG
Vcc=5V,VM=24V
PS=High
CP1‐CP2=0.1μF
VG=0.1μF
50μs/div
PS
5V/div
VM+4V
VG
5V/div
tONG
Figure36.StartuptimewithdifferentVGcapacitor
Vcc=5V,VM=24V
PS=High
CP1‐CP2=0.1μF
VG=0.1μF/0.22μF/1μF
500μs/div
PS
5V/div
VG=0.1μF
5V/div
VG=0.22μF
5V/div
VG=1μF
5V/div
tONG
Thermal shutdown function
The thermal shutdown circuit is incorporated and the output is turned off when junction temperature Tj
exceeds 180C and the abnormal state warning output is turned on (The warning output function is only
LV8761V). As the temperature falls by hysteresis, the output turned on again (automatic restoration).
The thermal shutdown circuit does not guarantee the protection of the final product because it operates
when the temperature exceed the junction temperature of Tjmax=150C.
TSD = 170C (typ)
TSD = 40C (typ)
24/36
LV8760T/LV8761V Application Note
Application Circuit Example
1. When you use the current limit function
<LV8760T>
35kΩ 15kΩ
0.1μF
PGND
VCC 20
2
OUTB
SCP 19
3
OUTB
VREF 18
4
RNF
10μF
5
RNF
- +
6
VM
7
VM
8
OUTA
CP2 13
9
OUTA
VG 12
0.22Ω
M
Control input
LV8760T
1
10 PS
+ -
100pF
IN2 17
Control input
IN1 16
REG5 15
CP1 14
0.1μF
0.1μF
0.1μF
GND 11
<LV8761V>
- +
1 VCC
EMM 36
2 PGND
SCP 35
Control input
100pF
3 NC
VREF 34
4 NC
NC 33
5 NC
NC 32
6 OUTB
NC 31
7 OUTB
IN2 30
8 RNF
IN1 29
Control input
10 VM
- +
Control input
LV8761V
9 RNF
M
NC 28
REG5 27
11 VM
CP1 26
12 OUTA
CP2 25
13 OUTA
NC 24
14 NC
GND 23
15 NC
NC 22
16 NC
VG 21
17 PS
NC 20
18 GND
EMOT 19
Monitor
Setting the current limit value
When VCC = 5V,
Vref = 1.5V
Ilimit = Vref/5/RNF
= 1.5V/5/0.22 = 1.36A
Setting the current limit regeneration time and short-circuit detection time
Tscp  C  Vthscp/Iscp
= 100pF  1V/5A
= 20s
25/36
LV8760T/LV8761V Application Note
2. When you do not use the current limit function
<LV8760T>
- +
Control input
PGND
VCC 20
2
OUTB
SCP 19
3
OUTB
VREF 18
4
RNF
5
RNF
6
VM
7
VM
8
OUTA
CP2 13
9
OUTA
VG 12
LV8760T
M
1
10 PS
+ -
100pF
IN2 17
Control input
IN1 16
REG5 15
CP1 14
GND 11
<LV8761V>
- +
1 VCC
EMM 36
2 PGND
SCP 35
Control input
100pF
3 NC
VREF 34
4 NC
NC 33
5 NC
NC 32
6 OUTB
NC 31
7 OUTB
IN2 30
8 RNF
IN1 29
Control input
10 VM
- +
Control input
LV8761V
9 RNF
M
NC 28
REG5 27
11 VM
CP1 26
12 OUTA
CP2 25
13 OUTA
NC 24
14 NC
GND 23
15 NC
NC 22
16 NC
VG 21
17 PS
NC 20
18 GND
EMOT 19
Monitor
Setting at short-circuit state detection time
Tscp  C  Vthscp/Iscp
= 100pF·1V/5µA
= 20µs
*Do the following processing when you do not use the current limit function.
 It is short between RNF-GND.
 The pin VREF is hung on suitable potential of VCC or lower.
26/36
LV8760T/LV8761V Application Note
3. Stepping motor drive application
<LV8760T>
Note: LV8761V is similar.
Setting the constant current value
When VCC = 5V,
Vref = 1.5V
Iout = Vref/5/RNF
= 1.5V/5/0.22 = 1.36A
Setting at slow-decay time of constant current control and short-circuit detection time
Tscp  C  Vthscp/Iscp
= 100pF  1V/5μA
= 20μs
27/36
LV8760T/LV8761V Application Note
4. Input example of Stepping motor drive application
Full-step excitation control
IN11
IN12
IN21
IN22
（％）
100
Iout1
0
（％）－100
100
Iout2
0
－100
Half-step excitation control
IN11
IN12
IN21
IN22
(%)
100
Iout1
0
－100
(%)
100
Iout2
0
－100
28/36
LV8760T/LV8761V Application Note
Allowable power dissipation
The pad on the backside of the IC functions as heatsink by soldering with the board. Since the heat-sink
characteristics vary depends on board type, wiring and soldering, please perform evaluation with your board for
confirmation.
The following Pd-Ta chart is based on the measurement result using ON semi’s evaluation board and the ICs.
Pd max – Ta
<LV8760T>
Allowable power dissipation, Pd max – W
4.0
3.30
*1 With Exposed Die-Pad substrate
*2 Without Exposed Die-Pad
*1
3.0
2.0
1.60
1.72
*2
1.0
0
– 20
0.83
0
20
40
60
80
100
Ambient temperature, Ta – °C
Substrate Specifications (Substrate recommended for operation of LV8760T)
Size
: 90mm × 90mm × 1.6mm (two-layer substrate [2S0P])
Material
: Glass epoxy
Copper wiring density
: L1 = 95% / L2 = 95%
L1 : Copper wiring pattern diagram
L2 : Copper wiring pattern diagram
29/36
LV8760T/LV8761V Application Note
Pd max – Ta
3.5
Allowable power dissipation, Pd max – W
<LV8761V>
*1
3.15
*2
2.05
3.0
2.5
2.0
1.64
1.5
1.07
1.0
0.5
*1 With Exposed Die-Pad substrate
*2 Without Exposed Die-Pad
0
– 20
0
20
40
60
80
100
Ambient temperature, Ta – °C
Substrate Specifications (Substrate recommended for operation of LV8761T)
Size
: 90mm × 90mm × 1.6mm (two-layer substrate [2S0P])
Material
: Glass epoxy
Copper wiring density
: L1 = 95% / L2 = 95%
L1 : Copper wiring pattern diagram
L2 : Copper wiring pattern diagram
Cautions (LV8760T/LV8761V common)
1) The data for the case with the Exposed Die-Pad substrate mounted shows the values when 90% or more
of the Exposed Die-Pad is wet.
2) For the set design, employ the derating design with sufficient margin.
Stresses to be derated include the voltage, current, junction temperature, power loss, and mechanical
stresses such as vibration, impact, and tension.
Accordingly, the design must ensure these stresses to be as low or small as possible.
The guideline for ordinary derating is shown below:
(1)Maximum value 80% or lower for the voltage rating
(2)Maximum value 80% or lower for the current rating
(3)Maximum value 80% or lower for the temperature rating
3) After the set design, be sure to verify the design with the actual product.
Confirm the solder joint state and verify also the reliability of solder joint for the Exposed Die-Pad, etc.
Any void or deterioration, if observed in the solder joint of these parts, causes deteriorated thermal
conduction, possibly resulting in thermal destruction of IC.
30/36
LV8760T/LV8761V Application Note
LV8760T’s Allowable power dissipation in each PCB size (Reference value)
PCB (1)
PCB (2)
PCB (3)
PCB (4)
PCB SIZE
(1) 90mm × 90mm × 1.6mm (two-layer substrate [2S0P] with backside mounting)
(2) 70mm × 70mm × 1.6mm (two-layer substrate [2S0P] with backside mounting)
(3) 60mm × 60mm × 1.6mm (two-layer substrate [2S0P] with backside mounting)
(4) 40mm × 40mm × 1.6mm (two-layer substrate [2S0P] with backside mounting)
The above chart shows the relation between Pdmax and PCB size.
PCB (1) provides the reference value based on ON semi’s evaluation board of LV8760T. Above
Pdmax values are obtained from the boards which are shrunk accordingly as stated above, where IC
mounting position is the center. Pdmax may fluctuate depending on board layout.
31/36
LV8760T/LV8761V Application Note
Evaluation board
1. Completed PCB with Devices
"VCC"
Power Supply
C6
M
R1
C5
IC1
C4
"VREF"
Power Supply
C3
C2
C7
C1
"VM"
Power Supply
SW1 SW2
SW3
Logic input
2. Bill of Materials for LV8760T and LV8761V Evaluation Board
Designator
C1
Quantity
Description
1
Capacitor
for Charge
pump
1
C2
1
1
C3
1
1
C4
1
1
C5
1
1
C6
1
Capacitor
for Charge
pump
REG5-out
stabilization
Capacitor
VREF
stabilization
Capacitor
Capacitor to
set
SCP timer
VCC Bypass
Capacitor
1
C7
1
R1
1
1
R2
IC1
1
1
VM Bypass
Capacitor
Output
current
detective
Resistor
Pull-up
Resistor
for pin
EMOT
Motor Driver
1
SW1SW3
SW1SW4
3
Switch
Manufacturer
Manufacturer Part Number
Substitution
Allowed
Lead
Free
Adjustment
product
±10%
TDK
FK28X7R1H104K
Yes
Yes
LV8760T
±10%
Murata
GRM188R72A104KA35*
Yes
Yes
LV8761V
±10%
TDK
FK28X7R1H104K
Yes
Yes
LV8760T
±10%
Murata
GRM188R72A104KA35*
Yes
Yes
LV8761V
±10%
TDK
FK28X7R1H104K
Yes
Yes
LV8760T
±10%
Murata
GRM188R72A104KA35*
Yes
Yes
LV8761V
±10%
TDK
FK28X7R1H104K
Yes
Yes
LV8760T
±10%
Murata
GRM188R72A104KA35*
Yes
Yes
LV8761V
±5%
TDK
FK28COG1H101J
Yes
Yes
LV8760T
±5%
Murata
GRM1882C1H101JA01*
Yes
Yes
LV8761V
±10%
TDK
FK28X7R1H104K
Yes
Yes
LV8760T
±10%
GRM188R72A104KA35*
Yes
Yes
LV8761V
±5%
Murata
SUN
Electronic
Industries
JAPAN
RESISTOR
MFG
KNP2WR22J/R0
Yes
Yes
LV8760T
±5%
ROHM
MCR100JZHJLR22
Yes
Yes
LV8761V
KOA
RK73B1JT**473J
Yes
Yes
LV8761V
ON
Semiconductor
LV8760T
No
Yes
LV8760T
LV8761V
No
Yes
LV8761V
MS-621C-A01
Yes
Yes
Value
Tolerance
0.1µF,
50V
0.1µF,
100V
0.1µF,
50V
0.1µF,
100V
0.1µF,
50V
0.1µF,
100V
0.1µF,
50V
0.1µF,
100V
100pF,
50V
100pF,
50V
0.1µF,
50V
0.1µF,
100V
10µF,
50V
0.22Ω,
2W
0.22Ω,
1W
47kΩ,
1/10W
Footprint
±20%
±5%
TSSOP20
J(225mil)
SSOP36J
(275mil)
MIYAMA
ELECTRIC
50ME10HC
Yes
Yes
4
TP1-TP13
13
TP1-TP15
15
LV8760T
LV8761V
LV8760T
LV8761V
Test Point
MAC8
ST-1-3
Yes
Yes
LV8760T
LV8761V
32/36
LV8760T/LV8761V Application Note
3. Evaluation board circuit
<LV8760T>
<LV8761V>
33/36
LV8760T/LV8761V Application Note
4. Evaluation Board Manual
[Supply Voltage]
VM (9 to 35V): Motor Power Supply
VCC (3 to 5.5V): Control Power Supply
VREF (0 to VCC-1.8V): Current Limit Control Reference Voltage
[Toggle Switch State]
Upper Side: High (VCC)
Middle: Open, enable to external logic input
Lower Side: Low (GND)
[Operation Guide]
1. Initial Condition Setting: Set “Open or Low” all switches.
2. Motor Connection: Connect the Motor between OUTA and OUTB.
3. Power Supply: Supply DC voltage to VM, VCC and VREF.
4. Ready for Operation from Standby State: Turn “High” the PS pin toggle switch.
5. Motor Operation: Set IN1, IN2 and EMM (at LV8761V) pins according to the purpose
(See LV8760T or LV8761V‘s logic table).
[Setting for External Component Value]
1. Current limit value
At VREF = 1.5V
Ilimit
= VREF [V]/5/R1 [ohm]
= 1.5 [V] / 5 / 0.22 [ohm]
= 1.36 [A]
2. Current limit regeneration time and short-circuit detection time
Tscp
 C5 [pF] Vthscp[V]/Iscp[A]
= 100[pF]  1[V]/5[A]
= 20[s]
5. Evaluation board waveform (DC motor drive)
Figure 37. Forward ↔ Output off
DC_motor load,PS=High,IN2=Low
Vcc=VREF=5V, VM=24V, RNF=GND
Figure 38. Forward ↔ Brake
DC_motor load,PS=High,IN1=High
Vcc=VREF=5V, VM=24V, RNF=GND
200ms/div
200ms/div
IN1
5V/div
IN2
5V/div
OUTA
10V/div
OUTA
10V/div
OUTB
10V/div
OUTB
10V/div
Motor
current
0 5A/div
Motor
current
0 5A/div
34/36
LV8760T/LV8761V Application Note
Cautions for layout:
●Power supply connection pin [VM,VCC]
 VCC is a control power supply, and VM is a motor power supply.
 Make sure that supply voltage does not exceed the absolute MAX ratings under no circumstance.
Noncompliance can be the cause of IC destruction and degradation.
 Caution is required for VM supply voltage because this IC performs switching.
 The bypass capacitor of the VM power supply should be close to the IC as much as possible to stabilize
voltage. Also if you intend to use high current or back EMF is high, please augment enough capacitance.
●GND pin [GND, PGND, RNF-resistor GND line, exposed die pad]
 High current flows into the PGND and GND side of RNF resistor; therefore, connect PGND and RNF –
GND independently.
 On the other hand, since PGND and GND are connected through silicon board, if the line of PGND is too
long, difference of electric potential occurs between PGND and GND which creates gradient to the GND
electric potential within the IC board. This can be the cause of the IC malfunction. Hence make sure to
connect PGND and RNF – GND independently so that the pins do not share the common impedance with
GND. And GND, PGND, and RNF should be single-point grounded to the low impedance GND area near
the IC. Also the capacitor between VM and GND should be connected adjacent to the IC.
 The exposed die-pad is connected to the board frame of the IC. Therefore, do not connect it other than
GND. Independent layout is preferable. If such layout is not feasible, please connect it to signal GND. Or
if the area of GND and PGND is larger, you may connect the exposed die pad to the GND.
(The independent connection of exposed die pad to PGND is not recommended.)
●Internal power supply regulator pin [REG5]
 REG5 is a reference supply of the charge pump circuit and the power supply to drive output FET (typ 5V).
 When VM supply is powered and PS is “High”, REG5 operates.
 Please connect capacitor for stabilize REG5. The recommendation value is 0.1uF.
 Since the voltage of REG5 fluctuates (±10%), do not use it as reference voltage that requires accuracy.
●Input pin
 The logic input pin incorporates pull-down resistor (100kΩ).
 When you set input pin to low voltage, please short it to GND because the input pin is vulnerable to noise.
 The input is TTL level (H: 2V or higher, L: 0.8V or lower).
 VREF pin is high impedance.
●OUT pin [OUTA, OUTB]
 During chopping operation, the output voltage becomes equivalent to VM voltage, which can be the cause
of noise. Caution is required for the pattern layout of output pin.
 The layout should be low impedance because driving current of motor flows into the output pin.
 Output voltage may boost due to back EMF. Make sure that the voltage does not exceed the absolute
MAX ratings under no circumstance. Noncompliance can be the cause of IC destruction and degradation.
●Current sense resistor connection pin [RNF]
 To perform current limit control, please connect resistor to RNF pin.
 To perform saturation drive (without current limit control), please connect RNF pin to GND, and connect
VREF pin to VCC.
 If RF pin is open, then short protector circuit operates. Therefore, please connect it to resistor or GND.
 The motor current flows into RF – GND line. Therefore, please connect it to common GND line and low
impedance line.
●NC pin
 NC pin is not connected to the IC.
 If VM line and output line are wide enough in your layout, please use NC.
35/36
LV8760T/LV8761V Application Note
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any
such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the
part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
36/36