LV8121V Three-phase Brushless Motor Driver IC Application Note http://onsemi.com Overview The LV8121V is a three-phase brushless motor driver that uses a PWM drive technique. The motor speed is controlled by changing the PWM duty that based on an analog voltage input. The motor driver includes an automatic return constraint protection circuit and is optimal for driving fan motors. Features PWM control based on an analog voltage input (the CTL voltage), synchronous rectification One Hall-effect sensor FG output Automatic return constraint protection circuit (ON/OFF=1/15) Start/Stop switching circuit, Forward/Reverse switching circuit Current limiter circuit, Low-voltage shutdown protection circuit, Thermal shutdown protection circuit Typical Applications Fan motors for Consumer electronics Pump motors for Hot water heaters CSD FG HB CT RT GND1 VREG CP2 CP1 VG VCC1 VCC2 NC RFS RF NC NC GND2 NC OUT1 OUT1 OUT2 Pin Assignment 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PWM LIM CTL S/S IN3- IN3+ IN2- IN2+ IN1- IN1+ NC VCC2 NC F/R RF NC NC GND2 NC OUT3 OUT3 OUT2 LV8121V Semiconductor Components Industries, LLC, 2013 November, 2013 Top view 1/23 LV8121V Application Note Package Dimensions unit : mm (typ) 3333A TOP VIEW SIDE VIEW BOTTOM VIEW 15.0 44 23 (3.5) 0.5 5.6 7.6 (4.7) 0.65 0.22 22 0.2 1.7 MAX 1 (0.68) 0.05 (1.5) SIDE VIEW SANYO : SSOP44K(275mil) Mounting Pad Sketch (Unit: mm) Reference symbol SSOP44K(275mil) eE 7.00 e 0.65 b3 0.32 l1 1.00 X (4.7) Y (3.5) Caution: The package dimension is a reference value, which is not a guaranteed value. 2/23 VREG VIN(CTL) PWM LIM CTL RT CT REF OSC COMP S/S S/S S/S FG CIRCUIT CSD CIRCUIT PWM OSC FG CSD VREG F/R F/R F/R IN1 TSD IN3 LVSD RFS CURR LIM CONTROL CIRCUIT HALL AMP & MATRIX IN2 RF Die-Pad VREG CHARGE PUMP DRIVER HB HB GND1 GND2 OUT3 OUT2 OUT1 VG CP2 CP1 VCC2 VCC1 GND1 VREG + VCC LV8121V Application Note Block Diagram 3/23 LV8121V Application Note Allowable power dissipation, Pd max -- W 2.0 1.7 Pd max -- Ta Mounted on the specified board: 114.3×76.1×1.6mm3 glass epoxy 1.5 1.0 0.68 0.5 0 --30 0 30 60 90 120 Ambient temperature, Ta -- C Three-phase logic truth table (A high level input is the state where IN+ > IN) F/R = L F/R = H Output IN1 IN2 IN3 IN1 IN2 IN3 OUT1 OUT2 OUT3 1 H L H L H L L H M 2 H L L L H H L M H 3 H H L L L H M L H 4 L H L H L H H L M 5 L H H H L L H M L 6 L L H H H L M H L Specifications Absolute Maximum Ratings at Ta = 25C Parameter Supply voltage Symbol Conditions Ratings Unit VCC max VCC pin 36 VG max VG pin 42 V V Output current IO max t 500ms 3.5 A Allowable power dissipation Pd max Mounted on the specified board * 1.7 W Operating temperature Topr -30 to +100 C Storage temperature Tstg -55 to +150 C Junction temperature Tjmax 150 C * Specified board : 114.3mm 76.1mm 1.6mm, glass epoxy board Caution 1) Absolute maximum ratings represent the values which cannot be exceeded for any length of time. Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current, high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4/23 LV8121V Application Note Recommendation Operating Conditions at Ta = 25C Parameter Supply voltage range Symbol Conditions Ratings Unit VCC 8.0 to 35 V 5V constant voltage output current IREG 0 to -6 mA HB output current IHB 0 to -7 mA FG applied voltage VFGS 0 to 6 V FG output current IFGS 0 to 5 mA Electrical Characteristics at Ta 25C, VCC = 24V Parameter Symbol Supply current 1 ICC1 Supply current 2 ICC2 Conditions Ratings min typ At stop Unit max 3.5 4.7 mA 1.1 1.5 mA Output block RON(L1) IO= 1.2A 0.26 0.43 Ω RON(L2) IO= 2.0A 0.26 0.43 Ω RON(H1) IO= -1.2A 0.27 0.45 Ω RON(H2) IO= -2.0A 0.27 0.45 Ω Mid output current IO(M) VO= 12V 120 170 A Lower side diode forward voltage VD(L1) ID= -1.2A 0.9 1.20 V VD(L2) ID= -2.0A 1.0 1.35 V VD(H1) ID= 1.2A 0.9 1.20 V VD(H2) ID= 2.0A 1.0 1.35 V 5.0 5.4 V Lower side output ON resistance Upper side output ON resistance Upper side diode forward voltage 5V Constant voltage Output Output voltage VREG 4.6 Line regulation ΔV(REG1) VCC= 8.0 to 35V Load regulation ΔV(REG2) IO= -1 to -6mA 20 100 mV 5 100 mV Hall Amplifier -2 A Input bias current IB(HA) -0.1 Common mode input voltage range 1 VICM1 When Hall-effect sensors are used Common mode input voltage range 2 VICM2 When one-side inputs are biased Hall input sensitivity VHIN SIN wave Hysteresis width ΔVIN(HA) 9 20 35 mV Input voltage L → H VSLH 3 8 16 mV Input voltage H → L VSHL -20 -12 -5 mV VREG-0.27 VREG-0.18 VREG-0.10 0.3 VREG-1.7 V 0 VREG V (Hall IC application) 80 mVp-p HB pin Output voltage VHBO IHB= -0.5mA Output leakage current IL(HB) VO= 0V V A -10 Reference Oscillator (CT pin) High level voltage VH(CT) VREG x 0.54 VREG x 0.56 VREG x 0.58 V Low level voltage VL(CT) VREG x 0.43 VREG x 0.45 VREG x 0.47 V Amplitude V(CT) VREG x 0.10 VREG x 0.11 VREG x 0.12 Oscillation frequency f(REF) 1.71 2.11 2.51 VREG-0.15 VREG-0.1 VREG-0.05 V 0.05 0.1 0.15 V VCC +4.1 VCC +4.7 VCC +5.4 V VCC -1.4 VCC -1.1 VCC -0.7 V 0.75 0.90 C= 56pF , R= 11kΩ V MHz RT pin High level output voltage VOH(RT) IRT= -0.3mA Low level output voltage VOL(RT) IRT= 0.3mA Charge Pump Output (VG pin) Output voltage VGOUT CP1 pin High level output voltage VOH(CP1) ICP1= -2mA Low level output voltage VOL(CP1) ICP1= 2mA Charge pump frequency f(CP1) 0.55 f(REF) / 32 V MHz Continued on next page. 5/23 LV8121V Application Note Continued from preceding page. Parameter Symbol Conditions Ratings min typ Unit max PWM Oscillator High level voltage VH(PWM) 2.75 3.05 3.35 V Low level voltage VL(PWM) 1.20 1.35 1.50 V Amplitude V(PWM) 1.40 1.70 2.00 V Charge current ICHG VPWM= 2.1V -80 -63 -45 A Oscillation frequency f(PWM) C= 1800pF 15.1 19.2 24.8 kHz -2 -0.1 LIM pin Input bias current IB(LIM) A CTL pin Input voltage Input bias current VCTL1 Output duty: 100% 2.74 3.07 3.40 VCTL2 Output duty: 0% 1.15 1.33 1.51 -2 -0.2 0.23 0.25 0.275 V V IB(CTL) V V A Current limiter operation Limiter voltage VRF CSD Oscillator High level voltage VH(CSD) 2.75 3.05 3.35 Low level voltage VL(CSD) 1.43 1.68 1.93 V Amplitude V(CSD) 1.12 1.37 1.62 V Charge current ICSD1 -13.5 -10.5 -7.0 A Discharge current ICSD2 8.0 11.5 14.5 A Oscillation frequency f(CSD) C= 0.047 F 62 83 104 Hz TSD Design target value * (Junction temperature) 150 180 ℃ ΔTSD Design target value * (Junction temperature) 40 ℃ 0.1 Thermal shutdown operation Thermal shutdown operation temperature Hysteresis width FG pin Low level output voltage VOL(FG) IFG= 2mA Output leakage current IL(FG) VFG= 6V 0.3 V 10 A Low-voltage shutdown protection circuit Operating voltage VSDL 6.52 7.03 7.54 V Release voltage VSDH 6.98 7.49 8.00 V Hysteresis width ΔVSD 0.36 0.46 0.56 V VREG V F/R pin High level input voltage range VIH(FR) 2.0 Low level input voltage range VIL(FR) 0 1.0 V Input open voltage VIO(FR) VREG-0.5 VREG V Hysteresis width VIS(FR) 0.15 0.5 V 0.35 High level input current IIH(FR) VF/R= VREG -10 0 10 A Low level input current IIL(FR) VF/R= 0V -80 -50 -35 A V S/S pin High level input voltage range VIH(SS) 2.0 VREG Low level input voltage range VIL(SS) 0 1.0 V Input open voltage VIO(SS) VREG-0.5 VREG V Hysteresis width VIS(SS) 0.15 0.5 V High level input current IIH(SS) VS/S= VREG -10 0 10 A Low level input current IIL(SS) VS/S= 0V -80 -50 -35 A 0.35 * : These items are design target value and are not tested. 6/23 5 5.4 4 5.2 VREG (V) ICC1(mA) LV8121V Application Note 3 2 5 4.8 4.6 1 4.4 0 5 10 15 20 25 30 35 5 40 10 15 0.35 0.35 0.3 0.3 0.25 OUT1 OUT2 OUT3 0.2 0.15 1 2 30 35 40 3 0.25 OUT1 OUT2 OUT3 0.2 0.15 0 4 1 2 3 4 Iout (A) Iout (A) Figure 4. Upper side output ON resistance vs Output current Figure 3. Lower side output ON resistance vs Output current 1.2 1.2 1.1 1.1 VD (V) VD (V) 25 Figure 2. VREG output voltage vs VCC voltage (Io=-1mA) Ron (Ω) Ron (Ω) Figure 1. Supply current vs Supply voltage 0 20 VCC (V) VCC (V) 1 0.9 OUT1 OUT2 OUT3 0.8 1 0.9 OUT1 OUT2 OUT3 0.8 0.7 0.7 0 1 2 3 4 0 1 2 3 Iout (A) Iout (A) Figure 5. Lower side diode forward voltage vs Output current Figure 6. Upper side diode forward voltage vs Output current 4 7/23 6 30 5 25 f(PWM) (kHz) VHBO (V) LV8121V Application Note 4 3 2 1 20 15 10 5 ‐7 ‐6 ‐5 ‐4 ‐3 ‐2 ‐1 0 IHB (mA) ‐40 ‐20 0 20 40 60 80 100 Temperature (℃) Figure 7. HB pin output voltage vs HB current Figure 8. PWM pin oscilation frequency vs Temperature (C=1800pF) VOL(FG) (V) 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 IFG (mA) Figure 9. FG pin output voltage vs FG current 8/23 LV8121V Application Note Pin Function Pin No. 1 Pin name PWM Function Pin to set the PWM oscillation frequency. Connect a capacitor between this pin and GND1. Equivalent circuit VREG A frequency of about 19kHz can be set by using a 1800pF capacitor. 200 Ω 1 950 Ω 2 LIM Pin to set the minimum output duty. A minimum output duty can be set by inputting VREG a fixed voltage to the LIM pin through resistor division of VREG. Connect the LIM pin to GND1 if this pin is not used, then the minimum output duty becomes 0 %. 500 Ω 3 CTL 2 Pin to control the output duty. The output duty is determined by the result of VREG comparing the CTL pin voltage with the PWM oscillation waveform. When the CTL pin is open, the output duty becomes 100%. Therefore, connect a pull-down resistor to prevent open. 500 Ω 4 S/S 3 Start / Stop control pin. Low : 0V to 1.0V VREG High : 2.0V to VREG Goes high when left open. Low for start. The hysteresis width is about 0.35V. 100k Ω 10k Ω 4 Continued on next page. 9/23 LV8121V Application Note Continued from preceding page. Pin No. Pin name 6 IN3IN3+ 7 IN2- 8 IN2+ 9 IN1- 10 IN1+ 5 14 F/R Function Hall input pins. The input is seen as the high level input when IN+ IN-, and as the low level input for the Equivalent circuit VREG opposite state. If noise on the Hall signals is a problem, connect a capacitor between the corresponding IN+ and IN- inputs. 5 6 7 8 9 10 Forward / Reverse control pin. Low : 0V to 1.0V VREG High : 2.0V to VREG Goes high when left open. Low for forward. 100k Ω The hysteresis width is about 0.35V. 14 10k Ω 34 VCC1 Power supply pin. (For systems other than the motor drive output.) Connect a capacitor between this pin and GND1 for stabilization. 12,33 VCC2 Motor drive output power supply pins. VCC2 12 33 20,21 OUT3 22,23 OUT2 20 21 24,25 OUT1 22 23 15,30 RF Motor drive output pins. 24 25 Source pins of the lower side output FET. Connect a resistor (Rf) between these pins and GND. 18,27 31 GND2 Motor drive output circuit GND pins. RFS Output current detection pin. Connect the RFS pin to the RF pin. 18 27 15 30 VREG 5k Ω 31 Continued on next page. 10/23 LV8121V Application Note Continued from preceding page. Pin No. 35 Pin name VG Function Equivalent circuit Charge pump output pin. VCC2 Connect a capacitor between this pin and VCC2. 300 Ω 37 CP2 Pin to connect the capacitor for charge pump. Connect a capacitor between this pin and CP1. 35 36 CP1 37 Pin to connect the capacitor for charge pump. VCC2 Connect a capacitor between this pin and CP2. 300 Ω 38 VREG 36 5V constant voltage output pin. VCC1 (Power supply pin for the control circuits.) Connect a capacitor between this pin and GND1 50 Ω for stabilization. 38 39 GND1 GND pin for the control circuits. 40 RT Pin to set the reference oscillation frequency. Connect a resistor to charge / discharge the VREG capacitor of CT between this pin and CT. 40 41 CT 200 Ω 41 Pin to set the reference oscillation frequency. Connect a capacitor between this pin and GND1. Continued on next page. 11/23 LV8121V Application Note Continued from preceding page. Pin No. 42 Pin name HB Function Equivalent circuit Hall bias switch pin. VREG Goes off when the S/S input is the stop mode. 250 Ω 42 100k Ω 43 FG One hall-effect sensor FG output pin. VREG (This is an open-drain output.) 43 44 CSD Pin to set the operating time of the constraint protection. VREG Connect a capacitor between this pin and GND1. 500 Ω 11,13 NC No connection pins. Die-Pad Exposed Die-Pad. 44 16,17 19,26 28,29 32 Backside metal The metal of the IC’s backside is the Exposed Die-pad and is internally connected to GND1, GND2. For stabilization, connect the Exposed Die-pad to GND1 externally. 12/23 LV8121V Application Note Description of LV8121V 1. Motor Drive Output Circuit The LV8121V provides a charge pump circuit and implements both upper side and lower side N-channel power FET drive circuit. This IC employs the direct PWM drive technique. The motor speed is controlled by changing the output duty according to an analog voltage input (CTL). The upper side N-channel power FET is switched so that the output duty tracks the CTL voltage. The PWM frequency is determined by the capacitor connected between the PWM pin and GND1. When the PWM switching of the upper side N-channel power FET is off, the lower side N-channel power FET is turned on (synchronous rectification). Therefore, it is possible to reduce the temperature increase of the lower side N-channel power FET. 2. PWM Oscillator The PWM frequency is set by the oscillation frequency of the PWM pin. When a capacitor C [F] is connected between the PWM pin and GND1, the PWM frequency (fPWM) is calculated as follows. fPWM = 1 / (28900 x C) When a 1800pF capacitor is connected, this frequency becomes about 19kHz. By the variance of the IC, “28900” of the above formula has varied from 22400 to 36800. If the PWM frequency is too high, since the switching power loss will be large, the IC temperature increase will be excessive. The PWM frequency therefore should be normally kept below 50kHz, which is achieved with a capacitor C of 1000pF or higher. The GND lead of the connected capacitor to the PWM pin should be connected as close as possible to the GND1 pin. 3. Output Duty The CTL voltage and the PWM oscillation waveform are compared to determine the output duty of the upper side N-channel power FET. If the LIM pin is not used (LIM=GND), the output duty becomes 0% when the CTL voltage is lower than about 1.3V and 100% when it exceeds about 3.1V. For the application that inputs a fixed voltage to the LIM pin, the LIM voltage and the PWM oscillation waveform are compared to determine the minimum output duty. Accordingly, even if the CTL voltage is lower than the LIM voltage, the output duty does not decrease below the minimum output duty. PWM oscillation waveform LIM voltage CTL voltage compared result ON Upper side FET (PWM) OFF ON Lower side FET (synchronous rectification) OFF If a minus voltage is applied to the CTL pin, this pin current must be limited within 2mA by inserting the resistor of about 200Ω. When the CTL pin is open, the output duty becomes 100%. Therefore, connect a pull-down resistor to prevent open. If the output duty is fast reduced by dropping the CTL voltage quickly when the motor speed is changed from high to low, since this IC employs the synchronous rectification, the lower side N-channel power FET can be the short brake condition that turns on two phases. If the lower side N-channel power FET (synchronous rectification) is switched from on to off while this condition, the motor current may flow on the power supply side, and the power supply voltage may bounce. The bounce of the power supply voltage is different on the motor speed, the varied range of the CTL voltage and the capacitance of the power supply line. Therefore, check sufficiently that the bounce of the power supply voltage does not exceed the maximum rating when the CTL voltage is changed. Continued on next page. 13/23 LV8121V Application Note Continued from preceding page. In case of limiting the bounce of the power supply voltage, the maximum voltage of To VG the VCC can be limited according to the following method. The maximum voltage 160kΩ 5.1kΩ of the VG is limited by using Zener diode, NPN transistor and some resistors. Normally, the relation between VG and VCC becomes “VG = VCC + 4.7V”. If 5.6V 33kΩ VCC rises above “VGmax - 4.7V” when VG is limited to VGmax, this relation does Zener not keep. Because the sufficient gate voltage cannot be applied to the upper side N-channel power FET when this relation does not keep, this IC includes the protective function that turns off the upper side N-channel power FET. Accordingly, if VCC rises above “VGmax - 4.7V” when VG is limited to VGmax, the upper side N-channel power FET is turned off, and the VCC bounce caused by dropping the CTL voltage can be limited to “VCC = VGmax - 4.7V”. When the above reference circuit is used, VG is limited to about 36.7V, and VCC is limited to about 32.0V. But this function does not guarantee that any VCC bounce can be limited. If VCC is steeply bounced by dropping the CTL voltage, this function may not limit the VCC bounce. 4. Current Limiter Circuit The current limiter circuit limits the output current peak to the value determined by “I = VRF / Rf” (VRF = 0.25V typ., Rf: current detection resistor). When the current limiter is operating, the upper side N-channel power FET is switched, and the output current is suppressed by reducing the output duty. 5. Reference Oscillator Connect a 56pF capacitor between CT and GND1, and a 11kΩ resistor between RT and CT. Then, the reference oscillation frequency becomes about 2.1MHz. The reference oscillation frequency functions as a reference clock for the internal logic circuit. The charge pump circuit boosts the voltage using a frequency that is 1/32 of the reference oscillation frequency. 6. Start / Stop Switching Circuit When the S/S pin is set to the low level, start/stop switching circuit is the start mode. Inversely, when the S/S pin is set to the high level or open, start/stop switching circuit is the stop mode. This IC goes into a power saving state that reduces the supply current at the stop mode. In the power saving state, the bias current is removed from most of the circuits in the IC. The operating circuits in the power saving state are limited to the start/stop switching circuit and the 5V constant voltage output. The other circuits do not operate. Both upper side and lower side N-channel power FET are turned off in the power saving state. If a minus voltage is applied to the S/S pin, this pin current must be limited within 2mA by inserting the resistor of about 200Ω. 7. Forward / Reverse Switching Circuit The motor rotation direction can be switched by using the F/R pin. However, the following notes must be observed if the F/R pin is switched while the motor is rotating. ･This IC is designed to avoid the through current when the direction is switched. However, the bounce of the VCC voltage (due to the motor current that flows instantly on the power supply side) may be caused during the direction switching. If this bounce is a problem, the capacitance inserted between VCC and GND must be increased. ･If the motor current after the direction switching exceeds the current limiter value, the upper side N-channel power FET will be turned off, but the lower side N-channel power FET will be the short brake condition. On the short brake condition, the current determined by the motor back EMF voltage and the coil resistance will flow. Because the current limiter circuit of this IC cannot limit this current, applications must be designed so that this current does not exceed the maximum rating (3.5A). When the motor speed is higher, the direction switching is dangerous. If a minus voltage is applied to the F/R pin, this pin current must be limited within 2mA by inserting the resistor of about 200Ω. 14/23 LV8121V Application Note 8. Hall Input Signal The input amplitude of 100mVp-p or more (differential) is desirable in the Hall inputs. The closer the input wave-form is to a square wave, the required input amplitude is lower. Inversely, the closer the input wave-form is to a triangular wave, the higher input amplitude is required. Also, note that the input DC voltage must be set within the common mode input voltage range. For the Hall IC application, one side (either the + or – side) of the Hall inputs must be fixed at a voltage within the common mode input voltage range that applies when the Hall-effect sensors are used, and the input voltage range for the other side becomes 0V to VREG. If noise on the Hall signals is a problem, that noise must be excluded by inserting capacitor between the Hall inputs as close as possible to these pins. When the Hall inputs for all three phases are in the same state, all the outputs (the both upper side and lower side N-channel power FET) are turned off. 9. FG Output The FG pin is the pulse output that has the same frequency as Hall input IN1 (one Hall-effect sensor FG output). 10. HB Pin The HB pin is the 5V constant voltage output that combines the switch function. This pin is connected to the base of external NPN transistor that supplies the bias of the Hall-effect sensors. If the HB output is turned off, this external NPN transistor is too turned off, and the bias of the Hall-effect sensors is cut (Hall bias switch). The HB output is turned off and is made pull-down by a 100kΩ internal resistor when the S/S pin is the stop mode. Therefore, the bias of the Hall-effect sensors can be cut when the S/S pin is the stop mode. In case the LIM pin is not used (LIM=GND), if the CTL voltage falls below 0.7V, the HB output is turned off, and the bias of the Hall-effect sensors is cut. In case the minimum output duty is determined by the LIM pin, even if the CTL voltage falls below 0.7V, the HB output is not turned off. If the HB pin is not used, keep open. 11. Constraint Protection Circuit The constraint protection circuit operates to turn the motor drive (the upper side N-channel power FET) on or off repeatedly in the motor constrained state. Therefore, the IC and the motor are protected. The drive on/off time can be set by adjusting the oscillation frequency of the CSD pin with external capacitor. When a capacitor C [F] is connected between the CSD pin and GND1, the drive on/off time is calculated as follows. TCSD1 (drive on time) = 8.21 x C TCSD2 (drive off time) = TCSD1 x 15 When a 0.047F capacitor is connected, this protection function will iterate an on/off period in which drive is on for about 0.39sec and off for about 5.8sec. By the variance of the IC, “8.21” of the above formula has varied from 5.41 to 11.01. If the switching from L to H of the Hall input IN1 (the rising edge on the FG output) is not caused during the drive on time, this protection function turns the motor drive off, and returns the motor drive on after the drive off time. If the drive on time to be set is too short, this protection function operates at a normal motor start-up, and the motor may not speed up since this protection function iterates an on/off period. Also, if the motor speed is too low, this protection function operates when one cycle of the Hall input IN1 is longer than the drive on time. The drive on time must be set to a sufficient time so that this protection function does not operate except the motor constrained state. The oscillation waveform of the CSD pin is used for some circuits in addition to the constraint protection circuit. Therefore, it is desirable to oscillate the CSD pin even if the constraint protection function is unnecessary. The CSD pin combines the function as the initial reset pin. The time that the CSD voltage is charged to about 1.25V is determined as the initial reset. At the initial reset, all the outputs (the both upper side and lower side N-channel power FET) are turned off. If the constraint protection function is not used, the oscillation of the CSD pin must be stopped by connecting a 220kΩ resistor and a 0.01F capacitor in parallel between the CSD pin and GND1. However, when the oscillation of the CSD pin is stopped, note that some functions do not operate in the following cases. ･If the motor does not rotate at the motor start-up because the motor is constrained, the upper side N-channel power FET may be switched by the current limiter. But, the synchronous rectification does not operate when the oscillation of the CSD pin is stopped. ･In case the LIM pin is not used (LIM=GND), even if the CTL voltage falls below 0.7V, the HB output is not turned off when the oscillation of the CSD pin is stopped. 15/23 LV8121V Application Note 12. Low-voltage Shutdown Protection Circuit The IC includes a low-voltage shutdown protection circuit to protect against incorrect operation when the VCC power supply is switched on or if the VCC voltage falls below the allowable operating range. When the VCC voltage falls below the specified voltage (VSDL), this protection function operates, and all the outputs (the both upper side and lower side N-channel power FET) are turned off. When the VCC voltage rises above the release voltage (VSDH), this protection function is released. 13. Thermal Shutdown Protection Circuit If the junction temperature rises to the specified temperature (TSD), this protection function operates, and the upper side N-channel power FET is turned off. If the temperature decrease falls to more than the hysteresis width (ΔTSD), this protection function is released. 14. Power Supply Stabilization Because a large switching current flows in the VCC line, the line inductance and other factors can lead to VCC voltage fluctuations. Sufficient capacitance should be provided between VCC and GND for stabilization. When long wiring routes are used, choose a capacitor with even larger capacitance. Ceramic capacitors of about 0.2F must be connected between the VCC1 pin and the GND1 pin as close as possible to these pins for excluding noise. 15. VREG Pin The VREG pin is the power supply for the control circuits. Therefore, a capacitor of about 0.1F must be connected between the VREG pin and the GND1 pin as close as possible to these pins for stabilization. 16. VG Pin When the S/S pin is the stop mode, the VG pin is the high-impedance condition in the IC. If the ambient temperature of the capacitor inserted between VG and VCC2 becomes high when the VG pin is the high-impedance condition, since the voltage charged in this capacitor may rise due to the temperature characteristic of the capacitor, the VG voltage may rise. Therefore, prevent the VG voltage from rising by inserting the resistor of about 200 kΩ between VG and VCC2 or VG and GND1 so that the VG pin is not the high-impedance condition. 17. Notes on wiring of a Printed Circuit Board Two pins are provided for each of pins (VCC2, RF, OUT1, OUT2, OUT3, GND2) where large current flows. Both of these pins should be externally connected. 18. The Metal of the IC’s Backside The metal of the IC’s backside is the Exposed Die-pad and is internally connected to GND1, GND2. For stabilization, connect the Exposed Die-pad to GND1 externally. The IC’s generation of heat can be efficiently diffused to a printed circuit board by soldering the Exposed Die-pad to the copper of the printed circuit board. 19. NC Pins The NC pins are electrically open. These pins may be used for wiring routes. 16/23 LV8121V Application Note Three-phase logic timing chart (example of forward rotation) When F/R＝”L” ＩＮ１ ＩＮ２ ＩＮ３ ＯＵＴ１ H M L ＯＵＴ２ H M L ＯＵＴ３ H M L ＦＧ H : The upper FET is turned ON. The lower FET is turned OFF. M : The upper FET is turned OFF. The lower FET is turned OFF. L : The upper FET is turned OFF. The lower FET is turned ON. When F/R＝”H” ＩＮ１ ＩＮ２ ＩＮ３ ＯＵＴ１ H M L ＯＵＴ２ H M L ＯＵＴ３ H M L ＦＧ H : The upper FET is turned ON. The lower FET is turned OFF. M : The upper FET is turned OFF. The lower FET is turned OFF. L : The upper FET is turned OFF. The lower FET is turned ON. 17/23 LV8121V Application Note Three-phase logic timing chart (example of reverse rotation) When F/R＝”L” ＩＮ１ ＩＮ２ ＩＮ３ ＯＵＴ１ H M L ＯＵＴ２ H M L ＯＵＴ３ H M L ＦＧ H : The upper FET is turned ON. The lower FET is turned OFF. M : The upper FET is turned OFF. The lower FET is turned OFF. L : The upper FET is turned OFF. The lower FET is turned ON. When F/R＝”H” ＩＮ１ ＩＮ２ ＩＮ３ ＯＵＴ１ H M L ＯＵＴ２ H M L ＯＵＴ３ H M L ＦＧ H : The upper FET is turned ON. The lower FET is turned OFF. M : The upper FET is turned OFF. The lower FET is turned OFF. L : The upper FET is turned OFF. The lower FET is turned ON. 18/23 LV8121V Application Note Application Circuit for Hall elements (Reference value) 100Ω 2SC5964 100Ω 24V Exposed Die-Pad 160 kΩ 27 kΩ 0.1μF 0.1 μF 47μF 1500pF 44 43 42 41 40 39 38 37 36 CSD FG HB CT RT GND1 VREG CP2 CP1 11 kΩ RFS RF NC NC OUT1 OUT1 OUT2 F/R RF NC NC GND2 NC OUT3 OUT3 OUT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC GND2 NC 23 NC 24 VCC2 25 NC 26 IN1+ 27 IN1- 28 IN2+ 29 IN2- 30 IN3+ 31 IN3- 32 S/S 33 CTL 34 LIM 35 PWM Capacitor for setting Constraint protection See P.15/23 0.1μF 0.033μF 56pF VCC2 Reference Oscillator See P.14/23 Resistor for setting Current limiter See P.14/23 0.17Ω/1W 0.2μF FG 0.047μF Capacitor for setting VG current capacity See P.11/23 2SC 5964 5.6V Zener 33 kΩ 10 kΩ Capacitor for VREG pin noise elimination See P.16/23 5.1kΩ VCC1 15 kΩ Capacitor for VCC pin noise elimination See P.16/23 510Ω/0.5W VG Resistor for setting Minimum output duty See P.13/23 Capacitor for VCC pin noise elimination See P.16/23 Circuit for setting VG voltage limit See P.14/23 Circuit for setting Hall element current See P.15/23 FG pull-up resistor See P.12/23 LV8121V 1800pF CTL pull-down resistor See P.13/23 200 Ω 100kΩ Capacitor for setting PWM frequency See P.13/23 4700 pF 51Ω CTL 4700 pF 4700 pF 200 Ω F/R S/S Resistor for setting Hall element current See P.15/23 Resistor for Pin current limit See P.14/23 Capacitor for Hall noise elimination See P.15/23 Resistor for Pin current limit See P.14/23 Application Circuit for Hall ICs (Reference value) Circuit for setting VG voltage limit See P.14/23 FG pull-up resistor See P.12/23 Resistor for setting Minimum output duty See P.13/23 160 kΩ 5.1kΩ 0.1 μF 47μF 44 43 42 41 40 39 38 37 36 CSD FG HB CT RT GND1 VREG CP2 CP1 RF NC NC OUT1 OUT1 OUT2 RF NC NC GND2 NC OUT3 OUT3 OUT2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC RFS F/R 2 GND2 NC 1 VG NC 23 VCC2 24 NC 25 IN1+ 26 IN1- 27 IN2+ 28 IN2- 29 IN3+ 30 IN3- 31 S/S 32 CTL 33 LIM 34 PWM 35 VCC2 1500pF 11 kΩ Capacitor for setting Constraint protection See P.15/23 0.1μF 0.033μF 56pF VCC1 Reference Oscillator See P.14/23 Resistor for setting Current limiter See P.14/23 0.17Ω/1W 0.2μF FG 0.047μF Capacitor for setting VG current capacity See P.11/23 2SC 5964 5.6V Zener 33 kΩ 10 kΩ Capacitor for VREG pin noise elimination See P.16/23 Capacitor for VCC pin noise elimination See P.16/23 24V Exposed Die-Pad 27 kΩ 15 kΩ Capacitor for VCC pin noise elimination See P.16/23 LV8121V Capacitor for setting PWM frequency See P.13/23 CTL pull-down resistor See P.13/23 1800pF CTL Resistor for Pin current limit See P.14/23 Hall IC pull-up resistor See P.15/23 Capacitor for Hall noise elimination See P.15/23 200 Ω 200 Ω 100kΩ S/S 10 kΩ 10 kΩ 10 kΩ 10 kΩ 4700 pF 4700 pF 4700 pF 10 kΩ Hall IC (IN3) Hall IC (IN2) Hall IC (IN1) F/R Resistor for Pin current limit See P.14/23 Resistor for setting One side input See P.15/23 19/23 LV8121V Application Note Evaluation Board (“M-DrAGON means Motor-Driver And GUI produced by ON semiconductor) 24V Parts for Hall elements F/R MOTOR CONNECTOR1 MOTOR CONNECTOR2 FG S/S CTL LIM Figure10. “M-DrAGON” overview (Top view) IC4: 3-Pin Regulator Daughter Board IC2-3: Level shifter Figure11. “M-DrAGON” overview (Bottom view) Figure12. Images of GUI 20/23 LV8121V Application Note Bill of Materials for LV8121V Evaluation Board Designator IC1 Quantity 1 Description Motor Driver Value IC2-3 IC4 Tr.1 2 1 1 Level Shifter 3-Pin Regulator Clamping Circuit TSSOP16 SOT-223 PCP Tr.2 1 Bias of Hall sensors PCP ZD1 CONNECTOR1 CONNECTOR2 R1 1 1 1 1 5.6V Zener Diode Motor connection socket Motor connection socket LIM(pull up) NC R2 1 LIM(pull down) NC R3 1 Tr.1(pull up) R4 1 Tr.1(pull up) R5 1 Tr.1(pull down) R6 1 FG(pull up) SOD-523 2.54mm pitch 2.54mm pitch 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 2012 (0805Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 3225 (1210Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) R15 1 Hall bias R16 1 Hall bias R20-24 5 Hall IC application 160kΩ (0.1W) 5.1kΩ (0.1W) 33kΩ (0.1W) 10kΩ (0.1W) 0.51Ω (0.25W) 11kΩ (0.1W) 100kΩ (0.1W) 200Ω (0.1W) 51Ω (0.1W) 510Ω (0.5W) 100Ω (0.1W) 100Ω (0.1W) NC R25-27 3 Jumper NC R28-29 2 Jumper NC R30 1 S/S R31 1 LIM R32 1 CTL C1 1 HB Bypass Capacitor C2 1 VCC Bypass Capacitor 200Ω (0.1W) 100kΩ (0.1W) 27kΩ (0.1W) 0.1uF /50V 0.1uF /50V 47uF /50V 0.22uF /50V 56pF /50V 0.1uF /50V 0.047uF /50V 1500pF /50V 0.033uF /50V 1800pF /50V 4700pF /50V NC R7-9 3 RF R10 1 CT R11 1 CTL (pull down) R12 1 F/R R13 1 Hall bias R14 1 Hall bias C3 1 VCC Bypass Capacitor C4 1 VCC Bypass Capacitor C5 1 CT C6 1 VREG Bypass Capacitor C7 1 CSD C8 1 CP C9 1 VG C10 1 PWM C11-13 3 IN+ / - C14-16 3 IN+ / GND C17 1 CTL C18 1 LIM C19-22 4 C23-24 2 Daughter Board CON_A1, A2, B P1-4 1 VCC, VDD of MC14504BDT IN, OUT of NCV4264-2ST50T3G Interface board 3 4 Female Socket Terminal Pin 0.1uF /50V 0.1uF /50V 0.1uF /50V 0.1uF /50V Tolerance ±5％ ±5％ ±5％ ±5％ ±5％ ±5％ ±5％ ±5％ ±5％ ±5％ ±5％ ±5％ ±5％ ±5％ ±5％ ±10％ ±10％ Footprint SSOP44K ±20％ ±10％ ±5％ ±10％ ±10％ ±10％ ±10％ ±5％ ±10％ ±10％ ±10％ ±10％ ±10％ 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) 1608 (0603Inch) Manufacturer ON semiconductor (SANYO) ON semiconductor ON semiconductor ON semiconductor (SANYO) ON semiconductor (SANYO) ON semiconductor Phoenix Contact Phoenix Contact Manufacturer Part Number LV8121V Substitution Allowed No Lead Free Yes MC14504BDT NCV4264-2ST50T3G 2SC5964 No Yes Yes Yes Yes Yes 2SC5964 Yes Yes MM5Z5V6ST1G MPT 0,5/3-2,54 MPT 0,5/8-2,54 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes KOA RK73B1JTTD164J Yes Yes KOA RK73B1JTTD512J Yes Yes KOA RK73B1JTTD333J Yes Yes KOA RK73B1JTTD103J Yes Yes ROHM MCR10EZHJLR51 Yes Yes KOA RK73B1JTTD113J Yes Yes KOA RK73B1JTTD104J Yes Yes KOA RK73B1JTTD201J Yes Yes KOA RK73B1JTTD510J Yes Yes Panasonic ERJP14J511U Yes Yes KOA RK73B1JTTD101J Yes Yes KOA RK73B1JTTD101J Yes Yes Yes Yes Yes Yes Yes Yes KOA RK73B1JTTD201J Yes Yes KOA RK73B1JTTD104J Yes Yes KOA RK73B1JTTD273J Yes Yes MURATA GRM188R11H104KA93 Yes Yes MURATA GRM188R11H104KA93 Yes Yes SUN Electronic 50ME47HC Yes Yes MURATA GCM188R71H224KA49 Yes Yes MURATA GRM1882C1H560JA01 Yes Yes MURATA GRM188R11H104KA93 Yes Yes MURATA GRM188B11H473KA61 Yes Yes MURATA GRM188B11H152KA01 Yes Yes MURATA GRM188B11H333KA61 Yes Yes MURATA GRM1882C1H182JA01 Yes Yes MURATA GRM188B11H472KA01 Yes Yes Yes Yes MURATA GRM188R11H104KA93 Yes Yes MURATA GRM188R11H104KA93 Yes Yes MURATA GRM188R11H104KA93 Yes Yes MURATA GRM188R11H104KA93 Yes Yes No Yes Yes Yes Yes Yes ON semiconductor (SANYO) MAC8 MAC8 PM-61 ST-1-3 21/23 LV8121V Application Note Evaluation board circuit 22/23 LV8121V Application Note Pd max -- Ta Allowable power dissipation, Pd max - W 4.0 Mounted on the Evalution board: 90.0×90.0×1.6mm 3 glass epoxy (Exposed Die-Pad Soldered) 3.0 2.0 1.20 1.0 0 --30 0 30 60 90 120 Ambient temperature, Ta -- C Operation Guide ･Connect a Three-phase Brushless DC motor with MOTOR CONNECTOR1 and MOTOR CONNECTOR2. When we provide the Evaluation Board, it is mounted peripheral parts for Hall elements. If you drive the Brushless DC motor with Hall ICs, please remove Tr.2, R13-16, C11-13 and mount R20-27, C14-16. Refer to 19 page for details. When you control LV8121V by DSP, remove the Daughter Board and R32. Then, apply each signal to CTL, LIM, S/S, F/R terminal pads. ･Please start up the system along the following procedures. 1. Plug the USB cable into the Daughter Board. 2. Start GUI for LV8121. 3. Switch on the VCC power supply. Don’t apply the voltage before plugging the USB cable and starting GUI. 4. Input the drive signals of the motor with GUI. ･After switching off the VCC power supply, unplug the USB cable from the Daughter Board. ･Don’t exceed the absolute maximum ratings under no circumstances. ･When the motor speed is higher, the direction switching is dangerous. If the motor current after the direction switching exceeds the current limiter value, the upper side N-channel power FET will be turned off, but the lower side N-channel power FET will be the short brake condition. On the short brake condition, the current determined by the motor back EMF voltage and the coil resistance will flow. The current limiter of the IC cannot limit this current. Notes in design ･VCC2, RF, GND2 and each OUT are the large current lines. These lines should be layouted thick and short as possible. ･VCC bypass capacitor between VCC1 and GND1 should be mounted as near as possible to the IC. ･VREG bypass capacitor between VREG and GND1 should be mounted as near as possible to the IC. ･The metal of the IC’s backside is the Exposed Die-pad. The IC’s generation of heat can be efficiently diffused to a printed circuit board by soldering the Exposed Die-pad to the copper of the printed circuit board. The Exposed Die-pad should be connected to GND1 pin of the IC. ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 23/23