AMIS-4168x Fault Tolerant CAN Transceiver

AND8368/D
AMIS-4168x Fault Tolerant
CAN Transceiver
Start−up Behavior
Prepared by:
ON Semiconductor
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APPLICATION NOTE
Introduction
This document discusses the start−up behavior of AMIS−41682.
Schematic Diagram
Vbat
AMIS−41682
M30291FCTHP
1
P9_3
P9_2
P1_5/INT3
P3_0
P3_1
INH
BAT
TXD
GND
RXD CANL
ERRB CANH
STBB VCC
EN
RTL
WAKEB RTH
10 K
1K
100 nF
ACT45B−510−2P−TL003
560
560
+5V
PE9D1CAN
100 nF
68 pF
68 pF
Figure 1. Application Diagram CANLSFT
In Figure 1 the customer schematic diagram of the application is illustrated. The microcontroller is supplied from the same
5 V regulator. An internal POR keeps all I/O’s in tri−state (HiZ) during 32 ms. See also Figure 2.
Vbat
+5 V
POR
Figure 2. POR of the Microcontroller
© Semiconductor Components Industries, LLC, 2009
January, 2009 − Rev. 0
1
Publication Order Number:
AND8368/D
AND8368/D
Customer Observation
After start−up one would expect RXD = 1. This is based on the state diagram as illustrated in Figure 3.
Power−On Stand−by
STB
EN change state
EN
High Low
INH ERR RxD RTL
Act
POR− WU−
flag
int
Vbat
EN, STB change state
STB change state
Normal Mode
STB
EN
High High
STB change state
INH ERR RxD RTL
Act
Err−
flag
Rec.
out
Vcc
GoTo Sleep Mode
STB
EN
Low High
INH ERR RxD RTL
Act
2)
WU−
int
WU−
int
Vbat
Time−out GoToSleep mode
EN change state
EN, STB change state
Sleep Mode
Standby Mode
STB
EN
Low Low
STB
INH ERR RxD RTL
Act
WU−
int
WU−
int
Vbat
Local or Remote
Wake−up 3)
Power−On
1) Only when Vcc > POR_Vcc
2) INH active for a time = T_GoToSleep
3) Local Wake−upthrough pin Wake which change state
for a time > T_wake_min
Remote Wake−up through pin CANL or CANH when
dominant for a time >TCANH_min or TCANL_min
4) Mode Change through pins STB and EN is only
possible if Vcc > POR_Vcc
EN
INH ERR RxD RTL
Low Low
Hz
WU− WU−
int 1) int 1)
Vbat
Mode Change 4)
Figure 3. State Diagram Low Power Modes
Because both EN = 0 and STBB = 0 the IC will enter stand−by mode. The RXD pin will output the WU detector. Because
WAKEB is connected to Vbat (see Figure 1) and because there is no dominant state on the CAN−bus (see Figure 4) RXD is
expected to stay “1”.
+5 V
CANH
CANL
RXD
Figure 4. Expected Start−up Behavior
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AND8368/D
This expected behavior is only seen from time to time. In most cases the RXD stays low. This is illustrated in Figure 5. It
looks like RXD is starting up correctly, but turns to zero after about hundred microseconds. Figure 6 is a zoom in.
+5 V
CANH
CANL
RXD
Figure 5. Observed Start−up Behavior
Figure 6. Zoom In of Observed Start−up Behavior
Observations
CAN−bus in a permanent dominant state. This IC is
permanent supplied.
Used equipment:
• Oscilloscope type: Agillent Infiniium 600 MHz,
4 GSa/s
• Power supply: Thurlby Thandar Instruments
PL320QMD
Figure 7 illustrates the used measurement set−up.
Different switches allow isolation of the CAN−bus; to put
EN and STBB to ground, VCC or floating; to create a
wake−up and to switch on/off the power. A separate 5 V
regulator ensures that the +5 V is powered up synchronous
to Vbat. The left transceiver is the device under test (DUT).
The transceiver on the right is used as buskeeper to put the
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AND8368/D
DUT
10 nF
VCC
10
EN
6
RTL
STB
CANL
5
12
TxD
2
AMIS−4168x
CANH
INH
11
1
ERR
4
RTH 8
RxD
13
3
GND
WAKE
BUS KEEPER
Figure 7. Measurement Set−up
The oscilloscope plots are showing the signals measured on the different measurement points (MP).
Figure 8. Power− up using set−up in Figure 7. The CAN−bus is in a permanent
recessive state (CANL = VCC). RxD becomes high after power−up of VCC.
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4
10 kW
VBAT
14
97
10 kW
2x
100 pF
10 nF
100 kW
100 kW
100 kW
MP
33 kW
+5V
100 kW
220W
220W
10 nF
VCC INH VBAT WAKE
1
14
10
79
MP MP
RTL
EN
6
STB
12 CANL
5 AMIS−4168x
CANH
TxD 2
11
ERR 4
RxD
8 RTH
13
3
2x
GND
100 pF
10 kW
220W
10 kW
10 nF
220W
7805
MP
VBAT
1 kW
VBAT
AND8368/D
Figure 9. Power−up using set−up in Figure 7. Both STBB as EN are kept floating.
The internal pull down resistors are keeping both levels low, also, during the
rising edge of VCC. RxD becomes high after power−up of VCC.
2x
100 pF
DUT
10 nF
VCC
EN
10
6
STB
CANL
5
12
2 TxD
AMIS−4168x
CANH
11
1 INH
ERR
4
RTH
RxD
8
3
13
GND
BUS KEEPER
Figure 10. Measurement Set−up: Buskeeper in Stand−by State: EN = STBB = 0
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5
10 kW
10 nF
10 kW
2x
100 pF
33 kW
WAKE VBAT
14
97
RTL
100 kW
220W
220W
MP MP
220W
TxD
ERR
RxD
100 kW
MP
STB
100 kW
10 kW
EN
VCC INH VBAT WAKE
10 1
14
79
RTL
6
CANL
12
5
AMIS−4168x
CANH
11
2
4
8 RTH
3
13
GND
220W
MP
10 kW
10 nF
100 kW
10 nF
7805
+5V
VBAT
1 kW
VBAT
AND8368/D
Figure 11. Power−up using set−up in Figure 10. The CAN−bus is in a permanent
recessing state (CANL = VBAT) with the buskeeper in stand−by state.
RxD becomes high after power−up of VCC.
220 W
10 nF
VCC
EN
10
6
RTL 9
STB
CANL
5
12
2 TxD
AMIS−4168x
CANH
INH
11
1
ERR
4
RxD
8
13
3
RTH
GND
WAKE
VBAT
7
14
2x
100 pF
BUS KEEPER
DUT
Figure 12. Measurement set−up: buskeeper in normal mode:
EN = STBB = 1. For DUT EN = floating (internally pulled down) and STBB = 1.
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10 kW
2x
100 pF
100 kW
GND
10 nF
100 kW
100 kW
TxD
ERR
RxD
MP MP
33 k W
220W
STB
100 kW
10 kW
EN
220W
MP
VCC INH VBAT WAKE
1 14
7
10
9 RTL
6
220W
12 CANL
5 AMIS−4168x
CANH
11
2
4
RTH
8
3
13
10 kW
10 nF
+5V
10 kW
10 nF
7805
MP
VBAT
1 kW
VBAT
AND8368/D
Figure 13. Power−up using set−up in Figure 12. The CAN−bus is in a permanent recessive state
(CANL = VCC) with the buskeeper in normal mode.
STBB = 1 and EN is floating (pulled down internally). RxD becomes high after power−up of VCC.
CANL
220W
CANH
2x
100 pF
2x
100 pF
DUT
RTH
12
11
8
10 nF
VCC
EN
10
6
STB
5
TxD
AMIS−4168x 2
INH
1
ERR
4
13
3 RxD
GND
BUS KEEPER
Figure 14. Measurement set−up: CAN−bus is open.
Both EN = STBB = 0 (internally pulled down).
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10 kW
10 nF
10 kW
33 kW
WAKE VBAT
7
14
RTL 9
100 kW
220W
220W
MP MP
220W
VCC INH VBAT WAKE
10
14
79
1
RTL
EN
6
CANL
STB
12
5
AMIS−4168x
CANH
TxD 2
11
ERR
4
RxD
8 RTH
3
13
GND
100 kW
100 kW
10 kW
MP
10 kW
10 nF
+5V
100 kW
10 nF
7805
MP
VBAT
1 kW
VBAT
AND8368/D
Figure 15. Power−up using set−up in Figure 14. The CAN−bus is
open. RxD becomes high after power−up of VCC.
Proposed Start−up Procedure
Under very specific conditions (the individual power−on rise time and delay between Vcc and Vbat) the chance exists that
RxD stays 0 after start−up. This very specific condition is illustrated in Figure 16.
Figure 16. RxD stays low under specific
conditions for Vcc and Vbat rise times and delay.
By changing the power−on rise times and/or changing the
delay between Vbat and Vcc, it is possible to increase the
probability to have RxD = 1, but this probability can never
be guaranteed to be one.
For that reason ON Semiconductor advises to perform a
short initialization using the digital input pins STBB and EN
as described in Table 1. See also Figure 3.
Table 1. Initialization Sequence
State
STBB
EN
Duration
Start−up
X
X
−
Power−on
stand−by
1
0
6.4 ms
Normal mode
1
1
5.8 ms
GoTo sleep mode
0
1
Time out GoTo sleep
Sleep mode
0
1
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AND8368/D
This sequence guarantees 100 percent that RxD = 1. Measurements were done using the test set−up illustrated in Figure 17.
When the power is switched on the POR circuit is creating a “start−pulse” to the microcontroller triggering the sequence on
the STBB and EN pins:
VBAT
MP
47 W
10 nF
1 kW
7805
22 uF
MP
EN
MP
STB
ERR
100 kW
RxD
100 kW
MP
14
TxD 2
POR
Micro−
controller
1
WAKE
VBAT
6
AMIS−4168x
5
7
9
12
11
4
3
13
8
RTL
CANL
10 nF
MP
MP
220W
10
10 kW
INH
CANH
RTH
220W
VCC
GND
2x
100 pF
DUT
Figure 17. Measurement Set−up to Check the Initialization
Figure 18. Start−up Behavior using the Proposed Sequence from Table 1
In Figure 18 the behavior is shown. Vcc comes up with a rise−time of about 600 ms. After a POR delay of 13 ms STBB and
EN are toggled. In return RxD switches high.
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AND8368/D
Figure 19 shows the influence on the CANL line.
Figure 19. Start−up behavior using the proposed sequence
from Table 1. Influence on the CANL line.
Figure 20. Zoomed in View of Figure 19
Because we enter the normal mode for 5.8 ms, CANL is
pulled−up via RTL to Vcc for a very short while: 9.6 ms. This
is about 1.2 Tbit (for baudrate = 125 kbit/s).
This short change in termination voltage level does not
influence the communication on the bus because it stays a
clean recessive level. (The CANL level is under all
conditions above the maximum receiver threshold level =
3.4 V).
To evaluate this, the buskeeper is (re)connected to the
CAN bus. (See Figures 10 and 12). With the buskeeper in
stand−by mode, RxD_buskeeper is monitored. As shown in
Figure 21 no effect is observed. The CAN bus stays in
recessive state and no wake−up is possible.
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AND8368/D
Figure 21. Buskeeper in stand−by mode. CANL termination
switched from Vbat to Vcc for a short while (1.2 Tbits).
No influence seen on RxD_buskeeper.
With the buskeeper in normal mode the bus will be terminated to Vcc and ground (respectively for CANL and CANH). As
a result the short “change” in bus termination voltage will even not be observable. Also in this case RxD_buskeeper is
monitored. As shown in Figure 22 no effect is observed. The CAN bus stays in recessive state and RxD_buskeeper is kept high.
Figure 22. Buskeeper in normal mode. CANL termination switched to
Vcc. No influence seen on CANL and on RxD_buskeeper.
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AND8368/D
Figures 23 and 24 are showing the influence on both CANL as CANH in a zoomed in and zoomed out time−scale. As can
be seen the short change in CANL termination is hardly detectable on the oscilloscope (only in glitch mode), and for long
time−base settings it can’t be even observed.
Figure 23. CANL termination switched from Vbat to Vcc for a short while (1.2 Tbit).
No influence seen CANH. RxD switches high after the POR time−out.
Figure 24. The CANL termination switched from Vbat
to Vcc is not observable on a bigger time scale.
Conclusion
The side effect of this sequence is that the transceiver
enters Normal Mode for a few micro−seconds. This results
in a short change in termination of the CANL line from Vbat
to Vcc. The duration of this change in termination is about
1.2 Tbit for a given baud−rate = 125 kbit/s.
There is no effect on communication because the CANL
level always stays above the receiver dominant threshold.
Under very specific conditions of power−on rise time and
delay between Vbat and Vcc, it is possible that RxD stays 0
after start−up.
To guarantee that always RxD = 1 after start−up, it is
advised to run a short sequence using the digital input pins
STBB and EN.
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AND8368/D
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