dm00077598

AN4259
Application note
STEVAL-ISA117V1: 12 V/4.2 W, 60 kHz flyback isolated with
VIPer16LN
By Mirko Sciortino
Introduction
This document describes a 12 V - 350 mA power supply set in isolated flyback topology with
VIPER16, a new off-line high voltage converter by STMicroelectronics.
The features of the device are:
– 800 V avalanche rugged power section
– PWM operation at 60 kHz with frequency jittering for lower EMI
– current limiting with adjustable set point
– on-board soft-start
– safe auto-restart after a fault condition (overload, short-circuit)
– low standby power consumption
The VIPER16 does not require a biasing circuit to operate because the IC can be supplied
by an internal current generator, therefore saving the cost of the transformers auxiliary
winding. If the device is biased through an auxiliary winding, the evaluation board can reach
very low standby consumption (< 30 mW at 230 VAC, with output load disconnected).
Both cases are treated in the present document. The available protections are: thermal
shutdown with hysteresis, delayed overload protection, open loop failure protection (the last
one available only if VIPER16 is biased through the auxiliary winding).
Figure 1. Evaluation board
May 2016
DocID024274 Rev 2
1/33
www.st.com
Contents
AN4259
Contents
1
Adapter features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Testing the board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
6
4.1
Typical waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2
Precision of the regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
Burst mode and output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5
Light load performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1
Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2
Overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3
Feedback loop failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Feedback loop calculation guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
Transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2
Compensation procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Thermal measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8
EMI measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9
Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Appendix A Test equipment and measurement of efficiency
and light load performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
A.1
2/33
Measuring input power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DocID024274 Rev 2
AN4259
Contents
11
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DocID024274 Rev 2
3/33
Adapter features
1
AN4259
Adapter features
The electrical specifications of the evaluation board are listed in Table 1.
Table 1. Electrical specification
4/33
Parameter
Symbol
Value
Input voltage range
VIN
[90 VAC; 265 VAC]
Output voltage
VOUT
12 V
Max output current
IOUT
0.35 A
Precision of output regulation
∆VOUT_LF
± 5%
High frequency output voltage ripple
∆VOUT_HF
50 mV
Max ambient operating temperature
TAMB
60 °C
DocID024274 Rev 2
AN4259
2
Circuit description
Circuit description
The power supply is set in flyback topology. The schematic is given in Figure 5 and the bill of
materials in Table 2. The input section includes a resistor R1 for inrush current limiting, a
diode bridge (D0) and a Pi filter for EMC suppression (C1, L1, C2). The transformers core is
a standard E16. A transil clamp network (D1, D5) is used for leakage inductance
demagnetization.
The output voltage value is set through the voltage reference IC2 and the voltage divider
from the output, made up of R11 and R12, each of them split into two in order to allow a
better tuning of the output voltage value. The FB pin of the VIPER16 is shorted to GND,
which disables the internal error amplifier. In this case, a 15 kΩ internal resistor is connected
between an internal 3.3 V generator and the COMP pin, as shown in Figure 2. The feedback
signal is transferred to the primary side through an optocoupler, connected in parallel with
the compensation network to COMP pin. The optocoupler modulates the voltage of the pin
(and so the primary peak current) according to the current sunk, thus setting the right drain
peak current value to keep the output voltage regulated.
Figure 2. FB and COMP pins internal structure
3.3V
Burst Mode Ref
Disabled
FB
PWM STOP
+
15K
-
VBU
E\A
From SenseFET
+
+
3.3V
nR
To PWM latch
R
COMP
AM17447v1
The LIM pin has been left open, thus the current limitation is set to the default value, IDLIM. If
a lower value is required, a resistor of the right value should be connected between LIM and
GND pins, according to the IDLIM vs RLIM graphic reported in the datasheet. In this
evaluation board, RLIM = R4.
A 100 nF capacitor has been placed very close to the output connector solder points, to limit
the spike amplitude.
At power-up, as the rectified input voltage rises over the VDRAINSTART threshold, the high
voltage current generator starts charging the VDD capacitor, C4, from 0 V up to VDDON. At
this point the power MOSFET starts switching, the HV current generator is turned off and
the IC is biased by the energy stored in C4.
If the jumper J is not selected, the VIPER16 is self-biased, i.e. supplied by the input line
voltage through the internal high-voltage startup current generator, which is turned on as the
VDD voltage falls down to VDDCSON and is switched off as it reaches VDDON (see Figure 3).
The use of self-biasing means higher power dissipation and must be avoided if low standby
consumption is required.
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5/33
Circuit description
AN4259
If the jumper J is selected, the IC is biased by the auxiliary winding, through D3 and L3, (see
Figure 4). The IC biasing through auxiliary winding is referred to as external biasing and
allows the converter to reach very low input power consumption in no load condition.
The auxiliary winding voltage, and then the VDD voltage, increases with the output load. In
order to avoid that the VDD operating range is exceeded, an external clamp (Dz and Rz) has
been added between VDD and GND pins.
Figure 3. VDD waveform (IC self-biased)
6/33
Figure 4. VDD waveform (IC externally biased)
DocID024274 Rev 2
AC IN
AC IN
-
R1
D0
+
C1
+
L1
C2
+
DocID024274 Rev 2
Dz
Rz
C4
+
C5
J
C8
COMP
FB
IC1
LIM
R4
CONTROL
VDD
L3
D3
GND
DRAIN
R5
D1
C3
2
4
1
5
C12
T1
8
D2
7
+
C9
IC2
IC3
R8
L2
R10
R9
C10
+
C11
C13
R12b
R12a
R11b
R11a
-
Vout
AN4259
Circuit description
Figure 5. Application schematic
AM17450v1
7/33
Circuit description
AN4259
Table 2. Bill of material
Ref.
Part
Description
Manufacturer
D0
DF06M
Diode bridge
Vishay
C1, C2
4.7µF, 400 V
Electrolytic capacitor, NHG series
Panasonic
C3
not mounted
C4
10 µF, 35 V
Electrolytic capacitor, G series
Panasonic
C5
100 nF, 50 V
Ceramic capacitor, SR series
AVX
C8
3.3 nF, 100 V
Ceramic capacitor
C9
470 µF, 25 V
Ultra-low ESR electrol. cap., ZL series
C10
not mounted
Electrolytic capacitor
C11
33 nF, 50 V
Ceramic capacitor B3798X series
EPCOS
C12
2.2 nF
Y1 capacitor 440L series
Vishay
C13
100 nF, 50 V
Ceramic capacitor, SR series
AVX
D1
not mounted
Clamp diode
D2
STPS2H100
Output diode 2 A, 100 V
ST
D3
BAT46
Small signal diode
ST
Dz
18 V
Zener diode
Rz
6.8 kΩ
1/4 W resistor
R1
4.7 Ω
1 W resistor
R4
not mounted
1/4 W resistor
R5
not mounted
1/2 W resistor
R8
8.2 kΩ
1/4 W resistor
R9
15 kΩ
1/4 W resistor
R10
680 kΩ
1/4 W resistor
R11a
120 kΩ
1/4 W resistor
R11b
27 kΩ
1/4 W resistor
R12a
15 kΩ
1/4 W resistor
R12b
1.8 kΩ
1/4 W resistor
IC1
Viper16L
PMW controller
ST
IC2
TS431
Voltage reference
ST
IC3
PC817
Optocoupler
L1
1 mH
Filter inductor BC type
L2
short circuit
L3
1 µH
8/33
EPCOS
Magnetica
Flyback transformer
7508110342 Rev. 6A
J
Tyco electronics
Small signal inductor
1335.0062
T1
Rubycon
Wurth
Jumper
DocID024274 Rev 2
AN4259
3
Transformer
Transformer
The transformer characteristics are listed in the table below.
Table 3. Transformer characteristics
Parameter
Value
Test conditions
Manufacturer
Magnetica
Part number
1335.0062
Primary inductance
1.2 mH ±15
Measured at 1 kHz 0.1V
Leakage inductance
2.9%
Measured at 10 kHz 0.1V
Primary to secondary turn radio (4 - 5)/(7 - 8)
7.85 ±0.5
Measured at 10 kHz 0.1V
Primary to auxiliary turn radio (4 - 5)/(1 - 2)
7.33 ±0.5
Measured at 10 kHz 0.1V
The following figures show size and pins distances ([mm]) of the transformer.
Figure 6. Transformer pins distances
Figure 7. Transformer electrical diagram
Figure 8. Transformer side view
Figure 9. Transformer terminal view
DocID024274 Rev 2
9/33
Testing the board
4
Testing the board
4.1
Typical waveforms
AN4259
Drain voltage and current waveforms in full load condition are reported for the two nominal
input voltages in Figure 10 and Figure 11, and for minimum and maximum input voltage in
Figure 12 and Figure 13 respectively.
Figure 10. Drain current and voltage at 115 VAC, Figure 11. Drain current and voltage at 230 VAC,
max load
max load
Figure 12. Drain current and voltage at 90 VAC, Figure 13. Drain current and voltage at 265 VAC,
max load
max load
4.2
Precision of the regulation
The output voltage of the board has been measured in different line and load condition with
the results shown in Output voltage line-load regulation Table 4. The output voltage
practically is not affected by the line condition and by the IC biasing (self or external
biasing).
10/33
DocID024274 Rev 2
AN4259
Testing the board
Table 4. Output voltage line-load regulation
VOUT (V)
VIN (VAC)
No load
50% Load
75% Load
100% Load
Self
biasing
External
biasing
Self
biasing
External
biasing
Self
biasing
External
biasing
Self
biasing
External
biasing
90
12.12
12.12
12.06
12.06
12.05
12.05
12.05
12.04
115
12.12
12.12
12.08
12.06
12.05
12.04
12.05
12.04
150
12.12
12.12
12.08
12.06
12.06
12.04
12.04
12.04
180
12.12
12.12
12.06
12.05
12.05
12.04
12.04
12.04
230
12.12
12.12
12.06
12.05
12.05
12.04
12.04
12.03
265
12.12
12.12
12.06
12.05
12.05
12.04
12.04
12.03
Figure 14. Line regulation
12.3
12.2
VOUT [V]
0
25%
12.1
50%
75%
100%
12
11.9
80
105
130
155 180
VIN [V AC ]
DocID024274 Rev 2
205
230
255
AM17459v1
11/33
Testing the board
AN4259
Figure 15. Load regulation
12.3
VOUT [V]
12.2
90
115
12.1
230
265
12
11.9
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
IOUT [A]
AM17460v1
Figure 16. Output voltage ripple at 115 VAC full Figure 17. Output voltage ripple at 230 VAC, full
load
load
12/33
DocID024274 Rev 2
AN4259
4.3
Testing the board
Burst mode and output voltage ripple
When the converter is lightly loaded, the COMP pin voltage decreases. As it reaches the
shutdown threshold, VCOMPL (1.1 V, typical), the switching is disabled and no more energy
is transferred to the secondary side. So, the output voltage decreases and the regulation
loop makes the COMP pin voltage increase again. As it rises 40 mV above the VCOMPL
threshold, the normal switching operation is resumed. This results in a controlled on/off
operation which is referred to as “burst mode”. This mode of operation keeps the frequencyrelated losses low when the load is very light or disconnected, making it easier to comply
with energy saving regulations. The figures below show the output voltage ripple when the
converter is no/lightly loaded and supplied with 115 VAC and 230 VAC respectively.
Figure 18. Output voltage ripple at 115 VAC,
no load
Figure 19. Output voltage ripple at 230 VAC,
no load
Figure 20. Output voltage ripple at 115 VAC,
IOUT = 25 mA
Figure 21. Output voltage ripple at 230 VAC,
IOUT = 25 mA
DocID024274 Rev 2
13/33
Testing the board
4.4
AN4259
Efficiency
The active mode efficiency is defined as the average of the efficiencies measured at 25%,
50%, 75% and 100% of maximum load, at nominal input voltage (VIN = 115 VAC and
VIN = 230 VAC). External power supplies (the power supplies which are contained in a
separate housing from the end-use devices they are powering) need to comply with the
code of conduct (version 4) “active mode efficiency” criterion, which states an active mode
efficiency higher than 71.18% for a power throughput of 4.2 W.
Another standard to be applied to external power supplies in the coming years is the DOE
(department of energy) recommendation, whose active mode efficiency requirement for the
same power throughput is 76.6%.
If the IC is externally biased, the presented evaluation board is compliant with both
standards, as can be seen from Figure 22 where the average efficiencies of the board at
115 VAC (79.7%) and at 230 VAC (77.1%) are plotted with dotted lines, together with the
above limits. In the same figure the efficiency at 25%, 50%, 75% and 100% of output load
for both input voltages is also shown.
Figure 22. Active mode efficiency and comparison with energy efficiency standards
(IC externally biased)
81
79
77
DOE limit
eff [%]
75
73
71
CoC 4 limit
69
67
115
230
av @ 115Vac
av @ 230Vac
65
0.2
4.5
0.4
0.6
0.8
Iout [% IOUT ]
1
G1709DI1222
Light load performance
The input power of the converter has been measured in no load condition for different input
voltages and the results are reported in Table 5.
14/33
DocID024274 Rev 2
AN4259
Testing the board
Table 5. No load input power
PIN (mW)
VIN (VAC)
Self biasing
External biasing
90
16.8
74.3
115
18.4
93
150
20.7
121
180
21.9
144
230
23
185
265
27
215
In version 4 of the code of conduct, also the power consumption of the power supply when it
is no loaded is considered. The criteria to be compliant with are reported in Table 6 below:
Table 6. No load input power
Nameplate output power (Pno)
Maximum power in no load for AC-DC EPS
0 to ≤ 50 W
< 0.3 W
> 50 W < 250 W
< 0.5 W
Considering only the case of external biasing (by auxiliary winding), the power consumption
of the presented board is more than ten times lower than the code of conduct, version 4
limit. Even if this performance seems to be disproportionately better than the requirements,
it is worth noting that often AC-DC adapter or battery charger manufacturers have very strict
requirement about no load consumption and when the converter is used as an auxiliary
power supply, the line filter is often the main line filter of the entire power supply that
considerably increases standby consumption.
Even if the code of conduct, version 4 program does not have other requirements regarding
light load performance, in order to give more information the consumption of the evaluation
board in two other light load cases (POUT = 25 mW and POUT = 50 mW) has also been
measured. The results versus line voltage are plotted in the figure below, together with the
no load measurements reported in Table 5.
DocID024274 Rev 2
15/33
Testing the board
AN4259
Figure 23. PIN vs. VIN @ POUT = 0; 25 mW;
50 mW, IC externally biased
Figure 24. PIN vs VIN @ POUT = 0; 25 mW;
50 mW, IC self biased
250
350
0
200
25mW
25mW
50mW
250
50mW
150
PIN [mW]
PIN [mW]
0
300
100
200
150
100
50
50
0
80
105
130
155
180
205
230
VIN [VAC]
0
255
80
105
130
AM17468v1
155
180 205
VIN [VAC]
230
255
AM17469v1
Depending on the equipment supplied, it is possible to have several criteria to measure the
performance of a converter. One criterion is the measure of the output power (or the
efficiency) when the input power is equal to one watt. This measurement is shown in
Figure 25 and Figure 26 for different input voltage values.
Figure 26. Efficiency @ PIN = 1 W, IC self biased
80
80
75
75
70
70
65
65
eff [%]
eff [%]
Figure 25. Efficiency @ PIN = 1 W, IC external
biased
60
60
55
55
50
50
45
45
40
40
80
110
140
170
200
VIN [V AC ]
230
260
80
AM17470v1
110
140
170
200
VIN [V AC ]
230
260
AM17471v1
Another requirement for light load performance (EuP lot 6) is that the input power should be
less than 500 mW when the converter is loaded with 250 mW. When the IC is externally
biased, the evaluation board can satisfy even this requirement, as shown in Figure 27. In
Figure 28 the performance with IC self supplied is shown.
16/33
DocID024274 Rev 2
AN4259
Testing the board
Figure 27. PIN @ POUT = 0.25 W, IC externally
biased
Figure 28. PIN @ POUT = 0.25 W, IC self biased
0.8
0.5
0.75
0.7
0.4
PIN [W]
PIN [W]
0.45
0.35
0.65
0.6
0.55
0.5
0.3
0.45
0.4
0.25
80
110
140
170
200
VIN [V AC ]
230
260
80
AM17472v1
DocID024274 Rev 2
110
140
170
200
VIN [V AC ]
230
260
AM17473v1
17/33
Functional check
5
Functional check
5.1
Soft start
AN4259
At startup the current limitation value reaches IDLIM after an internally fixed time, tSS, whose
typical value is 8.5 msec. This time is divided into 16 time intervals, each corresponding to a
current limitation step progressively increasing. In this way the drain current is limited during
the output voltage increase, therefore reducing the stress on the secondary diode.
The soft start phase is shown in Figure 29 and Figure 30.
Figure 29. Soft start @ startup
5.2
Figure 30. Soft start @ startup (zoom)
Overload protection
In case of over load or short circuit (see Figure 31), the drain current reaches the IDLIM value
(or the one set by the user through the RLIM resistor). In every cycle where this condition is
met, a counter is incremented; if it is maintained continuously for the time tOVL (50 msec
typical, internally fixed), the overload protection is tripped, the power section is turned off
and the converter is disabled for a tRESTART time (1 sec typical). After this time has elapsed,
the IC resumes switching and, if the short is still present, the protection occurs indefinitely in
the same way (Figure 32). This ensures restart attempts of the converter with low repetition
rate, so that it works safely with extremely low power throughput and avoids the IC
overheating in case of repeated overload events.
Furthermore, every time the protection is tripped, the internal soft startup function is invoked
(Figure 33), in order to reduce the stress on the secondary diode.
After the short removal, the IC resumes normal working. If the short is removed during tSS or
tOVL, i.e. before the protection tripping, the counter is decremented on a cycle-by-cycle
basis down to zero and the protection is not tripped.
If the short-circuit is removed during tRESTART, the IC must wait for the tRESTART period to
elapse before switching is resumed (Figure 34).
18/33
DocID024274 Rev 2
AN4259
Functional check
Figure 31. Output short-circuit applied: OLP
tripping
Figure 32. Output short circuit maintained: OLP
steady- state
Figure 33. Output short circuit maintained: OLP
steady-state (zoom)
Figure 34. Output short-circuit removal and
converter restart
5.3
Feedback loop failure protection
This protection is available only if the IC is not self-biased. As the loop is broken (R12
shorted or R11 open), the output voltage VOUT increases and the VIPER16 runs at its
maximum current limitation. The VDD pin voltage increases as well, because it is linked to
the VOUT through the auxiliary winding.
If the VDD voltage reaches the VDD clamp threshold (23.5 V min.) in less than 50 msec, the
IC is shut down by open loop failure protection (see Figure 35 and Figure 36), otherwise by
OLP, as described in the previous section. The breaking of the loop has been simulated by
shorting the low side resistor of the output voltage divider, R12 = R12a+R12b. The same
behavior can be induced opening the high side resistor, R11 = R11a+R11b.
The protection acts in auto-restart mode with tRESTART = 1sec (Figure 36). As the fault is
removed, normal operation is restored after the last tRESTART interval has been completed
(Figure 38).
DocID024274 Rev 2
19/33
Functional check
AN4259
Figure 35. Feedback loop failure protection:
tripping
Figure 36. Feedback loop failure protection:
steady-state
Figure 37. Feedback loop failure protection:
steady state (zoom)
Figure 38. Feedback loop failure protection:
restore of normal operation after fault removal
20/33
DocID024274 Rev 2
AN4259
Feedback loop calculation guidelines
6
Feedback loop calculation guidelines
6.1
Transfer function
The set PWM modulator + power stage is indicated with G1(f), while C(f) is the “controller”,
i.e. the network which is in charge to ensure the stability of the system.
Figure 39. Control loop block diagram
∆Vo
∆Ipk
∆Ipk
G1(f)
∆Vo
∆Ipk
∆VCOMP
C(f)
1/HCOMP
∆VCOMP
∆Vo
AM17474v1
The mathematical expression of the power plant G1(f) is the following:
Equation 1
j ⋅ 2 ⋅π ⋅ f
j⋅ f
VOUT ⋅ (1 +
)
VOUT ⋅ (1 +
)
∆VOUT
z
fz
=
G 1 (f) =
=
j⋅ 2 ⋅π ⋅ f
j⋅ f
∆I pk
Ipkp ( fsw, Vdc ) ⋅ (1 +
) Ipkp ( fsw, Vdc ) ⋅ (1 +
)
p
fp
where, considering the schematic of Figure 5.:
Equation 2
fp =
1
π ⋅ C 9·(R OUT + 2ESR)
is the pole due to the output load (ROUT = VOUT/IOUT) and
Equation 3
fz =
1
2 ⋅ π ⋅ C 9·ESR
is the zero due to the ESR of the output capacitor C9. The mathematical expression of the
compensator C(f) is:
DocID024274 Rev 2
21/33
Feedback loop calculation guidelines
AN4259
Equation 4
f⋅j
C0
fZc
C( f ) =
=
⋅
∆Vo HCOMP

f ⋅ j
2 ⋅ π ⋅ f ⋅ j ⋅ 1 +

fPc 

1+
∆I pk
where:
Equation 5
C0 =
RCOMP ⋅ CTR
R11 ⋅ R8 ⋅ C11
Equation 6
1
2 ⋅ π ⋅ (R10 + R11) ⋅ C11
fZc =
Equation 7
fPc =
1
2 ⋅ π ⋅ RCOMP ⋅ C 8
will be chosen in order to censure the stability of the overall system.
In the formulas above, HCOMP = 7Ω is the ∆VCOMP to ∆IDRAIN ratio of VIPER16,
RCOMP = 15 kΩ is the dynamic resistance of the COMP pin, CTR is the current transfer ratio
of the optocoupler.
6.2
Compensation procedure
The first step is to choose the pole and zero of the compensator and the crossing frequency,
for instance:
fZc = fp/2
fPc = fz
fcross = 4kHz ≤ fsw/10
G1(cross) can be calculated from equation (1) and, since by definition
it is ǀ C(fcross)*G1(fcross) ǀ = 1, C0 can be calculated as follows:
Equation 8
2 ⋅ π ⋅ fcross ⋅ j ⋅ 1 +
C0 =
1+
fcross ⋅ j
fPc
fcross ⋅ j
fZc
⋅
Hcomp
G1( fcross)
At this point the bode diagram of G1(f)*C(f) can be plotted, in order to check the phase
margin for the stability.
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Feedback loop calculation guidelines
If the margin is not high enough, another choice should be done for fZc, fPc and fcross, and
the procedure repeated.
When the stability is ensured, the next step is to find the values of the schematic
components, which can be calculated, using the above formulas, as follows:
Equation 9
R11
R12 =
VOUT
−1
VREF
Equation 10
C11 =
RCOMP ⋅ CTR
R11 ⋅ R8 ⋅ C 0
Equation 11
R10 =
1
− R11
2π ⋅ C11 ⋅ fZc
Equation 12
C8 =
1
2 ⋅ π ⋅ fPc ⋅ RCOMP
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Thermal measurements
7
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Thermal measurements
A thermal analysis of the board has been performed using an IR camera for 115 VAC and
230 VAC mains input, full load condition, both with IC externally biased and self biased. The
results are shown in Figure 40, 41, 42 and 43.
When the IC is self biased its temperature is higher, due to the power dissipated by the HVstartup generator.
Figure 40. Thermal measurements at 90VAC, full load, IC externally biased
Figure 41. Thermal measurements at 115VAC, full load, IC externally biased
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Thermal measurements
Figure 42. Thermal measurements at 230VAC, full load, IC externally biased
Figure 43. Thermal measurements at 265VAC, full load, IC externally biased
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EMI measurements
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EMI measurements
A pre-compliant tests to EN55022 (Class B) European normative has been performed using
an EMC analyzer and a LISN.
The average EMC measurements at 115 VAC/full load and 230 VAC/full load have been
performed and the results are shown in Figure 44 and Figure 45 respectively.
Figure 44. Average measurement at VIN = 115 VAC, full load
Figure 45. Average measurement at VIN = 230 VAC, full load
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Board layout
Board layout
Figure 46. Bottom layer
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Conclusion
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Conclusion
The VIPER16 allows a non-isolated converter to be designed in a simple way and with few
external components. In this document a isolated flyback has been described and
characterized. Special attention has been given to light load performance, confirmed as very
good by bench analysis. The efficiency performance has been compared to the
requirements of the Code of Conduct (version 4) for an external AC-DC adapter with very
good results.
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Test equipment and measurement of efficiency and light load performance
Appendix A
Test equipment and measurement of
efficiency and light load performance
The converter input power has been measured using a wattmeter. The wattmeter measures
simultaneously the converter input current (using its internal ammeter) and voltage (using its
internal voltmeter). The wattmeter is a digital instrument so it samples the current and
voltage and converts them to digital forms. The digital samples are then multiplied giving the
instantaneous measured power. The sampling frequency is in the range of 20 kHz (or higher
depending on the instrument used). The display provides the average measured power,
averaging the instantaneous measured power in a short period of time (1 sec typ.).
Figure 47 shows how the wattmeter is connected to the UUT (unit under test) and to the AC
source and the wattmeter internal block diagram.
Figure 47. Connections of the UUT to the wattmeter for power measurements
An electronic load has been connected to the output of the power converter (UUT), allowing
the converter load current to be set and measured, while the output voltage has been
measured by a voltmeter. The output power is the product between load current and output
voltage. The ratio between the output power, calculated as previously stated, and the input
power, measured by the wattmeter, is the converter's efficiency, which has been measured
in different input/output conditions.
A.1
Measuring input power
With reference to Figure 47, the UUT input current causes a voltage drop across the
ammeter's internal shunt resistance (the ammeter is not ideal so it has an internal resistance
higher than zero) and across the cables connecting the wattmeter to the UUT.
If the switch of Figure 47 is in position 1 (see also the simplified scheme of Figure 48), this
voltage drop causes an input measured voltage higher than the input voltage at the UUT
input that, of course, affects the measured power. The voltage drop is generally negligible if
the UUT input current is low (for example when we are measuring the input power of UUT in
light load condition).
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Test equipment and measurement of efficiency and light load performance
AN4259
Figure 48. Connections of the UUT to the wattmeter for power measurements
In the case of high UUT input current (i.e. for measurements in heavy load conditions), the
voltage drop can be relevant compared to the UUT real input voltage. If this is the case, the
switch in Figure 47 can be changed to position 2 (see simplified scheme of Figure 49) where
the UUT input voltage is measured directly at the UUT input terminal and the input current
does not affect the measured input voltage.
Figure 49. Switch in position 2 - setting for efficiency measurements
On the other hand, the position of Figure 49 may introduce a relevant error during light load
measurements, when the UUT input current is low and the leakage current inside the
voltmeter itself (which is not an ideal instrument and doesn't have infinite input resistance) is
not negligible. This is the reason why it is better to use the setting of Figure 48 for light load
measurements and Figure 49 for heavy load measurements. If it is not clear which
measurement scheme has the lesser effect on the result, try with both and register the lower
input power value. As noted in IEC 62301, instantaneous measurements are appropriate
when power readings are stable. The UUT is operated at 100% of nameplate output current
output for at least 30 minutes (warm up period) immediately prior to conducting efficiency
measurements. After this warm-up period, the AC input power is monitored for a period of 5
minutes to assess the stability of the UUT. If the power level does not drift by more than 5%
from the maximum value observed, the UUT can be considered stable and the
measurements can be recorded at the end of the 5-minute period. If AC input power is not
stable over a 5-minute period, the average power or accumulated energy is measured over
time for both AC input and DC output. Some wattmeter models allow integration of the
measured input power in a time range and then measure the energy absorbed by the UUT
during the integration time. The average input power is calculated dividing by the integration
time itself.
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References
References
•
Code of Conduct on Energy Efficiency of External Power Supplies, Version 4
•
VIPER16 datasheet
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Revision history
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Revision history
Table 7. Document revision history
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Date
Revision
Changes
29-May-2015
1
Initial release.
19-May-2016
2
Added: new T1 part 7508110342 Rev 6A in Table 2.
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