Microsemi Corporation
SoC Products Reliability Report
RT0001 Report - Revision 13
December 2015
Accelerated Reliability Testing
The failure rate of semiconductor devices is inherently small. For this reason, the Microsemi®
System-on-Chip Products Group (Microsemi SoC, formerly known as Actel Corporation) uses accelerated
testing to assess reliability of its devices. Overstresses are used to produce the same failure mechanisms
that would be seen under normal conditions but in a much shorter period of time. Acceleration factors are
used by Microsemi SoC to estimate failure rates based on the results of accelerated testing. The objective
of this testing is to identify the failure mechanisms and eliminate them as a cause of failure during the
useful life of Microsemi SoC (formerly Actel) products.
Die selection is determined by both the largest die size and/or the currently available die. Microsemi SoC
will, whenever possible, test the largest die in a given family. Package selection for the testing is
determined by test board availability and will not always include the largest package available. The primary
use of this report is to include the reliability data of the silicon devices.
Standard FIT Rate and MTTF Assumptions
All of the FIT (Failure in Time) rates and MTTF (Mean Time to Failure) numbers reported here use a base
set of assumptions. FIT rate is calculated using JESD85 (Methods for Calculating Failure Rates in Units of
FITs) standard. The failure rate is calculated using Chi-square distribution at 60% confidence interval from
the small number of failures and limited sample size of the population tested. The Chi-squared value is
calculated from the inverse Chi-squared distribution using the desired probability level and degrees of
freedom. The failure rate is then calculated from the Chi-square value:
2
9
10
Failure Rate = ------------------------------------------------------------2 A.F. Device Hours
EQ 1
2
Where = Chi-Squared value at 60% confidence level and (2f + 2) degrees of freedom, where f is the
number of failures, Device Hours = (No. of Devices) × (No. of Hours)
The Acceleration Factor (A.F.) is calculated using the Arrhenius relationship.
Acceleration Factor = Exp {(Ea/k) × (1/Tuse – 1/Tstess)}
EQ 2
Where:
Ea = Activation Energy (eV), assumed 0.7 eV
k = Boltzmann’s constant (8.617 × 10–5 eV/ºK)
Tstress = Temperature at accelerated conditions in degrees Kelvin (°K = 125°C + 273.16)
Tuse = Temperature at normal use conditions in degrees Kelvin (°K = 55°C + 273.16)
A.F. = Acceleration Factor
Assuming that the actual usage voltage is within the rated specification, acceleration coefficients are
calculated for temperature stress. Sample sizes, total devices tested, device hours, and failures can be
found in the data tables for each product family. The Arrhenius Life-Temperature relationship is widely
used to model product life as a function of temperature. This relationship is used to express both a single
failure mechanism's sensitivity to temperature and the product thermal acceleration factor.
General Note: Notes at the end of each table correspond to the numbers or asterisk indicated by the
superscript in the product column of that table. If there is only one note, an asterisk is used. Failures
indicated in parentheses represent false failures due to ESD or EOS.
2
SoC Reliability Report
Table of Contents
Accelerated Reliability Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Standard FIT Rate and MTTF Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Reliability Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Group E Inspection—Generic Data (Radiation Hardness) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.0 µm FPGA Reliability Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.0 µm FPGA (RH) Reliability Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
0.8 µm FPGA (RH) Reliability Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
0.8 µm FPGA Reliability Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
0.6 µm FPGA Reliability Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
0.6 µm RTSX FPGA Reliability Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
0.45 µm CSM FPGA Reliability Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
0.45 µm UMC FPGA Reliability Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
0.35 µm FPGA Reliability Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
0.25 µm MEC FPGA Reliability Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
0.25 µm Flash FPGA Reliability Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
0.25 µm UMC FPGA Reliability Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Antifuse Reliability Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Antifuse FIT Rate Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Reliability Summary – Silicon Sculptor Programming Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
0.22 µm UMC FPGA Reliability Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
0.22 µm UMC Flash FPGA Reliability Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
0.15 µm UMC FPGA Reliability Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Reliability Summary – Silicon Sculptor Programming Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
0.13 µm Infineon Flash FPGA Reliability Summary
(ProASIC3 – A3P)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
0.13 µm Infineon Flash FPGA Reliability Summary
(Fusion – AFS)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
0.13 µm Infineon Flash FPGA Reliability Summary
(SmartFusion – A2F)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
0.13 µm UMC Flash FPGA Reliability Summary
(IGLOO – AGL/AGLE; IGLOO PLUS – AGLP; IGLOO nano – AGLN)
. . . . . . . . . . . . . . . . 68
0.13 µm UMC Flash FPGA Reliability Summary
(ProASIC3, ProASIC3E – A3P, A3PE; ProASIC3L, ProASIC3EL – A3PL, A3PEL; ProASIC3 nano –
A3PN, RT ProASIC3 – RT3P)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
0.065 μm UMC Flash FPGA Reliability Summary (SmartFusion2 – M2S (S,T,TS), IGLOO2 – M2GL
(S,T,TS) Product Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SoC Reliability Report
3
Reliability Summary
Table 1: Reliability Summary: FIT Rate by Device Technology
Device Technology
Number of
CMOS Failures
Device
Hours
TJ (oC)
EA, eV
Confidence
FIT
MTTF
1.0 µm CMOS FPGA
1
3.60E+08
55
0.7
60%
5.62
1.78E+08
1.0 µm CMOS FPGA (RH1020)
0
3.97E+07
55
0.7
60%
23.05
4.34E+07
0.8 µm CMOS FPGA (RH1280)
1
9.16E+07
55
0.7
60%
22.04
4.54E+07
0.8 µm CMOS FPGA
0
2.05E+08
55
0.7
60%
4.47
2.24E+08
0.6 µm CMOS FPGA
0
1.82E+08
55
0.7
60%
5.04
1.99E+08
0.6 µm RT54SX CMOS FPGA
0
2.29E+07
55
0.7
60%
39.88
2.51E+07
0.45 µm CSM CMOS FPGA
1
1.09E+08
55
0.7
60%
18.05
5.41E+07
0.45 µm UMC CMOS FPGA
0
3.80E+07
55
0.7
60%
24.06
4.16E+07
0.35 µm CMOS FPGA
0
6.31E+07
55
0.7
60%
14.51
6.89E+07
0.25 µm MEC CMOS FPGA
2
7.51E+07
55
0.7
60%
41.40
2.42E+07
0.25 µm Infineon Flash CMOS FPGA
0
3.62E+07
55
0.7
60%
25.30
3.95E+07
0.25 µm UMC CMOS FPGA
0
7.84E+08
55
0.7
60%
1.17
8.57E+08
0.22 µm UMC CMOS FPGA
0
5.19E+08
55
0.7
60%
1.76
5.67E+08
0.22 µm UMC Flash CMOS FPGA
0
8.49E+07
55
0.7
60%
10.77
9.28E+07
0.15 µm UMC CMOS FPGA
2
4.56E+08
55
0.7
60%
6.82
1.47E+08
0.13 µm Infineon Flash CMOS FPGA
0
4.56E+08
55
0.7
60%
2.01
4.98E+08
0.13 µm UMC Flash CMOS FPGA
1
2.78E+08
55
0.7
60%
7.28
1.37E+08
0.065 µm UMC Flash CMOS FPGA
0
3.64E+06
55
0.7
60%
3.22
3.11+08
Notes:
1. Refer to the “0.25 µm UMC FPGA Reliability Summary” section for RTSX-SU antifuse FIT rate reliability data.
2. Technically, mean time between failures (MTBF) should be used only in reference to repairable items, while MTTF
should be used for non-repairable items. However, MTBF is commonly used for both repairable and non-repairable
items, hence MTTF or MTBF = 1/FIT.
4
SoC Reliability Report
Table 2: Reliability Summary: FIT Rate by Device Technology and Product Family
Device Technology and Product Family
1.0 µm CMOS FPGA
Number of
CMOS
Failures
Device
Hours
1
3.60E+08
55
0.7
TJ (°C) EA, eV Confidence
FIT
MTTF
60%
5.62
1.78E+08
–
ACT1
1
1.93E+08
55
0.7
60%
10.49
9.53E+07
–
ACT2
0
1.67E+08
55
0.7
60%
5.48
1.82E+08
1.0 µm CMOS FPGA (RH1020)
0
3.97E+07
55
0.7
60%
23.06
4.34E+07
0.8 µm CMOS FPGA (RH1280)
1
9.16E+07
55
0.7
60%
22.04
4.54E+07
0.8 µm CMOS FPGA (ACT3)
0
2.05E+08
55
0.7
60%
4.47
2.24E+08
0.6 µm CMOS FPGA
0
1.82E+08
55
0.7
60%
5.04
1.99E+08
–
ACT3
0
6.13E+07
55
0.7
60%
14.93
6.70E+07
–
XL
0
7.73E+07
55
0.7
60%
11.83
8.45E+07
–
DX
0
4.31E+07
55
0.7
60%
21.25
4.70E+07
0.6 µm RT54SX CMOS FPGA
0
2.29E+07
55
0.7
60%
39.88
2.51E+07
0.45 µm CSM CMOS FPGA (MX)
1
1.09E+08
55
0.7
60%
18.05
5.41E+07
0.45 µm UMC CMOS FPGA (MX)
0
3.80E+07
55
0.7
60%
24.06
4.16E+07
0.35 µm CMOS FPGA (SX)
0
6.31E+07
55
0.7
60%
14.51
6.89E+07
0.25 µm MEC CMOS FPGA
2
7.51E+07
55
0.7
60%
41.40
2.42E+07
–
SX-A
0
3.15E+07
55
0.7
60%
29.08
3.44E+07
–
RTSX™-S
2
4.37E+07
55
0.7
60%
71.23
1.40E+07
0
3.62E+07
55
0.7
60%
25.30
3.95E+07
0.25 µm UMC CMOS FPGA (RTSX-SU)
0
7.84E+08
55
0.7
60%
1.17
8.57E+08
0.22 µm UMC CMOS FPGA (SX-A/eX1)
0
5.19E+08
55
0.7
60%
1.76
5.67E+08
0.22 µm UMC Flash CMOS FPGA
0
8.49E+07
55
0.7
60%
10.77
9.28E+07
0.15 µm UMC CMOS FPGA
(Axcelerator)
0
2.67E+07
55
0.7
60%
34.23
2.92E+07
0.15 µm UMC CMOS FPGA (RTAX-S)
2
4.29E+08
55
0.7
60%
7.24
1.38E+08
0.25 µm Infineon Flash CMOS FPGA
(ProASIC®)
(ProASICPLUS®)
Notes:
1. The eX family of devices is covered under the 0.22 µm FPGA family by similarity (extension). Testing is conducted on
the SX-A devices for the eX family. The smallest SX-A device (A54SX08A) is the largest die equivalent to the eX256.
2. The IGLOO®2 – M2GL family of devices is covered under 0.065um; SmartFusion®2 – M2S FPGA family by similarity
(extension).
• M2GL and M2S are fabricated at UMC, using the same foundry process and maskset.
• M2GL has a reduced product feature set compared to the M2S product family.
3. For Customer defined accelerated programming qualification:
• The maximum number of programming cycles allowed in SmartFusion2 or IGLOO2 is defined for the life of the
product. Refer to the datasheet for specifications. Typical real-life programming usage varies from one-time
programming, to a few programming cycles on the production lines, to periodic in-application updates, to multiple
programming cycles per day during system development and integration in a lab environment. If accelerated
programming qualification is required, Microsemi recommends a maximum of 6 back-to-back programming cycles
with a minimum of 15 minutes between programming cycles, followed by a 24 hour wait before the next round of
programming cycles.
SoC Reliability Report
5
Table 2: Reliability Summary: FIT Rate by Device Technology and Product Family (continued)
Number of
CMOS
Failures
Device
Hours
0.13 µm Infineon Flash CMOS FPGA
(ProASIC3 – A3P)
0
2.28E+08
55
0.7
0.13 µm Infineon Flash CMOS FPGA
(Fusion – AFS)
0
1.41E+08
55
0.13 µm Infineon Flash CMOS FPGA
(SmartFusion – A2F)
0
8.70E+07
0.13 µm UMC Flash CMOS FPGA
0
0.13 µm UMC Flash CMOS FPGA
(ProASIC3– A3P/RT3PEL)
0.065 µm UMC Flash CMOS FPGA
Device Technology and Product Family
TJ (°C) EA, eV Confidence
FIT
MTTF
60%
4.01
2.50E+08
0.7
60%
6.51
1.54E+08
55
07
60%
10.51
9.51E+07
1.37E+08
55
0.7
60%
6.78
1.48E+08
1
1.43E+08
55
0.7
60%
14.15
7.07E+07
0
3.64E+06
55
0.7
60%
3.22
3.11+08
(IGLOO® – AGL)
®
(SmartFusion 2 – M2S /
IGLOO®2 – M2GL2, 3)
Notes:
1. The eX family of devices is covered under the 0.22 µm FPGA family by similarity (extension). Testing is conducted on
the SX-A devices for the eX family. The smallest SX-A device (A54SX08A) is the largest die equivalent to the eX256.
2. The IGLOO®2 – M2GL family of devices is covered under 0.065um; SmartFusion®2 – M2S FPGA family by similarity
(extension).
• M2GL and M2S are fabricated at UMC, using the same foundry process and maskset.
• M2GL has a reduced product feature set compared to the M2S product family.
3. For Customer defined accelerated programming qualification:
• The maximum number of programming cycles allowed in SmartFusion2 or IGLOO2 is defined for the life of the
product. Refer to the datasheet for specifications. Typical real-life programming usage varies from one-time
programming, to a few programming cycles on the production lines, to periodic in-application updates, to multiple
programming cycles per day during system development and integration in a lab environment. If accelerated
programming qualification is required, Microsemi recommends a maximum of 6 back-to-back programming cycles
with a minimum of 15 minutes between programming cycles, followed by a 24 hour wait before the next round of
programming cycles.
6
SoC Reliability Report
ESD Performance
Table 3: Summary of ESD Performance for All Product Families (TM 3015/JESD22-A114)
Product Family
ESD
(Volts)
HBM
Family Members
Fab
Technology
ACT1
2000
A1010B, A1020B
1.0 µm
ACT2
1000
A1225A, A1240A, A1280A, RT1280A
1.0 µm
RH1020
4100
RH1020, RT1020
1.0 µm
RH1280
1500
RH1280
0.8 µm
ACT3
2000
A1415A, A1425A, A1460A, A14100A, & RT Variants
0.8 µm
XL
1500
A1225XL, A1240XL, A1280XL
0.6 µm
DX
2000
A3265DX, A32100DX, A32140DX, A32200DX, A32300DX
0.6 µm
RT54SX
2000
RT54SX16, RT54SX32
0.6 µm
MX
20007
A40MX02, A40MX04,A42MX09, A42MX16, A42MX24, A42MX36
0.45 µm
SX
2000
A54SX08, A54SX16, A54SX16P, A54SX32
0.35 µm
SX-A
20001
A54SX16A, A54SX32A, A54SX72A
0.25 µm
RTSX-S
20001
RT54SX32S, RT54SX72S
0.25 µm
ProASIC
2000
A500K050, A500K130, A500K180, A500K270
0.25 µm
RTSX-SU
20001
RT54SX32SU, RT54SX72SU
0.25 µm
SX-A
20001
A54SX08A, A54SX16A, A54SX32A, A54SX72A
0.22 µm
eX
20001
eX64, eX128, eX256
0.22 µm
ProASICPLUS
2000
APA075, APA150, APA300, APA450, APA600, APA750, APA1000
0.22 µm
Axcelerator®
2000
AX125, AX250, AX500, AX1000, AX2000
0.15 µm
RTAX-S
2000
RTAX250S, RTAX1000S, RTAX2000S, RTAX4000S
0.15 µm
Notes:
1. Except for 4 GNDQ pins, all other pins pass ESD performance of 2000 V, HBM. Refer to the application note at AC233:
Electro-Static Discharge App Note for more details.
• On the 4 GNDQ pins: eX devices passed 50 V HBM.
• SX-A, RTSX-S, and RTSX-SU devices passed at 75 V HBM.
2. Passed 2000 V HBM on all pins except VCC33A, which meets 500 V.
3. Passed 2000 V HBM on all pins except VCC33A and VCC33PMP, which meet 250 V.
4. Passed 2000 V HBM on all pins except VCC_PLL, which meets 500 V.
5. ProASIC3, ProASIC3E, ProASIC3L, ProASIC3/EL, IGLOO, IGLOOe, IGLOO PLUS, and Fusion passed
200 V CDM.
6. ProASIC 3 nano, IGLOO nano, and SmartFusion passed 500 V CDM.
7. MX (Foundry UMC) passed 2000 V HBM on all pins except power supply pins VPP and VSV, which meet 1500 V.
8. Passed 2000 V HBM on all pins except VCC_PLL / VCOMP_PLL, which meet 500 V.
9. Passed 2000 V HBM on all pins except for the SERDES internal PLL supply which meet 1000 V HBM. Passed 500 V
CDM on all pins except for SERDES internal PLL supply which meet 250 V.
SoC Reliability Report
7
Table 3: Summary of ESD Performance for All Product Families (TM 3015/JESD22-A114) (continued)
Product Family
ProASIC3®
ESD
(Volts)
HBM
2000
A3P015, A3P030, A3P060, A3P1254, A3P250, A3P400, A3P600,
A3P1000, A3PE600, A3PE1500, A3PE3000
0.13 µm
2000
A3P250L, A3P600L, A3P1000L, A3PE600L, A3PE3000L, RT3PE600L8,
0.13 µm
® 5
ProASIC3 E
ProASIC®3L
Fab
Technology
Family Members
ProASIC®3/EL5
RT3PE3000L8
RT3PEL
ProASIC®3 nano6
2000
A3PN010, A3PN015, A3PN020, A3PN030, A3PN060, A3PN125,
A3PN250
0.13 µm
Fusion® 5
2000
AFS0902, AFS2502, AFS6003, AFS15003
0.13 µm
SmartFusion® 5
2000
A2F060, A2F200, A2F500
0.13 µm
IGLOO®/IGLOO®e5
2000
AGL015, AGL030, AGL0604, AGL1254, AGL2504, AGL4004, AGL6004,
4
4
AGL1000 , AGLE600 , AGLE3000
0.13 µm
4
2000
AGLP030, AGLP0604, AGLP1254
0.13 µm
IGLOO® nano6
2000
AGLN010, AGLN015, AGLN020, AGLN060, AGLN125, AGLN250,
AGLN030Z, AGLN060Z, AGLN125Z, AGLN250Z
0.13 µm
SmartFusion2
2000
M2S005, M2S010, M2S025, M2S0509, M2S090, M2S150
0.065 µm
IGLOO®
PLUS5
IGLOO2
M2GL005, M2GL010, M2GL025, M2GL0509, M2GL060, M2GL090,
M2GL150
Notes:
1. Except for 4 GNDQ pins, all other pins pass ESD performance of 2000 V, HBM. Refer to the application note at http://
www.actel.com/documents/ESD_AN.pdf for more details.
• On the 4 GNDQ pins: eX devices passed 50 V HBM.
• SX-A, RTSX-S, and RTSX-SU devices passed at 75 V HBM.
2. Passed 2000 V HBM on all pins except VCC33A, which meets 500 V.
3. Passed 2000 V HBM on all pins except VCC33A and VCC33PMP, which meet 250 V.
4. Passed 2000 V HBM on all pins except VCC_PLL, which meets 500 V.
5. ProASIC3, ProASIC3E, ProASIC3L, ProASIC3/EL, IGLOO, IGLOOe, IGLOO PLUS, and Fusion passed 200 V CDM.
6. ProASIC3 nano, IGLOO nano, and SmartFusion passed 500 V CDM.
7. MX (Foundry UMC) passed 2000V HBM on all pins except power supply pins Vpp and VSV, which meet 1500 V.
8. Passed 2000 V HBM on all pins except VCC_PLL / VCOMP_PLL, which meet 500 V.
9. Passed 2000 V HBM on all pins except for the SERDES internal PLL supply which meet 1000 V HBM. Passed 500 V
CDM on all pins except for SERDES internal PLL supply which meet 250 V.
Table 4: Summary of ESD Performance for AEC-Q100 Qualified Product Families (AEC-Q100-002)
Product Family ESD (volts) HBM
ProASIC3
8
1500
Family Members
Fab Technology
A3P060, A3P125, A3P250, and A3P1000
0.13 µm
SoC Reliability Report
Group E Inspection—Generic Data (Radiation Hardness)
Verification of radiation performance for each wafer lot is performed through in-line parameter monitoring
in the QML RHA wafer production line. Table 5 lists the summarized radiation performance of RH FPGAs.
Table 5: Radiation Performance for RadHard Devices (Data Published on SMDs)
Total Dose
TID
RH1280
RH1020
Units
300
300
krads (Si)
Single Event Latch-Up
177
>84
LETth (MeV-cm2/mg)
Single Event Upset – Combinatorial
17
>8
LETth (MeV-cm2/mg)
Single Event Upset – Sequential
4
–
LETth (MeV-cm2/mg)
Single Event Dielectric Rupture
>60
>40
LETth (MeV-cm2/mg)
Total Ionizing Radiation Dose
SEP (Single Event Phenomena)
SEL
SEU
SEDR
Note: Wafer Lot Acceptance (SEM)—RHCMOS4EF (ONO PBEOL) wafer process utilizes plugged vias, which eliminates
the step coverage issue, so the SEM metallization inspection is not required.
1.0 µm FPGA Reliability Summary
Table 6: High Temperature Operating Life (HTOL)
Test Hours / Failures
Number
of Units
Test
Time
168
500
1000
U1G-01
79
1000
0
0
0
79000
PLCC68
U1G-02
57
500
0
0
–
28500
A1010B
PQFP100
U9G01P
76
1000
0
0
0
76000
A1020B
CQFP84
UP121
24
1000
0
0
0
24000
A1020B
PGA84
U1P057/0014
97
2000
0
0
0
A1020B
PGA84
JJ-13
30
1000
0
0
0
A1020B
PGA84
JJ-13
80
500
0
0
A1020B
PLCC84
JJ-14
45
1000
0
0
0
45000
A1020B
PLCC84
JJ-15
45
1000
0
0
0
45000
A1020B
PLCC84
JJ-17
45
1000
0
0
0
45000
A1020B
PLCC84
JJ-16
80
1000
0
0
0
80000
A1020B
PLCC84
U1P-01
40
1000
0
0
0
40000
A1020B
PLCC84
U1P-02
40
1000
0
0
0
40000
A1020B
PLCC84
JJ-24
87
1000
0
0
0
87000
A1020B
PLCC84
EBFJ001
40
1000
0
0
0
40000
A1020B
PLCC84
EBFI004
40
1000
0
0
0
40000
A1020B
PLCC84
U1P209B
40
1000
0
0
0
40000
Product
Package
Wafer Lot
A1010B
PLCC68
A1010B
Date
Code
2000
0
Unit
Hours
194000
30000
40000
Notes:
1. Tested at 150ºC. Equivalent hours corresponding to 125ºC were used to calculate the FIT rates.
2. Functional failure was observed for the product A1020B, run U9P01, at 500 hours. No defects were observed after
decapsulation.
3. Functional failure was observed during Group C for the product A1020B, run FP4946901, at 1000 hours. FA concluded
ESD/EOS event caused by voltage spike. Group C passed per TRB approval. Observation only; not counted towards
device FIT.
SoC Reliability Report
9
Table 6: High Temperature Operating Life (HTOL) (continued)
Test Hours / Failures
Number
of Units
Test
Time
168
500
1000
U9P-004
47
1000
0
0
0
47000
PLCC84
U9P046
100
1000
0
0
0
100000
PLCC84
6085878
100
1000
0
0
0
100000
Product
Package
Wafer Lot
A1020B
PLCC84
A1020B
A1020B
Date
Code
2000
Unit
Hours
A1020B
PLCC84
U9P128
100
1000
0
0
0
A1020B
PLCC84
UB9P034
98
2000
0
0
0
A1020B
PQFP100
U1P41HM
80
1000
0
0
0
80000
A1020B
PQFP100
U1P05
129
1000
0
0
0
129000
A1020B1
PGA84
UB1P001
77
615
0
0
0
47355
A1020B2
PQFP100
U9P01,
U9P021A
133
1000
0
1
0
133000
A1020B
VQFP80
U1P25
45
500
0
0
–
22500
A1020B
VQFP80
U1P83
43
1000
0
0
0
43000
A1020B
VQFP80
U1P25
39
1000
0
0
0
39000
A1020B1
PGA84
UB1P008
77
615
0
0
0
47355
A1020B
PGA84
FP4946901
80
1000
0
0
(1)3
79000
A1020B1
CQFP84
U1RT01
80
1671
0
0
0
133680
A1020B
PGA84
FP2458201
77
1000
0
0
0
77000
A1020B
PGA84
UB1P012
77
1000
0
0
0
77000
A1020B
CQFP84
FP6502401
79
615
0
0
A1225A
PGA100
UJ-01
80
1000
0
0
0
80000
A1225A
PQFP100
MIX
32
1000
0
0
0
32000
A1225A
PQFP100
UJ-01
127
1000
0
0
0
127000
A1225A
PQFP100
U1J-02
80
1000
0
0
0
80000
A1240A
PGA132
TI3257
7
500
0
0
–
3500
A1240A
PGA132
UI-01
50
1000
0
0
0
50000
A1240A
PLCC84
UI-03
80
1000
0
0
0
80000
A1240A
PLCC84
E-04
30
2000
0
0
0
A1240A
PQFP144
MIX
36
1000
0
0
0
36000
A1240A
PQFP144
E-02,03
100
1000
0
0
0
100000
A1240A
PQFP144
U1I-26
80
1000
0
0
0
80000
A1240A
PGA132
FP3879301
80
1000
0
0
0
A1240A1
PGA132
FP16459
77
615
0
0
0849
1047
100000
0
196000
48567
0
60000
80000
47355
Notes:
1. Tested at 150ºC. Equivalent hours corresponding to 125ºC were used to calculate the FIT rates.
2. Functional failure was observed for the product A1020B, run U9P01, at 500 hours. No defects were observed after
decapsulation.
3. Functional failure was observed during Group C for the product A1020B, run FP4946901, at 1000 hours. FA concluded
ESD/EOS event caused by voltage spike. Group C passed per TRB approval. Observation only; not counted towards
device FIT.
10
SoC Reliability Report
Table 6: High Temperature Operating Life (HTOL) (continued)
Test Hours / Failures
Number
of Units
Test
Time
168
500
UB1H001
77
615
0
0
CQFP172
U1H486
81
1000
0
0
A1280A1
CQFP172
U1H442
81
615
0
0
49815
A1280A1
CQFP172
U1H363
58
615
0
0
35670
A1280A1
CQFP172
U1H83
45
1670
0
0
A1280A1
PGA176
U1H511
77
615
0
0
A1280A
PGA176
JH05
15
2000
0
0
0
0
30000
A1280A
PGA176
JH06
15
2000
0
0
0
0
30000
A1280A
PGA176
JH03(K)
25
2000
0
0
0
0
50000
A1280A
PGA176
JH03(SB)
25
2000
0
0
0
0
50000
A1280A
PGA176
UH-01
26
1000
0
0
0
26000
A1280A
PGA176
UH-02
26
1000
0
0
0
26000
A1280A
PGA176
UH-05
40
1000
0
0
0
40000
A1280A
PGA176
UH-10,14
75
1000
0
0
0
75000
A1280A
PGA176
U1H-35
132
168
0
A1280A
PQFP160
UH-04
79
1000
0
0
0
79000
A1280A
PQFP160
ADC18X
130
1000
0
0
0
130000
A1280A
PQFP160
EBFJ002
30
168
0
5040
A1280A
PQFP160
EBFJ003
30
168
0
5040
A1280A
PQFP160
EBFJ004
20
168
0
3360
A1280A
PQFP160
U1H-01
27
2000
0
0
0
0
54000
A1280A
PQFP160
U1H-02
27
2000
0
0
0
0
54000
PQFP160
U1H-18
80
1000
0
0
0
CQFP172
UB1H029
77
615
0
0
A1280A
CQFP172
U1H439
18
1000
0
0
RT1280A1
CQFP172
U1H611
15
615
0
0
RT1280A
CQFP172
U1H609S
10
1000
0
0
0
10000
RT1280A
CQFP172
FP21573
12
1000
0
0
0
12000
RT1280A
CQFP172
U1H611
RT1280A
CQFP172
FP5986501
Product
Package
Wafer Lot
A1280A1
CQFP172
A1280A
A1280A
A1280A
1
Date
Code
1004
TOTAL Units for 1.0 µm FPGA =
1000
2000
Unit
Hours
47355
0
81000
0
75150
47355
22176
80000
47355
0
18000
9225
12
1000
0
0
0
12000
80
1000
0
0
0
80000
Total Test Time Hours =
4613353
4710
Notes:
1. Tested at 150ºC. Equivalent hours corresponding to 125ºC were used to calculate the FIT rates.
2. Functional failure was observed for the product A1020B, run U9P01, at 500 hours. No defects were observed after
decapsulation.
3. Functional failure was observed during Group C for the product A1020B, run FP4946901, at 1000 hours. FA concluded
ESD/EOS event caused by voltage spike. Group C passed per TRB approval. Observation only; not counted towards
device FIT.
SoC Reliability Report
11
Table 6: High Temperature Operating Life (HTOL) (continued)
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
168
500
1000
2000
Unit
Hours
TOTAL Failures for 1.0 µm FPGA = 1
ACT1
TOTAL Units for 1.0 µm FPGA =
2406
Total Test Time Hours =
2472957
TOTAL Failures for 1.0 µm ACT1 FPGA = 1
ACT2
TOTAL Units for 1.0 µm FPGA =
2304
Total Test Time Hours =
2140396
TOTAL Failures for 1.0 µm ACT2 FPGA = 0
Notes:
1. Tested at 150ºC. Equivalent hours corresponding to 125ºC were used to calculate the FIT rates.
2. Functional failure was observed for the product A1020B, run U9P01, at 500 hours. No defects were observed after
decapsulation.
3. Functional failure was observed during Group C for the product A1020B, run FP4946901, at 1000 hours. FA concluded
ESD/EOS event caused by voltage spike. Group C passed per TRB approval. Observation only; not counted towards
device FIT.
Table 7: 85°C/85% Temperature Humidity BIAS
Test Hours / Failures
Number
of Units
Test
Time
168
500
1000
JJ-14
27
1000
0
0
0
27000
PLCC84
JJ-15
27
1000
0
0
0
27000
PLCC84
JJ-17
27
1000
0
0
0
27000
Total Test Time Hours =
81000
Product
Package
Wafer Lot
A1020B
PLCC84
A1020B
A1020B
Date
Code
TOTAL Units for 1.0 µm FPGA =
81
2000
Unit
Hours
TOTAL Failures for 1.0 µm FPGA = 0
Table 8: Biased Humidity (HAST)
Test Hours / Failures
Number
of Units
Test Time
50
100
EBFJ001
44
100
0
0
4400
PLCC84
EBFI004
36
100
0
0
3600
A1020B
PLCC84
U9P01
29
100
0
0
2900
A1020B
PLCC84
U9P021A
50
100
0
0
5000
A1020B
PLCC84
U9P039
50
100
0
0
5000
A1020B
PLCC84
U9P046
50
100
0
0
5000
A1020B
PLCC84
6085878
50
100
0
0
5000
A1020B
PLCC84
103501
61
100
0
0
6100
Product
Package
Wafer Lot
A1020B
PLCC84
A1020B
Date
Code
TOTAL Units for 1.0 µm FPGA =
370
200
250
Total Test Time Hours =
Unit
Hours
37000
TOTAL Failures for 1.0 µm FPGA = 0
12
SoC Reliability Report
Table 9: Temperature Cycle
Number of Cycles / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
100
500
1000
2000
Cycles
(0°C – +125°C)
TOTAL Units for 1.0 µm FPGA =
0
Total Test Cycles =
0
TOTAL Failures for 1.0 µm FPGA = 0 (0°C – +125°C)
(–55°C – +125°C)
A1020B
PLCC68
U9P186
30
1000
0
0
0
30000
A1020B
PQFP100
U9G042
25
1000
0
0
0
25000
TOTAL Units for 1.0 µm FPGA =
55
Total Test Cycles =
55000
TOTAL Failures for 1.0 µm FPGA = 0 (–55°C – +125°C)
(–65°C – +150°C)
A1010B
PLCC68
U1G-01,02
40
1000
0
0
0
40000
A1020B
PLCC84
JJ14-17
81
1000
0
0
0
81000
A1020B
PLCC84
U1P-01,02
40
1000
0
0
0
40000
A1020B
PLCC84
EBFJ001
80
1000
0
0
0
80000
A1020B
PQFP100
U1P41HM
80
1000
0
0
0
80000
A1020B
PLCC84
EWAI003
80
1000
0
0
0
80000
A1020B
PLCC84
U1P-209B
15
1000
0
0
0
15000
A1020B
PQFP100
U1P05
80
1000
0
0
0
80000
A1020B
PLCC84
U9P021A
55
1000
0
0
0
55000
A1020B
PLCC84
U9P01
23
1000
0
0
0
23000
A1020B
PLCC84
U9P039
50
1000
0
0
0
50000
A1020B
PLCC84
U9P046
50
1000
0
0
0
50000
A1020B
PLCC84
6085878
50
1000
0
0
0
50000
A1020B
PLCC84
103501
62
1000
0
0
0
62000
TOTAL Units for 1.0 µm FPGA =
786
Total Test Cycles =
786000
TOTAL Failures for 1.0 µm FPGA = 0 (–65°C – +150°C)
Table 10: Pressure Pot (Unbiased Autoclave)
Test Hours / Failures
Number
of Units
Test Time
96
168
240
U1G-01
40
264
0
0
0
10560
PLCC84
JJ14-17
81
264
0
0
0
21384
A1020B
PLCC84
U1P-01
40
264
0
0
0
10560
A1020B
PLCC84
U09039
50
264
0
0
0
13200
TOTAL Units for 1.0 µm FPGA =
211
Product
Package
Wafer Lot
A1010B
PLCC68
A1020B
Date
Code
336
Total Test Time Hours =
Unit
Hours
55704
TOTAL Failures for 1.0 µm FPGA = 0
SoC Reliability Report
13
1.0 µm FPGA (RH) Reliability Summary
Table 11: High Temperature Operating Life (HTOL)1
Test Hours / Failures
Number
of Units
Test
Time
168
500
1000
T8036
78
1000
0
0
0
78000
CQFP172
T9064
40
1000
0
0
0
40000
RH10202
CQFP172
T9085
15
615
0
0
RH1020
CQFP172
T9089
8
1000
0
0
0
8000
RH1020
CQFP172
T2208
18
1000
0
0
0
18000
RH10203
CQFP172
T2404
48
1000
0
0
0
48000
207
5615
Product
Package
Wafer Lot
RH1020
CQFP172
RH1020
Date
Code
TOTAL Units for 1.0 µm RH1020 FPGA =
Unit
Hours
2000
9225
Total Test Time Hours =
201225
TOTAL Failures for 1.0 µm RH1020 FPGA = 0
Notes:
1. Data from BAe
2. Tested at 150ºC. Equivalent hours corresponding to 125ºC were used to calculate the FIT rates.
3. One unit failed at –55ºC after completing 1000 hours, which was verified to be false failure due to tester noise.
14
SoC Reliability Report
0.8 µm FPGA (RH) Reliability Summary
Table 12: High Temperature Operating Life (HTOL)1
Test Hours / Failures
Product
Package
Wafer Lot
Date Code
Number
Units
Test
Time
168
500
1000
RH1280
CQFP172
FPGAQQC11
95507A.1
6
1000
0
0
0
6000
RH1280
CQFP172
FPGAQQC11
95507C.1
17
1000
0
0
0
17000
RH1280
CQFP172
FPGAQQC11 95506C.1,2,3
34
1000
0
0
0
34000
RH1280
CQFP172
FPGAQQC11
20
1000
0
0
0
20000
RH1280
CQFP172
T7013C
12
1000
0
0
0
12000
95506D.1
2000
Unit
Hours
RH1280
CQFP172
T7013C
96580C.1
33
1000
0
0
0
33000
RH12802
CQFP172
T7013C
96580E.1
32
1000
1
0
0
32000
RH1280
CQFP172
T9065
1990510 &
1990511
61
1000
0
0
0
61000
RH1280
CQFP172
T9066
10
1000
0
0
0
10000
RH1280
CQFP172
T9072
12
1000
0
0
0
12000
RH1280
CQFP172
T9088-
38
1000
0
0
0
38000
RH1280
CQFP172
T2208
59
1000
0
0
0
59000
334
12000
Total Test Time Hours =
334000
TOTAL Units for 1.0 µm RH1280 FPGA =
TOTAL Failures for 1.0 µm RH1280 FPGA = 1
Notes:
1. Data from BAe
2. No defect found. Part destroyed in analysis.
SoC Reliability Report
15
0.8 µm FPGA Reliability Summary
Table 13: High Temperature Operating Life (HTOL)
Test Hours / Failures
Test
Time
168
500
1000
77
615
0
0
0
47355
UCL058
82
615
0
0
0
50430
A14100A1,2 CQFP256
UCL072
78
615
(1)
0
0
47970
A14100A3
CQFP256
UCL049
15
1,000
0
0
(1)
15000
A14100A
CQFP256
UCL055
18
1,000
0
0
0
18000
A14100A1
CQFP256
UCL058
82
561
0
A14100A
CQFP256
UCL073
10
1,000
0
0
0
10000
A14100A1
CQFP256
UCL082
10
1,670
0
0
0
16700
A14100A
PBGA313
25290820
45
1000
0
0
0
45000
A14100A
RQFP208
24239130
51
1000
0
0
0
51000
A14100A
RQFP208
UCLO1
25
1000
0
0
0
25000
A14100A
CQFP256
FP4947201
80
1000
0
0
0
80000
A14100A
CQFP256
FP2732701
12
1000
0
0
0
12000
A14100A
CQFP256
UBCL011
12
1000
0
0
0
12000
A14100A
CQFP256
UCL086
10
1000
0
0
0
10000
A14100A1
CQFP256
UBCL009
80
615
0
0
A1425A1
PGA133
UCJ01/02E/03
130
615
0
0
0
79950
A1425A
PGA133
JK08,09,10
140
1000
0
0
0
140000
A1425A
PGA133
ACN32804,
ACN30805,
ACN33807
130
1000
0
0
0
130000
A1425A1
PGA133
UCJ01, 2, 3
130
615
0
0
0
79950
A1425A
PLCC84
JK08, 09, 10
135
1000
0
0
0
135000
A1425A
PQFP100
UCJ013
100
1000
0
0
0
100000
A1440A
VQFP100
51940
79
1000
0
0
0
79000
A1440A
VQFP100
JN05
79
1000
0
0
0
79000
A1460A1
PGA207
UCK056
80
561
0
44880
A1460A1
CPGA207
UCKT01
81
561
0
45441
A1460A1
PGA207
UCK005
77
615
0
Product
Package
Wafer Lot
A14100A1
CQFP256
UBCLP01A
A14100A1
CQFP256
Date Number
Code of Units
2000
Unit
Hours
46002
0
49200
0
47355
Notes:
1. Tested at 150ºC. Equivalent hours corresponding to 125ºC were used to calculate the FIT rates.
2. Product A14100A, run UCL072, at 168 hours, one unit failed gross-functional. FA shown contact spike caused by ESD/
EOS, qualification passed by TRB approval.
3. Product A14100A, run UCL049, at 1000 hours, unit failed was proven by FA as EOS. No functional failures observed.
16
SoC Reliability Report
Table 13: High Temperature Operating Life (HTOL) (continued)
Test Hours / Failures
Test
Time
168
500
80
615
0
0
49200
UCKT01
81
615
0
0
49815
PGA207
JL-01
80
1000
0
0
0
80000
A1460A
PGA207
JL-06B
65
1000
0
0
0
65000
A1460A
PGA207
PC435091, PC435092,
PC435093
80
1000
0
0
0
80000
A1460A
PQFP208
20072420
0026
30
1000
0
0
0
30000
A1460A
PQFP208
20094560
0022
29
1000
0
0
0
29000
A1460A
PQFP208
20145270
0026
30
1000
0
0
0
30000
A1460A
PQFP208
29350050
9947
65
2000
0
0
0
0
130000
A1460A
PQFP208
UCK070
9946
22
2000
0
0
0
0
44000
A1460A
PQFP208
JL-01
80
1000
0
0
0
80000
A1460A
PQFP208
JL-03
62
1000
0
0
0
62000
A1460A
PGA207
FP4341401
80
1000
0
0
0
80000
A1460A
PGA207
FP12176
79
1000
0
0
0
79000
A1460A
PGA207
FP2157501
80
1000
0
0
0
80000
A1460A
PGA207
FP03898A
77
1000
0
0
0
77000
RT14100A
CQFP256
UCL055
18
1000
0
0
0
18000
RT14100A
CQFP256
UCL073
9949
15
1000
0
0
0
15000
RT14100A
CQFP256
UCL073
0019
10
1000
0
0
0
10000
RT14100A1
CQFP256
UCL72
9931
9925
77
561
0
Product
Package
Wafer Lot
A1460A1
PGA207
UCK056
A1460A1
PGA207
A1460A
Date Number
Code of Units
TOTAL Units for 0.8 µm FPGA =
2988
1000
2000
Unit
Hours
43197
Total Test Time Hours = 2627445
TOTAL Failures for 0.8 µm FPGA = 0
TOTAL Units for 0.8 µm ACT3 FPGA =
2988
Total Test Time Hours = 2627445
TOTAL Failures for 0.8 µm ACT3 FPGA = 0
Notes:
1. Tested at 150ºC. Equivalent hours corresponding to 125ºC were used to calculate the FIT rates.
2. Product A14100A, run UCL072, at 168 hours, one unit failed gross-functional. FA shown contact spike caused by ESD/
EOS, qualification passed by TRB approval.
3. Product A14100A, run UCL049, at 1000 hours, unit failed was proven by FA as EOS. No functional failures observed.
SoC Reliability Report
17
Table 14: 85°C/85%Temperature Humidity Bias
Test Hours / Failures
Number of
Units
Test
Time
168
500
1000
25290820
45
1000
0
0
0
45000
TOTAL Units for 0.8 µm FPGA =
45
Total Test Time Hours =
45000
Product
Package
Wafer Lot
A14100A
PBGA313
Date
Code
2000
Unit Hours
TOTAL Failures for 0.8 µm FPGA = 0
Table 15: Biased Humidity (HAST)
Test Hours / Failures
Number
of Units
Test
Time
50
100
JK8,9,10
81
100
0
0
8100
PQFP100
ACN32804,
ACN30805,
ACN33807
80
100
0
0
8000
A1425A
PQFP100
UCJ01,2,3
80
100
0
0
8000
A1440A
VQFP100
JN05
45
100
0
0
4500
A1440A
VQFP100
51940
45
100
0
0
4500
A1460A
PQFP208
JL04A
80
100
0
0
8000
A1460A
PQFP208
WB24279010
47
100
0
0
4700
A14100A
RQFP208
24239130
14
100
0
0
1400
Product
Package
Wafer Lot
A1425A
PLCC84
A1425A
Date
Code
TOTAL Units for 0.8 µm FPGA =
472
200
250
Total Test Time Hours =
Unit
Hours
47200
TOTAL Failures for 0.8 µm FPGA = 0
Table 16: Temperature Cycle
Number of Cycles / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
100
200
500
0
0
1000
Cycles
(–65°C – +150°C)
A14100A
PBGA313
25290820
78
500
0
A14100A
RQC208
MIX
24
100
0
2400
A14100A
RQC209
MIX
24
100
0
2400
A14100A
RQFP208
24239130
14
500
0
0
0
7000
A14100A
RQFP208
UCLO1
31
500
0
0
0
15500
A14100A
RQFP208
2537198
19
100
0
A1425A
PGA133
JK8,9,10
81
500
0
0
0
40500
A1425A
PLCC84
JK8,9,10
83
500
0
0
0
41500
A1425A
PQFP100
UCJ01,2,3
80
500
0
0
0
40000
A1425A
PQFP100
ACN32804,
ACN30805,
ACN33807
80
500
0
0
0
40000
A1440A
PQFP160
JN-02
80
500
0
0
0
40000
18
39000
1900
SoC Reliability Report
Table 16: Temperature Cycle (continued)
Number of Cycles / Failures
Number
of Units
Test
Cycles
100
200
500
JN-05
80
500
0
0
1
40000
VQFP100
51940
45
500
0
0
0
22500
A1460A
PGA207
JL-01
80
500
0
0
0
40000
A1460A
PGA207
PC435091,
PC435092,
PC435093
80
500
0
0
0
40000
A1460A
PQFP208
JL-01
80
500
0
0
0
40000
A1460A
PQFP208
25364430
45
500
0
0
0
22500
A1460A
PQFP208
2610001
80
500
0
0
0
40000
TOTAL Units for 0.8 µm FPGA =
1084
Product
Package
Wafer Lot
A1440A
VQFP100
A1440A
Date
Code
1000
Total Test Cycles =
Cycles
515200
TOTAL Failures for 0.8 µm FPGA = 1
Table 17: Pressure Pot (Unbiased Autoclave)
Test Hours / Failures
Number
of Units
Test
Time
48
96
25290820
45
96
0
0
TOTAL Units for 0.8 µm FPGA =
45
Product
Package
Wafer Lot
A14100A
PBGA313
Date
Code
168
Total Test Time Hours =
336
Unit
Hours
4320
4320
TOTAL Failures for 0.8 µm FPGA = 0
SoC Reliability Report
19
0.6 µm FPGA Reliability Summary
Table 18: High Temperature Operating Life (HTOL)
Test Hours / Failures
Product
Package
Wafer Lot
Date Number Test
Code of Units Time
168
500
1000
2000
Unit
Hours
A1225XL
PQFP100
ACP02187.1
26
1000
0
0
0
–
26000
A1225XL
PQFP100
ACQ10102
56
1000
0
0
0
–
56000
A1240XL
PLCC84
ACP57584.1
100
1000
0
0
0
–
100000
A1240XL
PQFP144
MIX
56
1000
0
0
0
–
56000
A1240XL
PQFP144
ACR50594.1
228
168
0
38304
A1240XL
PQFP144
ACR50594.1
143
168
0
24024
A1240XL
PQFP144
ACR50594.1
227
168
0
38136
A1240XL
PQFP144
ACP01117.1,
ACN51939.1
52
1000
0
0
A1280XL1
CQFP172
ACT10293.1
80
561
0
0
44880
A1280XL1
CQFP172
ACT10293.1
80
615
0
0
49200
A1280XL1
CQFP172
ACY953401
77
615
0
0
47355
A1280XL1,2
PGA176
ACU413553
77
615
(1)
0
47355
A1280XL1
PGA176
ACV715861
77
561
0
0
43197
A1280XL
PLCC84
MIX
100
1000
0
0
A1280XL
PQFP160
ACR53214
129
168
0
A1280XL
PQFP160
ACU458071/ 0008
86
2000
0
0
0
A1280XL
PQFP160
ACP212072,
ACP19329.1
76
1000
0
0
0
76000
A14100BP
RQFP208
26026670
27
1000
0
0
0
27000
A1415A
PQFP100
ACP17300
100
1000
0
0
0
100000
A1425A
PGA133
UCJ01,02,03
130
1670
0
0
0
217100
A1425A
PQFP100
ACP17300
101
2000
0
0
0
A1425A
PQFP100
ACP122761
100
1000
0
0
0
100000
A1425A
PQFP100
ACP12285
88
1000
0
0
0
88000
A1460BP
PQFP208
25430540
52
1000
0
0
0
52000
A32100DX1
CQFP84
ACR50293.1
80
615
0
0
A32140DX
PQFP208
ACP562551
28
2000
0
0
0
A32140DX
PQFP208
G10854
26
1000
0
0
0
0
–
0
52000
100000
21672
0
0
172000
202000
49200
0
56000
26000
Notes:
1. Tested at 150ºC. Equivalent hours corresponding to 125ºC were used to calculate the FIT rates.
2. Product A1280XL, run 2ACU413553, at 160 hours; unit failed was verified to be ESD/EOS.
3. Product A32200DX, run ACT16685.1, at 160 hours, rejects are due to electrical over stress (EOS) or ESD), which are
induced by HP1 tester during the same time frame in which these devices are tested. Failure modes are not life-test
induced; therefore, the qualification is still passed.
20
SoC Reliability Report
Table 18: High Temperature Operating Life (HTOL) (continued)
Test Hours / Failures
Product
Package
Wafer Lot
Date Number Test
Code of Units Time
168
500
1000
A32140DX
PQFP160
ACP540231
26
1000
0
0
0
26000
A32140DX
PQFP160
25464510
26
1000
0
0
0
26000
A32140DX
PQFP208
ACP33277.1
75
1000
0
0
0
75000
A32140DX
PQFP208
ACP56255.1
52
1000
0
0
0
52000
A32200DX1,3 CQFP256
ACT16685.1
77
1000
(1)
0
0
77000
A32200DX
CQFP256
ACV648421
5
615
0
0
3075
A32200DX1
CQFP256
ACV648421
5
615
0
0
3075
A32200DX1
PQFP208
26207340
29
1000
0
0
0
A32300DX
RQFP240
ACQ09069.1
26
2000
0
0
0
A3265DX
PQFP160
ACP163684
78
1000
0
0
0
TOTAL Units for 0.6 µm FPGA =
2801
2000
Unit
Hours
29000
0
52000
78000
Total Test Time Hours =
2330573
Total Test Time Hours =
786100
Total Test Time Hours =
992123
Total Test Time Hours =
552350
TOTAL Failures for 0.6 µm FPGA = 0
ACT3
TOTAL Units for ACT3 FPGA =
598
TOTAL Failures for ACT3 FPGA = 0
XL
TOTAL Units for XL FPGA =
1670
TOTAL Failures for XL FPGA = 0
DX
TOTAL Units for DX FPGA =
1207
TOTAL Failures for DX FPGA = 0
Notes:
1. Tested at 150ºC. Equivalent hours corresponding to 125ºC were used to calculate the FIT rates.
2. Product A1280XL, run 2ACU413553, at 160 hours; unit failed was verified to be ESD/EOS.
3. Product A32200DX, run ACT16685.1, at 160 hours, rejects are due to electrical over stress (EOS) or ESD), which are
induced by HP1 tester during the same time frame in which these devices are tested. Failure modes are not life-test
induced; therefore, the qualification is still passed.
SoC Reliability Report
21
Table 19: Biased Humidity (HAST)
Test Hours / Failures
Number
of Units
Test Time
50
100
ACP02187.1
17
100
0
0
1700
PQFP144
ACP01117.1,
ACN51939.1
31
100
0
0
3100
A1280XL
PQFP160
ACP19329.1
ACP212072
76
100
0
0
7600
A1280XL
PQFP160
ACP33235.1
76
100
0
0
7600
A1280XL
PQFP160
ACQ01769
40
100
0
0
4000
A1280XL
PQFP160
ACQ05561
39
100
0
0
3900
A3265DX
PQFP160
ACP163684
40
100
0
0
4000
A1415A
PQFP100
ACP17300
50
100
0
0
5000
A1425A
PQFP100
ACP122761
50
100
0
0
5000
A32140DX
PQFP160
ACP54023.1
26
100
0
0
2600
A32140DX
PQFP208
ACP33277.1,
ACP55730.1,
ACP54023.1
76
100
0
0
7600
A32200DX
PQFP208
26207340
26
100
0
0
2600
A14100BP
RQFP208
26330340
26
100
0
0
2600
A32200DX
PQFP208
ACQ03818.1
30
100
0
0
3000
A1280XL
PQFP160
26084380
58
100
0
0
5800
A32140DX
PQFP208
55558
25
100
0
0
2500
Product
Package
Wafer Lot
A1225Xl
PQFP100
A1240XL
Date
Code
TOTAL Units for 0.6 µm FPGA =
686
200
250
Total Test Time Hours =
Unit
Hours
68600
TOTAL Failures for 0.6 µm FPGA = 0
22
SoC Reliability Report
Table 20: Temperature Cycle
Number of Cycles / Failures
Number
of Units
Test
Cycles
100
200
500
25026540
17
500
0
0
0
8500
PQFP160
25312500, 25312480
76
500
0
0
0
38000
PQFP160
25312500, 25312480
76
200
0
0
A1280XL
PQFP160
25312500, 25312480
75
500
0
0
0
37500
A1280XL
PQFP160
25312500, 25312480
75
500
0
0
0
37500
A1280XL
PQFP160
25312500, 25312480
74
500
0
0
0
37000
A1280XL
PQFP160
25312500, 25312480
76
500
0
0
0
38000
A1280XL
PQFP160
25504560
36
500
0
0
0
18000
A1425A
PGA133
JK8,9,10
81
500
0
0
0
40500
Product
Package
Wafer Lot
A1280XL
TQFP176
A1280XL
A1280XL
Date
Code
1000
Cycles
15200
A1425A
PLCC84
JK8,9,10
83
500
0
0
0
41500
A1425A
PQFP100
UCJ01,2,3
80
500
0
0
0
40000
A1425A
PQFP100
ACN32804, ACN30805,
ACN33807
80
500
0
0
0
40000
A1440A
PQFP160
JN-02
80
500
0
0
0
40000
A1440A
VQFP100
JN-05
80
500
0
0
1
40000
A1440A
VQFP100
51940
45
500
0
0
0
22500
A1460A
PQFP208
JL-01
80
500
0
0
0
40000
A1460A
PGA207
JL-01
80
500
0
0
0
40000
A1460A
PGA207
PC435091, PC435092,
PC435093
80
500
0
0
0
40000
A1460A
PQFP208
25364430
45
500
0
0
0
22500
A1460A
PQFP208
2610001
80
500
0
0
0
40000
A14100A
RQFP208
24239130
14
500
0
0
0
7000
A14100A
RQFP208
UCLO1
31
500
0
0
0
15500
A14100A
RQFP208
2537198
19
100
0
A14100A
PBGA313
25290820
78
500
0
A14100A
RQFP208
MIX
24
100
0
2400
A14100A
RQFP208
MIX
24
100
0
2400
TOTAL Units for 0.6 µm FPGA =
1900
0
1589
0
39000
Total Test Cycles = 744900
TOTAL Failures for 0.6 µm FPGA = 1
Table 21: Pressure Pot (unbiased autoclave)
Test Time
48
96
168
25312480
45
168
0
0
0
25290820
45
96
0
0
Package
Wafer Lot
A1280XL
TQFP176
A14100A
PBGA313
Date
Code
Test Hours / Failures
Number
of Units
Product
TOTAL Units for 0.6 µm FPGA =
90
336
Total Test Time Hours =
Unit Hours
7560
4320
11880
TOTAL Failures for 0.6 µm FPGA = 0
SoC Reliability Report
23
0.6 µm RTSX FPGA Reliability Summary
Table 22: High Temperature Operating Life (HTOL)
Test Hours / Failures
Number
of Units
Test
Time
168
500
77
615
0
0
46
2000
0
0
0
P02, P03, P04
81
1000
0
0
0
CQFP256
T6HP12
101
240
0
RT54SX32*
CQFP208
T6JP01A
76
615
0
0
46740
RT54SX32*
CQFP256
T6JP05A
5
615
0
0
3075
Product
Package
Wafer Lot
RT54SX16*
CQFP256
P05
RT54SX16
CQFP256
P04
RT54SX16
PQFP208
RT54SX16
Date
Code
9931
TOTAL Units for 0.6 µm RTSX FPGA =
386
1000
2000
Unit
Hours
47355
0
92000
81000
24240
Total Test Time Hours =
294410
TOTAL Failures for RTSX 0.6 µm FPGA = 0
Note: * Tested at 150ºC. Equivalent hours corresponding to 125ºC were used to calculate the FIT rates.
24
SoC Reliability Report
0.45 µm CSM FPGA Reliability Summary
Table 23: High Temperature Operating Life (HTOL)
Test Hours / Failures
Number
of Units
Test
Time
168
500
1000
2000
Unit
Hours
2ACR23038.3
30
2000
0
0
0
0
60000
PLCC84
2ACR23038.3
45
2000
0
0
0
0
90000
A40MX04
PLCC84
2ACT160021
77
2000
0
0
0
0
154000
A40MX04
PLCC84
2ACU040091
77
2000
0
0
0
0
154000
A40MX04
PLCC84
2XZR24206.5
29
2000
0
0
0
0
58000
A42MX16
PLCC84
2ACU492561
148
1000
0
0
0
A42MX16
PQFP160
2XZR25104.1
26
2000
0
0
0
A42MX24
PQFP160
2XYE254371
0920
77
1500
0
0
0
115500
A42MX24
PQFP160
2XYE254371
0920
80
1000
0
0
0
80000
A42MX361
CQFP208
2ACZ310131
77
615
0
0
0
47355
A42MX361,2
CQFP256
2ACT363611
77
615
(1)2
0
A42MX36
PQFP208
2ACT10221
27
2000
0
0
0
A42MX361
CQFP208
2ACU523241
0019
45
615
0
0
0
27675
A42MX36
CQFP208
2ACC512631
0733
77
1000
–
–
13
76000
A42MX36
CQFP256
2ACH323581
1212
80
1000
0
0
0
80000
A42MX36
CQFP256
2ACG311291
1116
79
1000
0
0
0
79000
A42MX36
CQFP208
2MPK091041
1330
80
1000
0
0
0
80000
Product
Package
Wafer Lot
A40MX04
PLCC84
A40MX04
Date
Code
9919
0012
TOTAL Units for 0.45 µm FPGA =
1131
148000
0
52000
47355
0
Total Test Time Hours =
54000
1402885
TOTAL Failures for 0.45 µm FPGA = 1
Notes:
1. Tested at 150ºC. Equivalent hours corresponding to 125ºC were used to calculate the FIT rates.
2. Product A42MX36, run 2ACT363611, at 168 hours, unit failed was verified to be ESD/EOS.
3. Product A42MX36, run 2ACC512631, 1 failure observed after 1000 hrs. pull point (no intermediate pull points), counted
towards device FIT (used Ea of 0.7eV as FA inconclusive, root cause could not be established). Report available upon
request.
SoC Reliability Report
25
Table 24: Biased Humidity (HAST)
Test Hours / Failures
Number
of Units
Test Time
50
100
2ACR23038.3
81
100
0
0
8100
PLCC84
2ACR23039.1
25
100
0
0
2500
A42MX09
PQFP160
2ACT110181
30
100
0
0
3000
A42MX16
PQFP160
2XZR25104.1
25
100
0
0
2500
A42MX36
BGA272
2ACT180141
76
100
0
0
7600
A42MX36
PQFP208
2ACT110221
27
50
0
Product
Package
Wafer Lot
A40MX04
PLCC84
A40MX04
Date
Code
TOTAL Units for 0.45 µm FPGA =
264
200
Unit
Hours
250
1350
Total Test Time Hours =
25050
TOTAL Failures for 0.45 µm FPGA = 0
Table 25: Unbiased Humidity
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test Time
50
100
A42MX09
PQFP160
2ACT052662
9817
30
100
0
0
3000
A42MX24
PQFPG2081,2
2ACD420191
0806
47
100
0
0
4700
TOTAL Units for 0.45 µm FPGA =
77
200
250
Total Test Time Hours =
Unit
Hours
7700
TOTAL Failures for 0.45 µm FPGA = 0
1. G indicates lead-free.
2. Unbiased HAST (JESD22 A118), 130ºC and RH = 85%.
Table 26: Temperature Cycle
Number of Cycles / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
200
500
1000
2000
Cycles
(–65°C – +150°C)
A40MX04
PLCC84
2XZR24206.5
26
1000
0
0
0
26000
A40MX04
PLCC84
2ACR23038.3
26
1000
0
0
0
26000
A42MX09
PQFP160
2ACT210121
30
1000
0
0
0
30000
A42MX16
PQFP160
2XZR25104.1
26
1000
0
0
0
26000
A42MX36
PQFP208
2ACT110221
27
1000
0
0
0
27000
A42MX24
PQFPG208*
2ACD420191
47
1000
0
0
0
47000
0806
TOTAL Units for 0.45 µm FPGA =
182
Total Test Cycles =
182000
TOTAL Failures for 0.45 µm FPGA = 0
Note: *G indicates lead-free.
26
SoC Reliability Report
0.45 µm UMC FPGA Reliability Summary
Table 27: High Temperature Operating Life (HTOL)
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
168
500
1000
A40MX04
PLCC84
HKJAH00
0736
90
1000
0
0
0
90000
A42MX24
PQFP208
HLF8Q0G
0941
80
1000
0
0
0
80000
A42MX24
PQFP208
HMGN000
1111
79
2000
0
0
0
0
158000
A42MX24
PQFP208
HPY9H00
1309
80
2000
0
0
0
0
160000
TOTAL Units for 0.45 µm FPGA =
329
2000
Total Test Time Hours =
Unit
Hours
488000
TOTAL Failures for 0.45 µm FPGA = 0
Table 28: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test Time
50
100
A40MX04
PLCC84
HKJAH00
0736
82
100
0
0
820
A42MX24
PQFP208
HKJNS00
0734
50
100
0
0
500
TOTAL Units for 0.45 µm FPGA =
132
200
250
Total Test Time Hours =
Unit
Hours
1320
TOTAL Failures for 0.45 µm FPGA = 0
Table 29: Temperature Cycle (TC), –55°C to +125°C
Number of Cycles / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
200
500
1000
A40MX04
PLCC84
HKJAH00
0736
85
1000
0
0
0
85000
A42MX24
PQFP208
HKJNS00
0734
80
1000
0
0
0
80000
TOTAL Units for 0.45 µm FPGA =
165
2000
Total Test Cycles =
Cycles
165000
TOTAL Failures for 0.45 µm FPGA = 0
Table 30: High Temperature Storage (HTS), 150°C
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test Time
200
500
1000
A40MX04
PLCC84
HKJAH00
0736
80
1000
0
0
0
80000
A42MX24
PQFP208
HKJNS00
0734
80
1000
0
0
0
80000
TOTAL Units for 0.45 µm FPGA =
160
2000
Total Test Time Hours =
Unit
Hours
160000
TOTAL Failures for 0.45 µm FPGA = 0
SoC Reliability Report
27
0.35 µm FPGA Reliability Summary
Table 31: High Temperature Operating Life (HTOL)
Test Hours / Failures
Number
of Units
Test
Time
168
500
1000
2ACW210771
105
615
(2)
0
0
PQFP208
2ACT110031
74
2000
0
0
0
A54SX16
PQFP208
2XZR402521
38
1000
0
0
0
38000
A54SX16
PQFP208
2ACU420072
99
1000
0
0
0
99000
A54SX16
PQFP208
2ACT100081
81
2000
0
0
0
A54SX16P
PQFP208
2ACT141821
45
1000
0
0
0
A54SX321
CQFP208
2ACU390881
45
615
0
0
27675
A54SX321
CQFP208
2ACT500021
45
615
0
0
27675
A54SX32
PQFP208
2ACV103721
88
1000
0
0
0
A54SX32
PQFP208
2XZT091468
43
2000
0
0
0
A54SX32
PQFP208
2ACT330111,
2ACT330101,
2HCU462006
88
1000
0
0
0
88000
TOTAL Units for 0.35 µm FPGA =
751
Total Test Time Hours =
809350
Product
Package
Wafer Lot
A54SX161,2
CQFP208
A54SX16
Date
Code
2000
Unit
Hours
0
148000
0
162000
45000
88000
0
86000
TOTAL Failures for 0.35 µm FPGA = 0
Notes:
1. Tested at 150ºC. Equivalent hours corresponding to 125ºC were used to calculate the FIT rates.
2. Product A54SX16, run 2ACW21O771; the group C lot was started with 77 units and two devices failed during functional
test. The failure analysis with the two failure devices was started to narrow down the failure location and find the root
cause of failure. Bench setup testing was done to reproduce the failure seen on the tester. Unfortunately, the two
devices in FA, plus one more reference unit from the same lot, were misplaced in the lab and got lost during the
Microsemi SoC Products Group (formerly Actel) facility move from Sunnyvale to Mountain View. The devices may have
been scrapped by mistake as reject parts. Therefore, the failure analysis could not be continued. An additional 29 units
from the same inspection lot were submitted for full group C process and all passed. As a result, this group C
qualification was passed with 105(2) result based on the LTPD(5) criteria. Actel TRB approved this group C result, and
agreed this was a one-time accident due to the facility move, which should not recur with the currently established
handling procedure for FA devices.
Table 32: Low Temperature Operating Life (LTOL)
Test Hours / Failures
Product
Package
A54SX32
PQFP208
Wafer Lot
Date
Code
2ACT330111,
2ACT330101,
2HCU462006
TOTAL Units for 0.35 µm FPGA =
Number
of Units
Test
Time
168
500
1000
88
1000
0
0
0
88
2000
Unit Hours
88000
Total Test Time Hours =
88000
TOTAL Failures for 0.35 µm FPGA = 0
28
SoC Reliability Report
Table 33: Biased Humidity (HAST)
Test Hours / Failures
Date
Code
Number
of Units
Test
Time
50
100
2ACU211641
9941
9942
9943
81
100
0
0
8100
PQFP208
2ACU241341
2ACU420072
2ACU222448
9947
0002
0004
84
100
0
0
8400
BGA329
2ACU410201
0013
0014
0015
76
100
0
0
7600
Product
Package
Wafer Lot
A54SX32
BGA329
A54SX16
A54SX32
TOTAL Units for 0.35 µm FPGA =
241
200
250
Total Test Time Hours =
Unit
Hours
24100
TOTAL Failures for 0.35 µm FPGA = 0
Table 34: Unbiased Humidity (HAST)
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
50
100
A54SX16
PQFP208
2ACU241341
2ACU420072
2ACU222448
9947
0002
0004
84
100
0
0
TOTAL Units for 0.35 µm FPGA =
84
200
250
Unit
Hours
8400
Total Test Time Hours =
8400
TOTAL Failures for 0.35 µm FPGA = 0
Table 35: Temperature Cycle
Number of Cycles / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
200
500
1000
2000
Cycles
(–65°C – +150°C)
A54SX16
A54SX32
A54SX32
PQFP208
BGA329
PQFP208
2ACU241341
9947
2ACU420072
0002
2ACU222448
0004
2ACU410201
0013
2ACU410201
0014
2ACU410201
0015
2HCU462006
0010
2HCU410216
0017
2HCV022691
0017
TOTAL Units for 0.35 µm FPGA =
93
1000
0
0
0
93000
76
1000
0
0
0
76000
76
1000
0
0
0
76000
245
Total Test Cycles =
245000
TOTAL Failures for 0.35 µm FPGA = 0
SoC Reliability Report
29
0.25 µm MEC FPGA Reliability Summary
Table 36: High Temperature Operating Life (HTOL)
Test Hours / Failures
Number
of Units
Test
Time
168
500
1000
T25J002
80
1000
0
0
0
80000
PQFP208
T25JP03
88
1000
0
0
0
88000
A54SX32A
PQFP208
T25J002, P05,
P04
50
500
0
0
25000
A54SX72A1,2
CQFP208
T25K065
77
615
(1)
0
47355
A54SX72A
PQFP208
T25K001
88
1000
0
0
A54SX72A
PQFP208
T25K065
77
615
0
0
A54SX72A
PQFP208
T25KP04
28
1000
0
0
0
RT45SX32S
CQFP208
T25JSP03
8
2000
0
0
0
0
16000
RT54SX32S
CQFP208
T25JS001
8
4000
0
0
0
0
32000
RT54SX32S
CQFP208
T25JS001
25
1000
0
0
0
25000
RT54SX32S
CQFP208
T25JSP03
24
1000
0
0
0
24000
RT54SX32S1
CQFP208
T25JSP03
52
615
0
0
RT54SX32S
CQFP208
T25JS004
22
2000
0
0
0
RT54SX32S
CQFP208
BP1037101
100
1000
0
0
0
100000
RT54SX32S
CQFP208
T25JS004
20
1000
0
0
0
20000
RT54SX32S1
CQFP256
T25JSP03
76
615
0
0
RT54SX32S3
CQFP208
BP0083301,
T25JS004,
T25JS001(KM1)
150
1000
0
1
1(2)
149250
RT54SX72S
CQFP208
T25KS005
22
1000
0
0
0
22000
RT54SX72S1,2
CQFP256
T25KS005
80
615
0
(1)
Product
Package
Wafer Lot
A54SX32A
PQFP208
A54SX32A
Date
Code
TOTAL Units for 0.25 µm MEC FPGA =
1075
2000
0
Unit
Hours
88000
47355
28000
31980
0
44000
46740
49200
Total Test Time Hours =
963880
TOTAL Failures for 0.25 µm MEC FPGA = 2
Notes:
1. Tested at 150ºC. Equivalent hours corresponding to 125ºC were used to calculate the FIT rates.
2. Product A54SX72A, run T25K065, and product RT54SX72S, run T25KS005; the failures determined were EOS.
3. K-antifuse failed at 250 hours, F-antifuse failure at 1000 hours, and 2 ESD failures at 1000 hours.
30
SoC Reliability Report
Table 37: Low Temperature Operating Life (LTOL)
Test Hours / Failures
Test
Time
168
500
1000
80
1000
0
0
0
80000
T25JP03
88
1000
0
0
0
88000
PQFP208
T25J002, P05, P04
50
500
0
0
25000
RT54SX32S*
CQFP208
BP0083301,
T25JS004,
T25JS001(KM1)
149
250
0
1
37250
A54SX72A
PQFP208
T25K001
88
1000
0
0
0
88000
A54SX72A
PQFP208
T25KP04
28
1000
0
0
0
28000
Total Test Time Hours =
346250
Product
Package
Wafer Lot
A54SX32A
PQFP208
T25J002, P05, P04
A54SX32A
PQFP208
A54SX32A
Date Number
Code of Units
TOTAL Units for 0.25 µm MEC FPGA =
483
Unit
Hours
2000
TOTAL Failures for 0.25 µm MEC FPGA = 0
Note: *One K-antifuse failed at 250 hours
Table 38: Biased Humidity (HAST)
Test Hours / Failures
Product
Package
Wafer Lot
A54SX32A
PQFP208
T25J002, P05, P04
A54SX72A
PQFP208
T25KP04
Date Number
Code of Units
TOTAL Units for 0.25 µm MEC FPGA =
Test
Time
50
100
80
100
0
0
8000
28
100
0
0
2800
108
200
250
Total Test Time Hours =
Unit
Hours
10800
TOTAL Failures for 0.25 µm MEC FPGA = 0
Table 39: Temperature Cycle
Number of Cycles / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
200
500
1000
2000
Cycles
(-65°C – +150°C)
A54SX32A
PQFP208
T25J002, P05, P04
80
1000
0
0
0
80000
A54SX72A
PQFP208
T25KP04
28
1000
0
0
0
28000
TOTAL Units for 0.25 µm MEC FPGA =
108
Total Test Cycles =
108000
TOTAL Failures for 0.25 µm MEC FPGA = 0
SoC Reliability Report
31
0.25 µm Flash FPGA Reliability Summary
Table 40: High Temperature Operating Life (HTOL)
Test Hours / Failures
Date
Code
Number
of Units
Test
Time
168
500
1000
0039,
0040
76
1000
0
0
0
76000
ZA051811
80
1000
0
0
0
80000
BGA456
ZA027920
28
1000
0
0
0
28000
A500K130
BGA272
ZA051811
120
1000
0
0
0
120000
A500K130
BGA272
ZA051811
80
1000
0
0
0
80000
A500K130
BGA272
ZA049887
80
1000
0
0
0
80000
Product
Package
Wafer Lot
A500K130
BGA272
ZA026941
ZA035953
ZA034979
A500K130
BGA272
A500K270
TOTAL Units for 0.25 µm Flash FPGA =
464
2000
Total Test Time Hours =
Unit
Hours
464000
TOTAL Failures for 0.25 µm Flash FPGA = 0
Table 41: Low Temperature Operating Life (LTOL)
Test Hours / Failures
Product
Package
Wafer Lot
A500K130
BGA272
ZA026941
ZA035953
ZA034979
Date
Code
Number
of Units
Test
Time
168
500
1000
0039,
0040
76
1000
0
0
0
TOTAL Units for 0.25 µm Flash FPGA =
76
2000
Unit
Hours
76000
Total Test Time Hours =
76000
TOTAL Failures for 0.25 µm Flash FPGA = 0
Table 42: Endurance
Number of Cycles / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
50
100
500
1000
Cycles
Room Temperature
A500K130
CGA272
ZA026941
15
TOTAL Units for 0.25 µm Flash FPGA =
15
50
0
750
Total Number of Cycles =
750
TOTAL Failures for 0.25 µm Flash FPGA = 0
32
SoC Reliability Report
Table 43: Retention 225°C Unbiased 100% Programmed
Test Hours / Failures
Product
Package
Wafer Lot
A500K130
CGA272
ZA026941
Date
Code
TOTAL Units for 0.25 µm Flash FPGA =
Number
of Units
Test
Time
168
500
1000
9
1000
0
0
0
9000
Total Test Time Hours =
9000
9
2000
Unit
Hours
TOTAL Failures for 0.25 µm Flash FPGA = 0
Table 44: Retention 225°C Unbiased 100% Erased
Test Hours / Failures
Product
Package
Wafer Lot
A500K130
CGA272
ZA026941
Date
Code
TOTAL Units for 0.25 µm Flash FPGA =
Number
of Units
Test Time
168
500
1000
8
1000
0
0
0
8000
Total Test Time Hours =
8000
8
2000
Unit
Hours
TOTAL Failures for 0.25 µm Flash FPGA = 0
SoC Reliability Report
33
0.25 µm UMC FPGA Reliability Summary
Table 45: CMOS Reliability – High Temperature Operating Life (HTOL)
Test Hours / Failures
Product
Package Wafer Lot
Date
Code
Number
of Units
Test
Time
168
500
1000
2000
3000
Unit
Hours
0
712402
RTSX32SU1 CQFP208
D122H1
0434
149
4,781
0
0
0
0
RTSX32SU1 CQFP208
D122H1
0434
1
1,912
0
0
0
0
RTSX32SU1 CQFP208
D122H1
0434
150
4,781
0
0
0
0
0
717182
RTSX32SU1 CQFP208
D122H1,
D1JW21
0434,
0442
2
10,412
0
0
0
0
0
20824
RTSX32SU1 CQFP208
D122H1,
D1JW21
0434,
0442
148
31,237
0
0
0
0
0
4623009
RTSX72SU1 CQFP208 D1AYH1,
D1KT11
0519,
0445
1
15,618
0
0
0
0
0
15618
RTSX72SU1 CQFP208 D1AYH1,
D1KT11
0519,
0445
73
31,237
0
0
0
0
0
2280268
RTSX72SU1 CQFP208 D1AYH1,
D1KT11
0519,
0445
5
20,824
0
0
0
0
0
104122
1912
RTSX32SU1 CQFP208
D110A1
–
68
0.91
62
RTSX72SU1 CQFP208
D0YMJ1
–
32
0.91
29
RTSX32SU1 CQFP208
D122H1
–
100
0.91
91
RTSX72SU1 CQFP256
DIJW01
–
35
54
1886
RTSX32SU1 CQFP256
D1HLK1
–
100
54
5389
RTSX32SU1 CQFP208
D110A1
–
100
4.2
420
RTSX32SU1 CQFP208
D110A1
–
100
162
16168
RTSX32SU1 CQFP208
D110A1
–
98
1.83
179
RTSX32SU1 CQFP208
D110A1
–
100
1.83
183
RTSX72SU1 CQFP208
D0YMJ1
–
68
0.91
62
RTSX72SU1 CQFP208
D0Y311
–
100
0.9
91
RTSX32SU1 CQFP256
D122H1
0441
100
54
5389
Notes:
1. As part of antifuse reliability testing HTOL tests were performed on RT54SX32-SU and RT54SX72-SU (UMC 0.25 m) at
varying temperatures and voltages. HTOL data from these tests has been summarized above for CMOS FIT calculation
based on the following assumptions
• Voltage Acceleration:
· Tests where VCCA > VCCA(max) (3.0 V) have been ignored
· Tests where VCCA = 2.5 V to 3.0 V, voltage acceleration factor for these tests was assumed to be 1.
• Temperature Acceleration:
· Stress Temperature = Junction Temperature (i.e., Tstress = TJ).
· The burn-in hours have been normalized to a TJ of 125ºC (i.e., 106 units @ TJ 145ºC burn-in time 168 hrs is
equivalent to 106 units @ TJ 125ºC burn-in time 446.105 hrs)
2. ESD failures are represented in parentheses.
34
SoC Reliability Report
Table 45: CMOS Reliability – High Temperature Operating Life (HTOL) (continued)
Test Hours / Failures
Product
Package Wafer Lot
Date
Code
Number
of Units
Test
Time
168
500
1000
2000
3000
Unit
Hours
RTSX32SU1 CQFP208
D19S61
0450
100
54
5389
RTSX72SU1 CQFP208
D1AYH1
–
100
0.91
91
RTSX32SU1 CQFP208
D1AYJ1
0450
100
54
5389
RTSX32SU1 CQFP208
D1AYJ1
0502
100
54
5389
RTSX72SU1 CQFP208
D1HLH4
0504
100
54
5389
RTSX72SU1 CQFP208
D1HLJ1
0446
100
54
5389
RTSX32SU1 CQFP256
D1HLK1
0507
100
54
5389
RTSX72SU1 CQFP208
D1JW01
0501
100
54
5389
RTSX32SU1 CQFP208
D1JW21
0451
100
54
5389
RTSX32SU1 CQFP208
D1JW21
0452
100
54
5389
RTSX32SU1 CQFP208
D1JW21
0511
100
54
5389
RTSX32SU1 CQFP208
D1JW21
0512
100
54
5389
RTSX32SU1 CQFP208
D1JW21
0523
100
54
5389
RTSX32SU1 CQFP256
D1JW21
0518
100
54
5389
RTSX72SU1 CQFP208
D1KT11
0515
100
54
RTSX72SU1 CQFP208
D1MM81
0519
100
54
5389
RTSX72SU1 CQFP256
D1MM91
0513
100
54
5389
RTSX72SU1 CQFP256
D1N2W1
0520
100
54
5389
RTSX72SU1 CQFP256
D1N8A1
0517
100
54
5389
RTSX32SU1 CQFP256
D1N8F1
0518
100
54
5389
RTSX72SU1 CQFP256
D1P8T1
0522
100
54
5389
RTSX32SU1 CQFP256 D1P8W.1
0531
100
54
5389
RTSX32SU1 CQFP208
0450
80
321
D1AYJ1
(1)
0
5389
25664
Notes:
1. As part of antifuse reliability testing HTOL tests were performed on RT54SX32-SU and RT54SX72-SU (UMC 0.25 m) at
varying temperatures and voltages. HTOL data from these tests has been summarized above for CMOS FIT calculation
based on the following assumptions
• Voltage Acceleration:
· Tests where VCCA > VCCA(max) (3.0 V) have been ignored
· Tests where VCCA = 2.5 V to 3.0 V, voltage acceleration factor for these tests was assumed to be 1.
• Temperature Acceleration:
· Stress Temperature = Junction Temperature (i.e., Tstress = TJ).
· The burn-in hours have been normalized to a TJ of 125ºC (i.e., 106 units @ TJ 145ºC burn-in time 168 hrs is
equivalent to 106 units @ TJ 125ºC burn-in time 446.105 hrs)
2. ESD failures are represented in parentheses.
SoC Reliability Report
35
Table 45: CMOS Reliability – High Temperature Operating Life (HTOL) (continued)
Test Hours / Failures
Product
Package Wafer Lot
Date
Code
Number
of Units
Test
Time
168
500
1000
2000
3000
Unit
Hours
RTSX72SU1 CQFP208
D1HLJ1
–
79
321
0
25343
RTSX72SU1 CQFP208
D0Y311
0410
133
1,000
(1)
133000
RTSX72SU1 CQFP208
D0Y311
0410
8
168
0
1344
RTSX32SU1 CQFP208
D19S61
0436
80
615
(1)
49181
RTSX32SU1 CQFP208
D110A1
–
135
168
0
22680
RTSX32SU1 CQFP256
D122H1
–
100
1000
0
0
0
100000
RTSX32SU1 CQFP208
D1AYJ1
0504
22
1000
0
0
0
22000
RTSX32SU1 CQFP208 D1JW21,
D1AYJ1
0519,
0502
150
750
0
0
–
77
1000
0
0
RTSX32SU1 CQFP208 D1JW21,
D1AYJ1
0519,
0502
150
750
0
0
RTSX72SU1 CQFP208
D1MM81
0534
15
1000
0
0
0
15000
RTSX72SU1 CQFP256
D1JW01
0501
20
1000
0
0
0
20000
RTSX72SU1 CQFP208
D1N8A1
0641
15
1000
0
0
0
15000
RTSX72SU1 CQFP256
D1N8A1
0831
12
1000
0
0
0
12000
RTSX72SU1 CQFP256
D1SG01
0939
100
168
0
RTSX32SU1 CQFP208
D1P8W1
0842
14
2000
0
0
0
0
RTSX72SU
CQFP256
D303Y1
0720
80
6000
0
0
0
0
RTSX72SU
CQFP208
D1SG11
0947
24
2000
0
0
0
0
48000
RTSX72SU
CQFP84
D1RH51
1007
24
2000
0
0
0
0
48000
RTSX72SU
CQFP256
D6AA61
1351
80
1000
0
0
0
RTSX72SU1 CQFP256
D1N2W1
TOTAL Units for 0.25 µm FPGA =
5128
112500
0
77000
112500
16800
28000
0
480000
8000
Total Test Time Hours =
10062558
TOTAL Failures for 0.25 µm FPGA = 0 CMOS failures observed
Notes:
1. As part of antifuse reliability testing HTOL tests were performed on RT54SX32-SU and RT54SX72-SU (UMC 0.25 m) at
varying temperatures and voltages. HTOL data from these tests has been summarized above for CMOS FIT calculation
based on the following assumptions
• Voltage Acceleration:
· Tests where VCCA > VCCA(max) (3.0 V) have been ignored
· Tests where VCCA = 2.5 V to 3.0 V, voltage acceleration factor for these tests was assumed to be 1.
• Temperature Acceleration:
· Stress Temperature = Junction Temperature (i.e., Tstress = TJ).
· The burn-in hours have been normalized to a TJ of 125ºC (i.e., 106 units @ TJ 145ºC burn-in time 168 hrs is
equivalent to 106 units @ TJ 125ºC burn-in time 446.105 hrs)
2. ESD failures are represented in parentheses.
36
SoC Reliability Report
Table 46: CMOS Reliability Low Temperature Operating Life (LTOL)
Test Hours / Failures
Wafer Lot
Date Code
Number
of Units
Test
Time
168
500
RTSX32SU* CQFP208
D122H1
0434
149
500
0
0
74500
RTSX32SU* CQFP208
D122H1
0434
150
500
0
0
75000
RTSX72SU* CQFP208
D1AYH1,
D1KT11
0445, 0519
75
6000
0
0
0
0
0
450000
RTSX32SU* CQFP208
D122H1,
D1JW21
0434, 0442
152
5000
0
0
0
0
0
760000
RTSX32SU* CQFP208
D122H1,
D1JW21
0434, 0442
2
4000
0
0
0
0
0
8000
RTSX72SU* CQFP256
D0Y311
0410
134
500
0
0
RTSX72SU* CQFP256
D0Y311
0410
8
168
0
RTSX32SU* CQFP256
D19S61
0436
6
1000
0
0
RTSX72SU* CQFP208
D0YMJ1
---
100
500
0
0
RTSX72SU* CQFP208
D0Y311
---
100
168
0
16800
RTSX72SU* CQFP208
D1AYH1
---
100
168
0
16800
RTSX32SU* CQFP208
D122H1
---
100
168
0
16800
RTSX32SU* CQFP208
D1JW21,
D1AYJ1
0519, 0502
150
1000
0
0
RTSX32SU* CQFP208
D1JW21,
D1AYJ1
0519, 0502
150
500
0
0
TOTAL Units for 0.25 µm FPGA =
1376
Product
Package
1000
2000
Unit
Hours
3000
67000
1344
0
6000
50000
0
150000
75000
Total Test Time Hours = 1767244
TOTAL Failures for 0.25 µm FPGA = 0 CMOS failures
Note: *LTOL data from antifuse reliability testing performed on RT54SX32-SU and RT54SX72-SU (UMC 0.25 m).
Table 47: Temperature Cycle
Number of Cycles / Failures
Product
Package
Number
of Units
Wafer Lot
Test
Cycles
200
500
1000
2000
Cycles
(–65°C – +150°C)
RTSX32SU
CQFP208
D110A1
68
100
6800
RTSX72SU
CQFP208
D0YMJ1
68
100
6800
RTSX32SU
CQFP208
D110A11
135
100
13500
TOTAL Units for 0.22 µm FPGA =
271
Total Test Cycles =
27100
TOTAL Failures for 0.25 µm FPGA = 0
SoC Reliability Report
37
Antifuse Reliability Overview
Failure rates described in this section refer only to the antifuse portion for UMC 0.25 µm RTSX32-SU and
RTSX72-SU Microsemi SoC Products Group (formerly Actel Corporation) FPGA products programmed
using the standard programming algorithm.
In the ideal case, all the testing would have been performed on these devices alone. However because of
their high cost and lower availability, additional lifetests have been performed on the commercial device
type A54SX72A (UMC 0.22 µm). Antifuse failures have been observed in both the military (RTSX32-SU
and RTSX72-SU) devices as well as in the commercial (A54SX72A) devices.
Antifuse FIT Rate Calculator
A failure rate calculator in the form of an excel spreadsheet has been developed by The Aerospace
Corporation. The statistical procedure used in the calculator to analyze the lifetest data is called the
Maximum Likelihood Method (MLE). The model assumed for antifuse failures is a Weibull cumulative
failure distribution as a function of time t (in hours) for n antifuses (EQ 3). The scale factor is given by
(hours) and the shape factor is given by (dimensionless).
t
F(t) = 1 – exp – n ---
EQ 3
The MLE shape factor was found to be less than one for the antifuses, describing a decreasing failure rate
situation. A cumulative failure time model for the antifuse types where failures have been detected is
therefore given by
•
n1 and 1 for the number and scale factor respectively for the failing antifuses in military FPGA
•
n2 and 2 for the number and scale factor respectively for the failing antifuse in commercial FPGA
•
where as the same shape factor has been assumed for both military and commercial categories.
The maximum likelihood method was programmed in S-Plus (http://www.insightful.com) to determine
the coefficients 1, 2, and for both military and commercial FPGAs in one pass. A simultaneous
estimate of all three parameters was made with all available data.
The calculator allows the user to describe a particular FPGA design, along with mission parameters, and
computes an averaged failure rate for the mission.
Average antifuse FIT for UMC 0.25 µm RTSX-SU FPGA products at a 60% confidence bound is a FIT of
17.
38
•
FIT calculator version used 2.12 (UMC Standard Algorithm FIT Rate Calculator Data v2.12.xls,
updated May 2008)
•
Total of 1 failure observed for medium timing perceptibility
•
Parts are programmed with standard programming algorithm
•
Standard Aerospace Industry Design used: Microsemi SoC has provided design characteristics of
42 different Aerospace Industry FPGA programming designs. To provide a guideline, an average
or standard design has been obtained by simply taking the average of the antifuses of the various
types and using in the FIT rate calculator.
•
Screen hours 500
•
10 years of mission life
SoC Reliability Report
Reliability Summary – Silicon Sculptor Programming
Software
The following table shows the number of unit-hours of life test data accumulated on Radiation-Tolerant
FPGAs programmed with specific revisions of Silicon Sculptor programming software. Life tests are
performed for several reasons: as part of device qualification (1,000 hours or 6,000 hours), as
customer-specific life tests (1,000 hours or 2,000 hours), as part of Group C life test (1,000 hours or 2,000
hours), or as part of our standard Enhanced Lot Acceptance (ELA) testing which is performed on samples
from every single wafer lot of RT FPGAs (168 hours). Microsemi’s official position is that customers are
recommended to use the latest version of software. However, customers who are unable to upgrade to use
the latest version of the software may find the life test data useful to determine how much reliability data is
accumulated on each version of the programming software.
Table 48: Unit-hours of Life Test Data Accumulated on Radiation-Tolerant FPGAs
Silicon Sculptor S/W Version
RTSX72SU
Total per Version
V4.78.1
16,800
16,800
V4.80.0
33,600
33,600
64,800
81,600
16,800
16,800
V5.2.0
RTSX32SU
16,800
V5.4.1
V5.6.0
48,000
48,000
V5.8.1
16,800
16,800
V5.18.1
2,856
2,856
V5.22.0
64,800
64,800
V5.22.2
8,000
8,000
V5.22.3
8,000
8,000
V5.22.4
16,800
164,000
180,800
Total per Device
114,400
363,656
478,056
SoC Reliability Report
39
0.22 µm UMC FPGA Reliability Summary
Table 49: CMOS High Temperature Operating Life (HTOL)
Test Hours / Failures
Number
of Units
Test
Time
168
DC183 0012
50
1000
0
0
0
50000
PQFP208
D1X181
90
1000
0
0
0
90000
A54SX08A
PQFP208
D1X191
84
1000
0
0
0
84000
A54SX08A
PQFP208
D7K052 W 2
90
1000
0
0
0
90000
A54SX32A
PQFP208
D7682 14.15 0028
100
1000
0
0
0
100000
A54SX32A and
A54SX08A
PQFP208
D7682.14 (HS),
D7766.12 (HS),
D7682.15 (FS),
D7766.19 (FS),
DC183(HS)
150
3340
0
0
0
A54SX32A
CQFP208
D5GTW1
80
1000
0
0
0
A54SX72A
PQFP208
D03TC1
101
2000
0
0
0
A54SX72A
PQFP208
D4F117
38
168
0
6384
A54SX72A
PQFP208
DCT03.1
22
168
0
3696
A54SX72A
FC4841
D55011
26
168
0
4368
A54SX72A
PQFP208
D09A21
77
516
0
A54SX72A
PQFP208
D09A21
19
168
0
3192
A54SX72A
PQFP208
D03TC1(74), D0KA91
(26)
100
168
0
16800
A54SX72A
PQFP208
DOKA91
100
168
0
16800
A54SX72A
PQFP208
DOKA91
100
168
0
16800
A54SX72A
PQFP208
DCT03.1
90
168
0
15120
A54SX72A
PQFP208
DCT03.1
69
120
Product
Package
Wafer Lot
A54SX08A
PQFP208
A54SX08A
Date
Code
1125
500 1000
0
2000
0
Unit
Hours
501000
80000
0
202000
39732
8280
Notes:
1. Engineering package.
2. As part of antifuse reliability testing, HTOL tests were performed on A54SX72A (UMC 0.22 µm) at varying temperatures
and voltages. HTOL data from these tests has been summarized above for CMOS FIT calculation based on the
following assumptions.
• Voltage Acceleration:
· Tests where VCCA > VCCA(max) (3.0 V) have been ignored
· Tests where VCCA = 2.5 V to 3.0 V, voltage acceleration factor for these tests was assumed to be 1.
• Temperature Acceleration:
· Stress Temperature = Junction Temperature (i.e., Tstress = TJ).
· The burn-in hours have been normalized to a TJ of 125ºC (i.e., 106 units at TJ 145ºC burn-in time 168 hrs is
equivalent to 106 units at TJ 125ºC burn-in time, 446.105 hrs)
3. ESD/EOS represented in parentheses—High ICCA current detected, device fully functional, and meets all AC
specifications.
40
SoC Reliability Report
Table 49: CMOS High Temperature Operating Life (HTOL) (continued)
Date
Code
Number
of Units
Product
Package
Wafer Lot
Test Hours / Failures
A54SX72A and
A54SX08A
PQFP208
D2E131, D2E151,
D1X171
76
1000
0
0
A54SX72A
PQFP208
DC0143
38
516
0
0
A54SX72A
CQFP256
D0F1J1.1
96
615
0
59040
A54SX72A
CQFP256
D0F1J1.1
23
615
0
14145
A54SX72A2
PQFP208
D1RCP1
106
446
0
47287
A54SX72A2
PQFP208
D1RCP1
108
1328
0
0
0
A54SX72A2
PQFP208
D1JTT1
108
2439
0
0
0
A54SX72A2
PQFP208
D14S71
1
813
0
0
A54SX72A2
PQFP208
D14S71
131
2439
0
0
A54SX72A2
PQFP208
D1RCP1
200
813
0
0
A54SX72A2
PQFP208
D1JTT1
1
446
0
A54SX72A2
PQFP208
D1JTT1
1
2159
0
0
0
0
2159
A54SX72A2
PQFP208
D1JTT1
97
2655
0
0
0
0
257573
A54SX72A2
PQFP208
D0H0N1
100
0.65
65
A54SX72A2
PQFP208
D03TC1
94
0.66
62
A54SX72A2
PQFP208
D09YJ1
100
2.05
205
A54SX72A2
PQFP208
D09YJ1
98
1.98
194
A54SX72A2
PQFP208
D09YJ1
139
1.97
274
A54SX72A2
PQFP208
D092A16
107
6.11
654
A54SX72A2
PQFP208
D146W1
104
42.8
4448
A54SX72A2
PQFP208
D0KA91
90
6.11
550
0
76000
19608
143391
0
263361
813
0
0
319447
162568
446
Notes:
1. Engineering package.
2. As part of antifuse reliability testing, HTOL tests were performed on A54SX72A (UMC 0.22 µm) at varying temperatures
and voltages. HTOL data from these tests has been summarized above for CMOS FIT calculation based on the
following assumptions.
• Voltage Acceleration:
· Tests where VCCA > VCCA(max) (3.0 V) have been ignored
· Tests where VCCA = 2.5 V to 3.0 V, voltage acceleration factor for these tests was assumed to be 1.
• Temperature Acceleration:
· Stress Temperature = Junction Temperature (i.e., Tstress = TJ).
· The burn-in hours have been normalized to a TJ of 125ºC (i.e., 106 units at TJ 145ºC burn-in time 168 hrs is
equivalent to 106 units at TJ 125ºC burn-in time, 446.105 hrs)
3. ESD/EOS represented in parentheses—High ICCA current detected, device fully functional, and meets all AC
specifications.
SoC Reliability Report
41
Table 49: CMOS High Temperature Operating Life (HTOL) (continued)
Date
Code
Number
of Units
Product
Package
Wafer Lot
A54SX72A2
PQFP208
D1JTT1
99
446
0
44165
A54SX72A2
PQFP208
D1AYG3
91
446
0
40596
A54SX72A2
PQFP208
D1JTT1
1
2092
0
0
0
0
2092
A54SX72A2
PQFP208
D1JTT1
100
2655
0
0
0
0
265539
A54SX72A2
PQFP208
D1JTT1
102
7966
0
0
0
0
812548
A54SX72A2
PQFP208
D1JTT1
108
2655
0
0
0
0
286782
A54SX72A2
PQFP208
D03TC1
101
2105
0
0
0
0
212602
A54SX72A2
PQFP208
D1JTT1
1
1774
0
0
0
A54SX72A2
PQFP208
D1JTT1
203
2655
0
0
0
A54SX72A2
PQFP208
D1AYG3
108
1328
0
0
0
143391
A54SX72A2
PQFP208
D1AYG3
108
1328
0
0
0
143391
A54SX72A2
PQFP208
D1AYG3
1
430
0
A54SX72A2
PQFP208
D1AYG3
107
1328
0
0
0
A54SX72A2
PQFP208
D1RCP1
108
5311
0
0
0
0
573564
A54SX72A2
PQFP208
D1RCP1
108
5311
0
0
0
0
573564
A54SX72A
CQFP208
D4TW61
1018
80
1000
0
0
0
A54SX72A
PQFP208
D54RJ1
1036
100
168
0
A54SX72A
CQFP208
D77SP1
1334
80
1000
0
TOTAL Units for 0.22 µm FPGA =
4810
Test Hours / Failures
1774
0
539044
430
142063
80000
16800
0
0
80000
Total Test Time Hours =
6658807
TOTAL Failures for 0.22 µm FPGA = 0 CMOS Failures
Notes:
1. Engineering package.
2. As part of antifuse reliability testing, HTOL tests were performed on A54SX72A (UMC 0.22 µm) at varying temperatures
and voltages. HTOL data from these tests has been summarized above for CMOS FIT calculation based on the
following assumptions.
• Voltage Acceleration:
· Tests where VCCA > VCCA(max) (3.0 V) have been ignored
· Tests where VCCA = 2.5 V to 3.0 V, voltage acceleration factor for these tests was assumed to be 1.
• Temperature Acceleration:
· Stress Temperature = Junction Temperature (i.e., Tstress = TJ).
· The burn-in hours have been normalized to a TJ of 125ºC (i.e., 106 units at TJ 145ºC burn-in time 168 hrs is
equivalent to 106 units at TJ 125ºC burn-in time, 446.105 hrs)
3. ESD/EOS represented in parentheses—High ICCA current detected, device fully functional, and meets all AC
specifications.
42
SoC Reliability Report
Table 50: Low Temperature Operating Life (LTOL)
Test Hours / Failures
Date Number
Code of Units
Test
Time
168
500
1000
DC183
0012
50
1000
0
0
0
50000
PQFP208
D7682 14.15
0028
100
1000
0
0
0
100000
A54SX72A
PQFP208
DC0143
38
168
0
A54SX72A and
A54SX08A
PQFP208
D2E13, D2E151,
D1X171
76
1000
0
A54SX72A
PQFP208
D4F117
38
168
0
6384
A54SX72A
PQFP208
DCT03.1
22
168
0
3696
A54SX72A1
PQFP208
D03TC1
101
2000
0
0
0
A54SX72A1
PQFP208
D1JTT1
108
1000
0
0
0
A54SX72A
PQFP208
D0KA91
85
168
0
14280
A54SX72A
FC4842
D55011
26
168
0
4368
PQFP208
DC183(HS)
150
1000
0
Product
Package
Wafer Lot
A54SX08A
PQFP208
A54SX32A
A54SX32A and
A54SX08A
TOTAL Units for 0.22 µm FPGA =
794
2000
Unit
Hours
6384
0
0
0
0
76000
0
202000
108000
150000
Total Test Time Hours = 721112
TOTAL Failures for 0.22 µm FPGA = 0
Notes:
1. LTOL data from antifuse reliability testing on A54SX72A (UMC 0.22 µm)
2. Engineering package
Table 51: Biased Humidity (HAST)
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
50
100
A54SX08A
PQFP208
DC183
0012
50
100
0
0
5000
A54SX32A
PQFP208
D7682 14.15
0028
100
100
0
0
10000
A54SX72A
PQFPG2081,2
D20CW1
0828
47
100
0
0
4700
TOTAL Units for 0.22 µm FPGA =
197
200
500
Total Test Time Hours =
Unit
Hours
19700
TOTAL Failures for 0.22 µm FPGA = 0
Notes:
1. G indicates lead-free.
2. Unbiased HAST (JESD22 A118), 130ºC and RH = 85%.
SoC Reliability Report
43
Table 52: Temperature Cycle
Number of Cycles / Failures
Product
Package
Date Number
Test
Code of Units Cycles
Wafer Lot
200
500
1000 2000
Cycles
(–65ºC – +150ºC)
A54SX08A
PQFP208
DC183
0012
50
1000
0
0
0
50000
A54SX32A
PQFP208
D7682 14.15
0028
100
1000
0
0
0
100000
A54SX72A
PQFP208
DC0143
38
500
0
0
A54SX72A + 08A
PQFP208
D2E131,D2E151,
D1X171
76
1000
0
0
A54SX72A
PQFP208
D4F117
38
500
0
0
A54SX72A
FC4841
D55011
26
1000
0
0
0
26000
A54SX32A + 08A
PQFP208
D7682.14 (HS),
D7766.12(HS)
D7682.15 (FS),
D7766.19(FS)
DC183(HS)
150
1000
0
0
0
150000
A54SX32A
TQFP176
BP34640-1 & D1JA1
0515,
0516,
0517
77
1000
0
0
0
77000
A54SX32A
PBGA329
D26E61
0610
22
1000
0
0
0
22000
A54SX72A
PQFPG2082
D20CW1
0828
46
1000
0
0
0
46000
TOTAL Units for 0.22 µm FPGA =
601
19000
0
76000
19000
Total Test Cycles = 563000
TOTAL Failures for 0.22 µm FPGA = 0
Notes:
1. Engineering package.
2. G indicates lead-free.
44
SoC Reliability Report
0.22 µm UMC Flash FPGA Reliability Summary
Table 53: High Temperature Operating Life (HTOL)
Test Hours / Failures
Number
of Units
Test
Time
168
500
1000
M279F, M279C
43
1000
0
0
0
43000
PBGA456
M1T74, M3AA6
86
1000
0
0
0
86000
APA750
PBGA456
MFJ2W, MFJ2S,
MFJ2T
77
1000
0
0
0
77000
APA750
PBGA456
MFRGH, MFPQ8
18
1000
0
0
0
18000
APA750
PBGA456
MFR6H, MFPQ8
18
1000
0
0
0
18000
APA750
PBGA456
MFJ2W, MFJ2T,
MFJ2S
77
1000
0
0
0
77000
APA7501
PBGA456
M3AA4
0336
84
2000
(1)
0
(1)
APA1000
CQFP352
MK3KA
0517
132
1115
0
0
0
147180
APA600
0
80000
Product
Package
Wafer Lot
APA1000
PBGA456
APA750
Date
Code
2000
0
Unit
Hours
167668
CQFP352
MR5T2
80
1000
0
0
2
CQFP208
MNRML
47
615
0
0
APA1000
CQFP352
MR91L
1025
24
2000
0
0
0
0
48000
APA300
CQFP208
MK91G
1036
24
2000
0
0
0
0
48000
APA300
PQFP208
MTG7J02
1045
77
168
0
APA1000
CQFP208
MWJ9W
1144
78
1000
0
0
0
78000
APA600
CQFP208
R00KY
1226
80
1000
0
0
0
80000
APA300
CQFP208
R21A5
1346
80
1000
0
0
0
80000
APA600
TOTAL Units for 0.22 µm Flash FPGA =
1025
28905
12936
Total Test Time Hours = 1089689
TOTAL Failures for 0.22 µm Flash FPGA = 0
Notes:
1. One device failed at 168 hours and it was confirmed due to ESD. The second one failed at 1500 hours and this failure
resulted from testing a feature that has been removed from silicon. The test programs have subsequently been
updated.
2. Tested at 150°C. Equivalent hours corresponding to 125° C were used to calculate the FIT rates.
Table 54: Low Temperature Operating Life (LTOL)
Test Hours / Failures
Number
of Units
Test
Time
168
500
1000
M297F, M279C
26
1000
0
0
0
26000
M1T74, M3AA6
51
1000
0
0
0
51000
TOTAL Units for 0.22 µm Flash FPGA =
77
Product
Package
Wafer Lot
APA1000
PBGA456
APA750
PBGA456
Date
Code
2000
Total Test Time Hours =
Unit
Hours
77000
TOTAL Failures for 0.22 µm Flash FPGA = 0
SoC Reliability Report
45
Table 55: Endurance
Number of Cycles / Failures
Product
Package
Date
Code
Wafer Lot
Number
of Units
Test
Cycles
50
100
500
1000
Cycles
Room Temperature
APA1000
CGA391
M297F, M279C
30
500
0
0
0
15000
APA750
CGA391
MFJ2W, MFJ2S, MFJ2T
30
500
0
0
0
15000
Total Test Cycles =
30000
TOTAL Units for 0.22 µm Flash FPGA =
60
TOTAL Failures for 0.22 µm Flash FPGA = 0
Table 56: Retention 225°C Unbiased 100% Programmed
Test Hours / Failures
Number
of Units
Test
Time
72
500
1000
3000
Unit
Hours
MAE49, MC147, MC148
73
3000
0
0
0
0
219000
MFJ2W, MFJ2S, MFJ2T
12
1000
0
0
0
Product
Package
Wafer Lot
APA1000
CGA391
APA750
CGA391
Date
Code
TOTAL Units for 0.22 µm Flash FPGA =
85
12000
Total Test Time Hours =
231000
TOTAL Failures for 0.22 µm Flash FPGA = 0
Table 57: Retention 225°C Unbiased 100% Erased
Test Hours / Failures
Number
of Units
Test
Time
72
500
1000
3000
Unit
Hours
MAE49, MC147, MC148
73
3000
0
0
0
0
219000
MFJ2W, MFJ2S, MFJ2T
73
1000
0
0
0
Product
Package
Wafer Lot
APA1000
CGA391
APA750
CGA391
Date
Code
TOTAL Units for 0.22 µm Flash FPGA =
146
73000
Total Test Time Hours =
292000
TOTAL Failures for 0.22 µm Flash FPGA = 0
Table 58: Temperature Cycle
Number of Cycles / Failures
Product
Package
Wafer Lot
APA750
PBGA4562
M3AA4
APA1000
PQFPG2081,3
MQRRS
Date
Code
0839
TOTAL Units for 0.22 µm Flash FPGA =
Number
of Units
Test
Cycles
200
500
1000
16
1000
0
0
0
16000
46
1000
0
0
0
46000
62
2000
Total Test Cycles =
Cycles
62000
TOTAL Failures for 0.22 µm Flash FPGA = 0
Notes:
1. G indicates lead-free.
2. Condition B, –55º to +125ºC
3. Condition C, –65ºC to +150ºC
46
SoC Reliability Report
0.15 µm UMC FPGA Reliability Summary
Table 59: High Temperature Operating Life (HTOL)
Test Hours / Failures
Wafer
Lot
Date Number
Code of Units
Test
Time
Test Time
TJ (oC) @ TJ 125oC 168 500 1000 2000
Unit
Hours
Product
Package
AX1000
PQFP208 DO3121,
DO3131,
DO4CA1
129
1000
125
1000
0
0
0
129000
AX1000
PQFP208 D097H1,
DO97J1
77
1000
125
1000
0
0
0
77000
AX2000
FBGA896 D0HGC1,
DOH3M6
38
1000
125
1000
0
0
0
38000
AX2000
FBGA896
D16T91
0431
22
1000
125
1000
0
0
0
22000
AX2000
FBGA896
D2A5A1
0620
77
1000
125
1000
0
0
0
77000
RTAX1000S4
CQFP352 D1GAH1 0444,
0507
98
1000
132
1423
0
(4)1
0
133762
RTAX2000S4
CQFP352
D1L9R1
0506
87
1000
132
1423
0
(2)1
0
120955
RTAX1000S4
CGA624
D1GAH1
0444
150
1000
132
1423
(1)2 (5)2
0
204912
RTAX1000S4
CGA624
D1GAH1
0444
28
1000
132
1423
0
13
0
38421
RTAX1000S4
CGA624
D1GAH1
0444
120
6000
132
8538
0
0
0
RTAX2000S4
CGA1152
D1PPY1
6
1000
132
1423
0
0
0
8538
RTAX2000S4
CQFP352 D1N9H1
6
1000
132
1423
0
0
0
8538
RTAX2000S4
CQFP352 D1GAG1
14
168
132
239
0
3346
RTAX2000S4
CQFP352 D1N9H1
14
168
132
239
0
3346
RTAX2000S4
CQFP352
14
168
132
239
0
3346
D21PH1
0
1024560
Notes:
1. ESD represented in parentheses – ESD failures due to high ESD levels on test loadboard sockets. Failure analysis was
completed and to improve the ESD environment during the testing and programming flow, Microsemi SoC's CQFP test
socket vendor manufactured socket lids with an ESD friendly polymer material that reduces the ESD charge to about 15
V. Microsemi SoC has replaced all CQFP socket lids in our test and programming facility with these “ESD-Friendly” lids.
Microsemi SoC issued PCN0512 for ESD-Friendly Lid Replacement for CQFP Programming Modules.
2. Continuity failures caused by contention problems with the burn-in driver and the device. Failure analysis was
completed and contention was fixed on the burn-in board adaptor.
3. CMOS failure happened at 500 hours. Failure analysis concluded the root cause as incomplete oxide etch during
fabrication process.
4. HTOL data summarized above for CMOS FIT calculation based on the following assumptions.
• Voltage Acceleration:
· VCCA = 1.6 V, voltage acceleration factor for these tests has been assumed to be 1.
• Temperature Acceleration:
· Stress Temperature = Junction Temperature (i.e., Tstress = TJ).
· The burn-in hours have been normalized to a TJ of 125ºC (i.e., 100 units @ TJ 132ºC burn-in time 1000 hrs is
equivalent to 100 units @ TJ 125ºC burn-in time 1423.015 hrs)
5. Unit passed 2000 hrs (4614 hrs @ 125ºC) but failed post 3000 hrs (6922 hrs @ 125ºC). Failure not counted towards
device FIT, as FA concluded it was due to the F/G leak test procedure. Test procedure has been updated and FA report
is available upon request.
6. One unit failed SRAM at 1000 hrs.
SoC Reliability Report
47
Table 59: High Temperature Operating Life (HTOL) (continued)
Test Hours / Failures
Package
Wafer
Lot
RTAX1000S4
CGA624
D1KH51
37
1000
132
1423
0
52651
RTAX1000S4
CQFP352
D1KH51
8
1000
132
1423
0
11384
RTAX2000S4
CQFP352 D1R0G1
14
168
132
239
0
3346
RTAX2000S4
CQFP352
D1L9R1
14
168
132
239
0
3346
RTAX2000S4
CQFP352 D1PPY1
14
168
132
239
0
3346
RTAX250S4
CQFP352
D1H381
100
168
132
239
0
23900
RTAX1000S4
CGA624
D1PQ01
150
1000
132
1423
0
CQFP352 D1N9H1
14
168
132
239
0
3346
D1KH51
24
168
132
239
0
5736
RTAX2000S4
CQFP352 D1NSG1
14
168
132
239
0
3346
RTAX250S4
CQFP208
D1H381
6
1000
125
1000
0
0
0
6000
RTAX2000S4
CQFP352 D1KHN1
78
1000
125
1000
0
0
0
78000
RTAX1000S4
CQFP352 D1NR91
24
168
132
239
0
5736
RTAX2000S4
CQFP352 D1KHN1
14
168
132
239
0
3346
RTAX2000S4
CQFP352
D21PH1
6
1000
125
1000
0
6000
RTAX4000S4
LGA1272
D30141
0730
75
6000
142
13844
0
0
0
0
1038310
RTAX4000S4
LGA1272
D30141
0730
1
3000
142
6922
0
0
0
0
6922
RTAX4000S4,5 LGA1272
D30141
0730
1
2000
142
4614
0
0
0
0
4614
RTAX2000S4
RTAX1000S4
CGA624
Date Number
Code of Units
Test
Time
Test Time
TJ (oC) @ TJ 125oC 168 500 1000 2000
Product
0
0
Unit
Hours
213450
Notes:
1. ESD represented in parentheses – ESD failures due to high ESD levels on test loadboard sockets. Failure analysis was
completed and to improve the ESD environment during the testing and programming flow, Microsemi SoC's CQFP test
socket vendor manufactured socket lids with an ESD friendly polymer material that reduces the ESD charge to about 15
V. Microsemi SoC has replaced all CQFP socket lids in our test and programming facility with these “ESD-Friendly” lids.
Microsemi SoC issued PCN0512 for ESD-Friendly Lid Replacement for CQFP Programming Modules.
2. Continuity failures caused by contention problems with the burn-in driver and the device. Failure analysis was
completed and contention was fixed on the burn-in board adaptor.
3. CMOS failure happened at 500 hours. Failure analysis concluded the root cause as incomplete oxide etch during
fabrication process.
4. HTOL data summarized above for CMOS FIT calculation based on the following assumptions.
• Voltage Acceleration:
· VCCA = 1.6 V, voltage acceleration factor for these tests has been assumed to be 1.
• Temperature Acceleration:
· Stress Temperature = Junction Temperature (i.e., Tstress = TJ).
· The burn-in hours have been normalized to a TJ of 125ºC (i.e., 100 units @ TJ 132ºC burn-in time 1000 hrs is
equivalent to 100 units @ TJ 125ºC burn-in time 1423.015 hrs)
5. Unit passed 2000 hrs (4614 hrs @ 125ºC) but failed post 3000 hrs (6922 hrs @ 125ºC). Failure not counted towards
device FIT, as FA concluded it was due to the F/G leak test procedure. Test procedure has been updated and FA report
is available upon request.
6. One unit failed SRAM at 1000 hrs.
48
SoC Reliability Report
Table 59: High Temperature Operating Life (HTOL) (continued)
Test Hours / Failures
Product
Package
Wafer
Lot
RTAX2000
CQFP352
D1L9R1
RTAX250S
Date Number
Code of Units
Test
Time
Test Time
TJ (oC) @ TJ 125oC 168 500 1000 2000
0
0
0
Unit
Hours
6
2000
125
2000
0
12000
CQFP352 D1M6K1
100
168
125
168
0
RTAX2000S
CQFP352
D2S8K1
79
1000
125
1000
0
RTAX2000S
CGA624
D2S8M1
14
168
125
168
0
RTAX2000S
CGA624
D2T2A1
24
1000
125
1000
0
0
0
RTAX2000S
CQFP352
D21PH1
8
2000
125
2000
0
0
0
0
16000
RTAX2000S
CGA624
D1N9H1
6
2000
125
2000
0
0
0
0
12000
RTAX2000S
CGA624
D1N9H1
2
1000
125
1000
0
0
16
0
2000
RTAX2000S
CGA624
D2T2A1
8
2000
125
2000
0
0
0
0
16000
RTAX2000S
CGA624
D2S8N5
14
168
125
168
0
2352
RTAX2000S
CGA624
D2T2C1
14
168
125
168
0
2352
RTAX2000S
CQFP352
D2T2C1
11
2000
125
2000
0
0
0
0
22000
RTAX2000S
CQFP352 D2WG61
11
2000
125
2000
0
0
0
0
22000
8
1000
125
1000
0
0
0
24
2000
131
2708
0
0
0
16800
0
0
79000
2352
24000
RTAX2000S
CGA624
D2S8N5
RTAX4000S4
LGA1272
D31CA1
RTAX2000S
CGA624
D2WG61
14
168
125
168
0
2352
RTAX2000S
CGA624
D334Y1
14
168
125
168
0
2352
RTAX4000S
LGA1272
D31CA1
15
2000
125
2000
0
0
0
0
30000
RTAX2000S
CQFP352
D334Y1
8
2000
125
2000
0
0
0
0
16000
RTAX1000S
CQFP352 D1NR91
8
1000
125
1000
0
0
0
0735
8000
0
64992
8000
Notes:
1. ESD represented in parentheses – ESD failures due to high ESD levels on test loadboard sockets. Failure analysis was
completed and to improve the ESD environment during the testing and programming flow, Microsemi SoC's CQFP test
socket vendor manufactured socket lids with an ESD friendly polymer material that reduces the ESD charge to about 15
V. Microsemi SoC has replaced all CQFP socket lids in our test and programming facility with these “ESD-Friendly” lids.
Microsemi SoC issued PCN0512 for ESD-Friendly Lid Replacement for CQFP Programming Modules.
2. Continuity failures caused by contention problems with the burn-in driver and the device. Failure analysis was
completed and contention was fixed on the burn-in board adaptor.
3. CMOS failure happened at 500 hours. Failure analysis concluded the root cause as incomplete oxide etch during
fabrication process.
4. HTOL data summarized above for CMOS FIT calculation based on the following assumptions.
• Voltage Acceleration:
· VCCA = 1.6 V, voltage acceleration factor for these tests has been assumed to be 1.
• Temperature Acceleration:
· Stress Temperature = Junction Temperature (i.e., Tstress = TJ).
· The burn-in hours have been normalized to a TJ of 125ºC (i.e., 100 units @ TJ 132ºC burn-in time 1000 hrs is
equivalent to 100 units @ TJ 125ºC burn-in time 1423.015 hrs)
5. Unit passed 2000 hrs (4614 hrs @ 125ºC) but failed post 3000 hrs (6922 hrs @ 125ºC). Failure not counted towards
device FIT, as FA concluded it was due to the F/G leak test procedure. Test procedure has been updated and FA report
is available upon request.
6. One unit failed SRAM at 1000 hrs.
SoC Reliability Report
49
Table 59: High Temperature Operating Life (HTOL) (continued)
Test Hours / Failures
Wafer
Lot
Product
Package
RTAX1000S
CQFP352 D1NR91
Date Number
Code of Units
Test
Time
Test Time
TJ (oC) @ TJ 125oC 168 500 1000 2000
Unit
Hours
11
2000
125
2000
0
0
0
0
22000
0
0
0
48000
RTAX2000S
CGA624
D32R41
24
2000
125
2000
0
RTAX2000S
CQFP352
D3CA81
14
168
125
168
0
2352
RTAX2000S
CQFP352
D3HY41
14
168
125
168
0
2352
RTAX4000S
CQFP352
D31CF1
8
168
125
168
0
1344
RTAX4000S
LGA1272
D30121
8
168
125
168
0
1344
RTAX2000S
CGA624
D3HY31
14
168
125
168
0
2352
RTAX250S4
CQFP208
D1H381
D1M6K1
82
3000
132
4269
0
0
0
RTAX250S4
CQFP208
D1H381
8
1000
131
1354
0
0
0
10833
RTAX250S4
CQFP352
D1H381
8
1000
131
1354
0
0
0
10833
RTAX250S4
CQFP352
D1H381
7
1000
131
1354
0
0
0
9479
RTAX250S4
CQFP352
D1H381
1
500
131
677
0
0
RTAX1000S4
CGA624
D1PQ01
150
1000
132
1423
0
0
0
RTAX1000S4
CQFP352 D1NR91
25
2000
134
3141
0
0
0
RTAX1000S4
CQFP352
D2S8P8
24
168
134
264
0
RTAX1000S4
CQFP352 D1NR91
8
1000
134
1570
0
0
0
0
350062
677
213452
0
78521
6332
RTAX2000S4
CGA624
D2S8N5
D2S8M1
82
3000
134
4711
0
0
0
RTAX2000S4
CQFP352
D3T0N1
80
1000
137
1817
0
0
0
12563
0
386323
145389
Notes:
1. ESD represented in parentheses – ESD failures due to high ESD levels on test loadboard sockets. Failure analysis was
completed and to improve the ESD environment during the testing and programming flow, Microsemi SoC's CQFP test
socket vendor manufactured socket lids with an ESD friendly polymer material that reduces the ESD charge to about 15
V. Microsemi SoC has replaced all CQFP socket lids in our test and programming facility with these “ESD-Friendly” lids.
Microsemi SoC issued PCN0512 for ESD-Friendly Lid Replacement for CQFP Programming Modules.
2. Continuity failures caused by contention problems with the burn-in driver and the device. Failure analysis was
completed and contention was fixed on the burn-in board adaptor.
3. CMOS failure happened at 500 hours. Failure analysis concluded the root cause as incomplete oxide etch during
fabrication process.
4. HTOL data summarized above for CMOS FIT calculation based on the following assumptions.
• Voltage Acceleration:
· VCCA = 1.6 V, voltage acceleration factor for these tests has been assumed to be 1.
• Temperature Acceleration:
· Stress Temperature = Junction Temperature (i.e., Tstress = TJ).
· The burn-in hours have been normalized to a TJ of 125ºC (i.e., 100 units @ TJ 132ºC burn-in time 1000 hrs is
equivalent to 100 units @ TJ 125ºC burn-in time 1423.015 hrs)
5. Unit passed 2000 hrs (4614 hrs @ 125ºC) but failed post 3000 hrs (6922 hrs @ 125ºC). Failure not counted towards
device FIT, as FA concluded it was due to the F/G leak test procedure. Test procedure has been updated and FA report
is available upon request.
6. One unit failed SRAM at 1000 hrs.
50
SoC Reliability Report
Table 59: High Temperature Operating Life (HTOL) (continued)
Test Hours / Failures
Date Number
Code of Units
Test
Time
Test Time
TJ (oC) @ TJ 125oC 168 500 1000 2000
Product
Package
Wafer
Lot
Unit
Hours
RTAX2000S4
CGA624
D2T2C1
8
1000
137
1817
0
0
0
14539
RTAX2000S4
CQFP352
D3CA81
8
1000
137
1817
0
0
0
14539
RTAX2000S4
CQFP352
D3HY41
8
1000
137
1817
0
0
0
14539
RTAX2000S4
CQFP352 D3WJA1
14
168
137
305
0
4274
RTAX2000S4
CAFP352
D404N1
14
168
137
305
0
4274
RTAX2000S4
CGA624
D2T2A1
8
1000
137
1817
0
0
0
RTAX2000S4
CQFP352
D3CA81
8
2000
137
3635
0
0
0
RTAX2000S4
CQFP352 D3WJA1
8
1000
137
1817
0
0
0
14539
0
29078
14539
RTAX1000S4
CGA624
D1PQ01
2
168
137
305
0
RTAX1000S4
CGA624
D1PQ01
22
2000
137
3635
0
0
0
CQFP352 D1PQ01
8
1000
137
1817
0
0
0
14539
0
0
10833
RTAX1000S4
611
0
79964
RTAX2000S4
CGA624
D3WJA1
8
1000
131
1354
0
RTAX2000S4
CGA624
D477A1
14
168
137
305
0
4274
RTAX2000S4
CQFP352
D45C11
14
168
137
305
0
4274
RTAX2000S
CQFP352
D517P1
1034
79
1500
125
1500
0
0
0
118500
RTAX2000S
CQFP352 D4CYF1
1004
80
1000
125
1000
0
0
0
8000
RTAX2000S
CQFP352
D404N1
0938
8
2000
125
2000
0
0
0
RTAX2000S
CQFP352
D55A21
1049
7
1000
125
1000
0
0
0
0
16000
7000
Notes:
1. ESD represented in parentheses – ESD failures due to high ESD levels on test loadboard sockets. Failure analysis was
completed and to improve the ESD environment during the testing and programming flow, Microsemi SoC's CQFP test
socket vendor manufactured socket lids with an ESD friendly polymer material that reduces the ESD charge to about 15
V. Microsemi SoC has replaced all CQFP socket lids in our test and programming facility with these “ESD-Friendly” lids.
Microsemi SoC issued PCN0512 for ESD-Friendly Lid Replacement for CQFP Programming Modules.
2. Continuity failures caused by contention problems with the burn-in driver and the device. Failure analysis was
completed and contention was fixed on the burn-in board adaptor.
3. CMOS failure happened at 500 hours. Failure analysis concluded the root cause as incomplete oxide etch during
fabrication process.
4. HTOL data summarized above for CMOS FIT calculation based on the following assumptions.
• Voltage Acceleration:
· VCCA = 1.6 V, voltage acceleration factor for these tests has been assumed to be 1.
• Temperature Acceleration:
· Stress Temperature = Junction Temperature (i.e., Tstress = TJ).
· The burn-in hours have been normalized to a TJ of 125ºC (i.e., 100 units @ TJ 132ºC burn-in time 1000 hrs is
equivalent to 100 units @ TJ 125ºC burn-in time 1423.015 hrs)
5. Unit passed 2000 hrs (4614 hrs @ 125ºC) but failed post 3000 hrs (6922 hrs @ 125ºC). Failure not counted towards
device FIT, as FA concluded it was due to the F/G leak test procedure. Test procedure has been updated and FA report
is available upon request.
6. One unit failed SRAM at 1000 hrs.
SoC Reliability Report
51
Table 59: High Temperature Operating Life (HTOL) (continued)
Test Hours / Failures
Product
Package
Wafer
Lot
RTAX2000SL
CQFP256
RTAX2000S
CQFP352
Test Time
TJ (oC) @ TJ 125oC 168 500 1000 2000
Date Number
Code of Units
Test
Time
D55A31
1052
22
2000
125
2000
0
0
0
44000
D54C81
1106
8
1000
125
1000
0
0
0
8000
RTAX2000S
CQFP352 D63WS1
1225
80
1000
125
1000
0
0
0
80000
RTAX4000S
CQFP352
D3T0N1
0818
44
1000
125
1000
0
0
0
44000
RTAX4000S
CGA1152
D404N1
0825
6
1000
125
1000
0
0
0
6000
RTAX4000D
CQFP352
D4LJQ1
1003
47
1000
125
1000
0
0
0
47000
RTAX4000SL
CQFP352
D41891
1110
24
1000
125
1000
0
0
0
24000
RTAX2000S
CQFP256 D71CM1
1350
79
1000
125
1000
0
0
0
79000
RTAX2000SL
CQFP256 D6CTH1
1338
23
2000
125
2000
0
0
0
0
46000
RTAX2000S
CQFP352 D6CN21
1345
24
2000
125
2000
0
0
0
0
48000
RTAX4000DL
CQFP352 D64NH1
1251
7
2000
125
2000
0
0
0
0
14000
TOTAL Units for 0.15 µm FPGA =
3112
Unit
Hours
Total Test Time Hours = 5844579
TOTAL Failures for 0.15 µm FPGA = 2
Notes:
1. ESD represented in parentheses – ESD failures due to high ESD levels on test loadboard sockets. Failure analysis was
completed and to improve the ESD environment during the testing and programming flow, Microsemi SoC's CQFP test
socket vendor manufactured socket lids with an ESD friendly polymer material that reduces the ESD charge to about 15
V. Microsemi SoC has replaced all CQFP socket lids in our test and programming facility with these “ESD-Friendly” lids.
Microsemi SoC issued PCN0512 for ESD-Friendly Lid Replacement for CQFP Programming Modules.
2. Continuity failures caused by contention problems with the burn-in driver and the device. Failure analysis was
completed and contention was fixed on the burn-in board adaptor.
3. CMOS failure happened at 500 hours. Failure analysis concluded the root cause as incomplete oxide etch during
fabrication process.
4. HTOL data summarized above for CMOS FIT calculation based on the following assumptions.
• Voltage Acceleration:
· VCCA = 1.6 V, voltage acceleration factor for these tests has been assumed to be 1.
• Temperature Acceleration:
· Stress Temperature = Junction Temperature (i.e., Tstress = TJ).
· The burn-in hours have been normalized to a TJ of 125ºC (i.e., 100 units @ TJ 132ºC burn-in time 1000 hrs is
equivalent to 100 units @ TJ 125ºC burn-in time 1423.015 hrs)
5. Unit passed 2000 hrs (4614 hrs @ 125ºC) but failed post 3000 hrs (6922 hrs @ 125ºC). Failure not counted towards
device FIT, as FA concluded it was due to the F/G leak test procedure. Test procedure has been updated and FA report
is available upon request.
6. One unit failed SRAM at 1000 hrs.
52
SoC Reliability Report
Table 60: Low Temperature Operating Life (LTOL)
Test Hours / Failures
Number
of Units
Test
Time
168
500
1000
DO3121,
DO3131,
DO4CA1
129
1000
0
0
0
129000
PQFP208
D097H1, D097J1
77
1000
0
0
0
77000
AX2000
FBGA896
D0HGC1,
D0H3M6
38
1000
0
0
0
38000
RTAX1000S
CQFP352
D1GAH1
78
1000
0
(1)1
0
77000
RTAX1000S
CGA624
D1GAH1
144
250
0
36000
RTAX1000S
CGA624
D1GAH1
150
250
(2)2
37000
RTAX1000S
CGA624
D1PQ01
148
250
0
37000
RTAX1000S
CGA624
D1PQ01
150
250
0
37500
RTAX2000S
CQFP352
D1KHN1
78
168
0
13104
RTAX250S
CQFP208
D1H381
D1M6K1
82
3000
0
0
0
RTAX4000S
LGA1272
D31CA1
24
1000
0
0
0
RTAX2000S
CGA624
D2S8N5
D2S8M1
82
3000
0
0
0
Product
Package
Wafer Lot
AX1000
PQFP208
AX1000
Date
Code
0444,
0507
TOTAL Units for 0.15 µm FPGA =
1180
2000
0
Unit
Hours
246000
24000
0
Total Test Time Hours =
246000
997604
TOTAL Failures for 0.15 µm FPGA = 0
Notes:
1. ESD represented in parentheses – ESD failures due to high ESD levels on test loadboard sockets. Failure analysis was
completed and to improve the ESD environment during the testing and programming flow, Microsemi SoC's CQFP test
socket vendor manufactured socket lids with an ESD friendly polymer material that reduces the ESD charge to about
15V. Microsemi SoC has replaced all CQFP socket lids in our test and programming facility with these “ESD-Friendly”
lids. Microsemi SoC issued PCN0512 for ESD-Friendly Lid Replacement for CQFP Programming Modules.
2. Continuity failures caused by contention problems with the burn-in driver and the device. Failure analysis was completed
and contention was fixed on the burn-in board adaptor.
Table 61: Biased Humidity
Test Hours / Failures
Number
of Units
Test
Time
50
100
DO3121,
DO3131,
DO4CA1
129
100
0
0
12900
D0HGC1,
D0H3M6
38
100
0
0
3800
TOTAL Units for 0.15 µm FPGA =
167
Product
Package
Wafer Lot
AX1000
PQFP208
AX2000
FBGA896
Date
Code
200
250
Total Test Time Hours =
Unit
Hours
16700
TOTAL Failures for 0.15 µm FPGA = 0
SoC Reliability Report
53
Table 62: Temperature Cycle
Number of Test Cycles/Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
100
200
500
1000
Cycles
(–65°C – +150°C)
AX1000
PQFP208
DO3121,
DO3131,
DO4CA1
129
500
0
0
0
64500
AX1000
PQFP208
D097H1,
D097J1
77
500
0
0
0
38500
AX2000
FBGA896
D0HGC1,
D0H3M6
22
500
0
0
0
11000
RTAX4000S
LGA1272
D30141
15
1000
0
0
0
RTAX4000D
CQFP352
D4LJQ1
15
100
0
1003
TOTAL Units for 0.15 µm FPGA =
258
0
15000
150
Total Test Cycles =
129150
TOTAL Failures for 0.15 µm FPGA = 0
54
SoC Reliability Report
Reliability Summary – Silicon Sculptor Programming
Software
The following tables show the number of unit-hours of life test data accumulated on Radiation-Tolerant
FPGAs programmed with specific revisions of Silicon Sculptor programming software. Life tests are
performed for several reasons: as part of device qualification (1,000 hours or 6,000 hours), as
customer-specific life tests (1,000 hours or 2,000 hours), as part of Group C life test (1,000 hours or 2,000
hours), or as part of our standard Enhanced Lot Acceptance (ELA) testing which is performed on samples
from every single wafer lot of RT FPGAs (168 hours). Microsemi’s official position is that customers are
recommended to use the latest version of software. However, customers who are unable to upgrade to use
the latest version of the software may find the life test data useful to determine how much reliability data is
accumulated on each version of the programming software.
Table 63: Unit-hours of Life Test Data
Silicon Sculptor
S/W Version
RTAX250S
RTAX1000S
RTAX2000S
RTAX4000S
RTAX2000D RTAX4000D
Total per
Version
V3.89
24,800
24,800
V3.93
6,000
6,000
V4.64.0
16,800
16,800
V4.68.1
33,704
V4.70.0
V4.70.1
528,000
561,704
57,856
2,520
75,376
2,352
1,344
3,696
2,352
5,000
10,000
V4.74
V4.76.0
2,352
2,520
V4.78.0
2,520
80,000
V4.78.1
80,000
8,000
8,000
V4.80.0
32,000
74,064
20,704
126,768
V5.2.0
48,000
4,032
116,056
168,088
V5.4.1
V5.6.0
6,048
48,000
V5.8.1
11,368
V5.10.1
V5.12.0
8,000
V5.12.1
16,800
44,000
15,056
4,032
92,720
14,000
10,352
22,384
4,032
64,704
114,352
V5.18.0
4,032
8,000
351,855
14,000
12,032
V5.22.1
282,799
81,352
V5.14.1
V5.22.0
50,048
6,000
85,536
51,344
2,352
180,080
89,408
1,680
95,120
264,464
1,344
265,808
4,704
12,704
V5.22.2
93,032
86,112
1,344
14,504
194,992
V5.22.3
8,064
96,872
30,000
1,440
136,376
202,442
50,688
V5.22.4
253,130
V5.22.5
Total per Device
SoC Reliability Report
213,400
230,736
1,364,842
717,760
2,352
1,344
1,344
303,111
2,832,201
55
0.13 µm Infineon Flash FPGA Reliability Summary
(ProASIC3 – A3P)
Table 64: High Temperature Operating Life (HTOL) After 550 Program/Erase Cycles
Test Hours / Failures
Product
Package
Wafer Lot
Date Number Test
Code of Units Time
TJ
(°C)
A3P060
FBGA256
ZA612052
0626
129
1000
133
1495
0
0
0
192855
A3P060
FBGA144
ZA835014
0838
77
1000
137
1817
0
0
0
139937
A3P125
FBGAG1442
ZA614041
0646
82
1000
130
1288
0
0
0
105616
A3P250
FBGA256
ZA519154
0527
15
168
133
251
0
A3P2501
FBGA256
ZA519154,
ZA519154.01,
ZA523569,
ZA523569.01
0532,
0533,
0534,
0536,
0537,
0538,
0541,
0543
129
3000
133
4485
0
0
0
A3P250
FBGA256
ZA628252.05
0628
77
1000
133
1495
0
0
0
115115
ZA614042
0637
77
1000
133
1495
0
0
0
115115
0604,
ZA546185,
ZA538175.02, 0602,
0608,
ZA548138
0609
129
2000
134
3141
0
0
0
A3P400
A3P1000
FBGA256
1
FBGAG484
2
Test Time
@ TJ 125°C 168 500 1000 2000
Unit
Hours
3765
0
0
578565
405189
A3P1000
FBGAG4842
ZA63718002
0640
77
1000
134
1570
0
0
0
120890
A3P1000
FBGAG4842
ZA63718002
ZA63717902
ZA64173402
ZA70708902
0640
0642
0645
0707
231
2008
134
3153
0
0
0
728343
A3P1000
FBGAG4842
ZA63718002
ZA63717902
ZA64173402
ZA70708902
0640
0642
0645
0707
2427
48
134
75
A3PE1500 FBGAG4842
ZA707790
0715,
0716,
0717
77
1000
134
1570
0
0
0
120890
A3P1000
ZA252062
1312
77
1000
134
1570
0
0
0
120890
FBGAG484
TOTAL Units for 0.13 µm FPGA =
3604
182025
Total Test Time Hours 2929195
TOTAL Failures for 0.13 µm FPGA = 0
Notes:
1. Initial 1000 hours HTOL completed per qualification requirement, HTOL was continued up to:
• 3000 hours for A3P250, all units passed
• 2000 hours for A3P1000, all units passed
2. G indicates lead-free.
56
SoC Reliability Report
Table 65: Low Temperature Operating Life (LTOL) at –55°C after 550 Program/Erase Cycles
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test Time
168
A3P250
FBGA256
ZA519154
0527
15
168
0
A3P2501
FBGA256
ZA519154,
ZA519154.01,
ZA523569,
ZA523569.01
0532,
0533,
0534,
0536,
0537,
0538,
0541,
0543
129
2000
0
0
0
A3P1000
FBGAG4842
ZA546185,
ZA538175.02,
ZA548138
0604,
0602,
0608,
0609
129
1000
0
0
0
A3PE1500
FBGAG4842
ZA707790
0715,
0716,
0717
77
1000
0
0
0
A3P250
VQG1002, 3
ZA418036
1430,
231
500
0
0
500
1000
2000
Unit
Hours
2520
0
258000
129000
0
77000
115500
1431,
1432
TOTAL Units for 0.13 µm FPGA =
581
Total Test Time Hours =
582020
TOTAL Failures for 0.13 µm FPGA = 0
Notes:
1. Initial 1000 hours LTOL completed per qualification requirement, LTOL was continued up to 2000 hours, all units
passed.
2. G indicates lead-free.
3. VQ100 package release by extension.
SoC Reliability Report
57
Table 66: Temperature Cycle (TC), –55°C to +125°C
Number of Test Cycles/Failures
Date
Code
Number
of Units
Test Cycles
200
500
1000
Product
Package
Wafer Lot
2000
A3P250
FBGA256
ZA519154,
ZA519154.01,
ZA523569,
ZA523569.01
0532,
0533,
0534,
0536,
0537,
0538,
0541,
0543
129
1000
0
0
0
129000
A3P1000
FBGAG4842
ZA546185,
ZA538175.02,
ZA548138
0604,
0602,
0608,
0609
77
1000
0
0
0
77000
A3P1000
FBGAG4841,2
ZA63718002
ZA63717902
ZA64173402
ZA70708902
0640
0642
0645
0707
231
1000
0
0
0
231000
A3PE1500
FBGAG4842
ZA707790
0715,
0716,
0717
77
1000
0
0
0
77000
A3PE1500
PQFPG2082,3
ZA732709
0811
48
1000
0
0
0
48000
A3P250
VQFP1003
ZA840056
1010
47
500
0
0
23500
A3P1000
PQFPG2082,3
ZA31005102
1314
47
500
0
0
23500
A3P250
QNG1322,3
ZA249133
1320
47
500
0
0
23500
A3P250
VQG100 2, 3
ZA418036
1430,
1431,
231
1000
0
0
0
Cycles
231000
1432
TOTAL Units for 0.13 µm FPGA =
934
Total Test Cycles =
863500
TOTAL Failures for 0.13 µm FPGA = 0
Notes:
1. Automotive (AEC Q-100) Grade 1 –50°C to +150°C.
2. G indicates lead-free.
3. Condition C, –65ºC to +150ºC (AECQ-100) Grade.
58
SoC Reliability Report
Table 67: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test Time
50
100
200
250
Unit
Hours
A3P250
FBGA256
ZA519154
0527
22
264
0
0
0
0
5808
A3P250
FBGA256
ZA519154,
ZA519154.01,
ZA523569,
ZA523569.01
0532,
0533,
0534,
0536,
0537,
0538,
0541,
0543
129
264
0
0
0
0
34056
A3P1000
FBGAG484
ZA546185,
ZA538175.02,
ZA548138
0604,
0602,
0608,
0609
77
264
0
0
0
0
34056
A3P1000
FBGAG4841,2
ZA63718002
ZA63717902
ZA64173402
ZA70708902
0640
0642
0645
0707
231
96
0
A3PE1500
FBGAG4842
ZA707790
0715,
0716,
0717
77
264
0
0
A3PE1500
PQFPG2082,3
ZA732709
0811
47
100
0
0
4700
A3P250
VQFP1003
ZA840056
1010
47
100
0
0
4700
A3P1000
PQFPG2082,3
ZA31005102
1314
47
96
0
4512
A3P250
QNG1322,3
ZA249133
1320
47
96
0
4512
A3P250
VQG1001, 2, 3
ZA418036
1430,
231
96
0
22176
231
96
0
22176
45
264
0
22176
0
0
20328
1431,
1432
A3P250
VQG1001, 2
ZA418036
1430,
1431,
1432
A3P1000
FGG2562, 3
ZA424029
1433
TOTAL Units for 0.13 µm FPGA =
1231
0
0
0
Total Test Time Hours =
11880
186380
TOTAL Failures for 0.13 µm FPGA = 0
Notes:
1. Automotive (AEC-Q100) 130°C and RH = 85%
2. G indicates lead-free.
3. Unbiased HAST (JESD22 A118), 130ºC and RH = 85%.
SoC Reliability Report
59
Table 68: High Temperature Storage (HTS), 150°C
Test Hours / Failures
Date
Code
Number
of Units
Test Time
200
500
1000
ZA519154,
ZA519154.01,
ZA523569, and
ZA523569.01
0532,
0533,
0534,
0536,
0537,
0538,
0541,
0543
129
1000
0
0
0
129000
FBGAG4841
ZA546185,
ZA538175.02,
ZA548138
0604,
0602,
0608,
0609
77
1000
0
0
0
77000
A3P1000
FBGAG4841
ZA63718002
ZA63717902
ZA64173402
ZA70708902
0640
0642
0645
0707
231
1000
0
0
0
231000
A3PE1500
FBGAG4841
ZA707790
0715,
0716,
0717
77
1000
0
0
0
77000
A3P1000
PQFPG2081
ZA31005102
1314
45
1000
0
0
0
45000
A3P250
QNG1321
ZA249133
1320
47
1000
0
0
0
47000
A3P250
VQG1001, 2
ZA418036
1430,
1431,
77
1000
0
0
0
77000
Product
Package
Wafer Lot
A3P250
FBGA256
A3P1000
2000
Unit
Hours
1432
TOTAL Units for 0.13 µm FPGA =
Total Test Cycles =
683
683000
TOTAL Failures for 0.13 µm FPGA = 0
Notes:
1. *G indicates lead-free.
2. Automotive (AEC-Q100)
Table 69: Temperature Humidity Bias (THB), 85°C / 85% RH
Test Hours / Failures
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
200
500
1000
2000
Unit
Hours
A3P1000
FBGAG484*
ZA641734
0647
77
2000
0
0
0
0
154000
A3P1000
PQFPG208*
ZA648504
0712
22
2000
0
0
0
0
44000
A3P1000
PQFPG208*
ZA719018
0743
22
2000
0
0
0
0
44000
A3P1000
FBGAG256*
ZA627018
0634
22
2000
0
0
0
0
44000
A3P250
FBGAG256*
ZA644020
0711
22
2000
0
0
0
0
44000
Product
TOTAL Units for 0.13 µm Flash FPGA =
165
Total Test Time Hours =
330000
TOTAL Failures for 0.13 µm Flash FPGA = 0
Note: *G indicates lead-free.
60
SoC Reliability Report
Table 70: Endurance (Room Temperature)
Number of Cycles / Failures
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
50
100
500
1000
Cycles
A3P250
FBGA256
ZA519154
0527
5
3000
0
0
0
0
150000
A3P250
FBGA256
ZA519154,
ZA519154.01
ZA523569,
ZA523569.01
0532,
0533,
0534,
0536,
0537,
0538,
0541,
0543
129
550
0
0
0
70950
A3P1000
FBGAG484*
ZA546185,
ZA538175.02,
ZA548138
0604,
0602,
0608,
0609
77
550
0
0
0
42350
A3P1000
FBGAG484*
ZA63718002
ZA63717902
ZA64173402
ZA70708902
0640
0642
0645
0707
231
550
0
0
0
127050
A3PE1500
FBGAG484*
ZA707790
0715,
0716,
0717
77
550
0
0
0
42350
Product
TOTAL Units for 0.13 µm Flash FPGA =
519
Total Test Cycles = 432700
TOTAL Failures for 0.13 µm Flash FPGA = 0
Note: *G indicates lead-free.
SoC Reliability Report
61
Table 71: Retention at 250°C after 550 Program/Erase Cycles
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
72
A3P250
CQFP2083
ZA519154
0527
45
168
0
A3P250
CQFP2083
ZA519154,
ZA519154.01,
ZA523569,
ZA523569.01
0532,
0533,
0534,
0536,
0537,
0538,
0541,
0543
129
1000
0
0
A3P1000
CQFP2083
ZA546185,
ZA538175.02,
ZA548138
0604,
0602,
0608,
0609
77
500
0
0
A3P1000
CQFP2083
ZA63718002
ZA63717902
ZA64173402
ZA70708902
0640
0642
0645
0707
231
10081
0
0
0
A3P1000
CQFP2083
ZA64173402,
ZA648504,
ZA649017
0650
0717
0705
149
3000
0
12
0
A3PE1500
CQFP2083
ZA707790
0715,
0716,
0717
77
1000
0
0
0
77000
Total Test Time Hours =
446408
TOTAL Units for 0.13 µm Flash FPGA =
559
500
1000
3000
Unit
Hours
7560
0
129000
38500
232848
0
447000
TOTAL Failures for 0.13 µm Flash FPGA = 1
Notes:
1. Retention at 150°C per Automotive AEC-Q100.
2. Single-bit random failure on erase side at 168 hours; physical analysis shows poly1 defect.
3. Not commercially available (i.e., the engineering package is for reliability testing only).
62
SoC Reliability Report
0.13 µm Infineon Flash FPGA Reliability Summary
(Fusion – AFS)
Table 72: High Temperature Operating Life (HTOL) after 550 Program/Erase Cycles
Test Hours / Failures
Product
Package
Wafer Lot
Test Time
Date Number Test
Code of Units Time TJ (°C) @ TJ 125°C 168 500 1000 2000
Unit
Hours
AFS1500
FBGA256
ZA915053
0919
77
168
141
370
0
28467
0806
0810
110
2000
144
5068
0
(1)2
0
0
0
AFS1500
ZA748708
FBGA256,
FBGAG2561 ZA74902101
557579
AFS600
FBGA256
ZA652744,
ZA652745,
ZA701716
0702
0709
0712
129
1000
141
2200
0
AFS600
FBGA256
ZA705109
0718
87
168
141
369
0
AFS600
FBGA256
ZA729021
0741
68
3200
141
7042
0
0
0
0
478894
AFS600
FBGA256
ZA729021
0741
70
1000
141
2200
0
0
0
0
154056
FBGA256,
ZA702009,
ZA702008,
ZA704181
0733
163
1000
135
1649
0
0
0
AFS250
FBGAG2561
TOTAL Units for 0.13 µm FPGA =
704
0
283903
32163
268819
Total Test Time Hours 1803883
TOTAL Failures for 0.13 µm FPGA = 0
Notes:
1. G indicates lead-free.
2. 1 unit failed after 500 hours of HTOL, continuity failure observed on PTBASE pin at ATE test (resistive short). Burning
power supply monitoring logs during HTOL do not show increase in current. Probable root cause suspected as ESD
(handling after 500 hr. pull point for electrical testing), hence not counted towards device FIT.
Table 73: Low Temperature Operating Life (LTOL) at –55°C after 550 Program/Erase Cycles
Test Hours / Failures
Product
AFS1500
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
168
500
1000
FBGA256,
ZA748708
ZA74902101
0806
0810
68
1000
0
0
0
68000
FBGA256
ZA652744,
ZA652745,
ZA701716
0702
0709
0712
129
1000
0
0
0
129000
FBGA256,
ZA702009,
ZA702008,
ZA704181
0733
48
1000
0
0
0
48000
FBGAG256*
AFS600
AFS250
FBGAG256*
TOTAL Units for 0.13 µm FPGA =
245
2000
Total Test Time Hours =
Unit
Hours
245000
TOTAL Failures for 0.13 µm FPGA = 0
Note: *G indicates lead-free.
SoC Reliability Report
63
Table 74: Temperature Cycle (TC), –55°C to +125°C
Number of Test Cycles/Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
200
500
1000
AFS1500
FBGAG256*
ZA748708
ZA74902101
0806
0810
48
1000
0
0
0
48000
AFS600
FBGA256
ZA617031,
ZA619115,
ZA617032
0623
0631
0629
129
1000
0
0
0
129000
AFS600
FBGAG488*
ZA932055
1008
47
1000
0
0
0
47000
TOTAL Units for 0.13 µm FPGA =
224
2000
Total Test Cycles =
Cycles
224000
TOTAL Failures for 0.13 µm FPGA = 0
Note: *G indicates lead-free.
Table 75: High Temperature Storage (HTS), 150°C
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
200
500
1000
AFS1500
FBGAG256*
ZA748708
ZA74902101
0806
0810
50
1000
0
0
0
50000
AFS250
QNG180*
ZA702009,
ZA702008,
ZA704181
0723
45
1000
0
0
0
45000
TOTAL Units for 0.13 µm FPGA =
95
2000
Total Test Cycles =
Unit
Hours
95000
TOTAL Failures for 0.13 µm FPGA = 0
Note: *G indicates lead-free.
Table 76: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
50
100
200
250
Unit
Hours
AFS1500
FBGAG256*
ZA748708
ZA74902101
0806
0810
69
264
0
0
0
0
18216
AFS600
FBGA256
ZA729021
0741
45
264
0
0
0
0
11880
FBGA256,
ZA702009,
ZA702008,
ZA704181
0733
75
264
0
0
0
0
19800
AFS250
FBGAG256*
TOTAL Units for 0.13 µm FPGA =
189
Total Test Time Hours =
49896
TOTAL Failures for 0.13 µm FPGA = 0
Note: *G indicates lead-free.
64
SoC Reliability Report
Table 77: Endurance (FPGA NVM) at Room Temperature
Number of Cycles / Failures
Product
Package
Date
Code
Wafer Lot
Number
of Units
Test
Cycles
50
100
500
1000
Cycles
Room Temperature
AFS1500
FBGA256
FBGAG256*
AFS600
FBGA256
ZA748708
ZA74902101
0806
0810
77
550
0
0
0
42350
ZA617031,
ZA619115,
ZA617032
0623
0631
0629
129
550
0
0
0
70950
TOTAL Units for 0.13 µm Flash FPGA =
206
Total Test Cycles =
113300
TOTAL Failures for 0.13 µm Flash FPGA = 0
Note: *G indicates lead-free.
Table 78: Endurance (eNVM) at Room Temperature
Number of Cycles / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
50
100
500
1000
Cycles
0
0
0
0
129000
Room Temperature
AFS600
FBGA256
ZA617031,
ZA619115,
ZA617032
129
0623
0631
0629
TOTAL Units for 0.13 µm Flash FPGA =
1000
129
Total Test Cycles =
129000
TOTAL Failures for 0.13 µm Flash FPGA = 0
Table 79: Retention (FPGA NVM) at 250°C after 550 Program/Erase Cycles
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
72
500
1000
3000
Unit
Hours
AFS1500
CQFP208*
ZA748708
ZA74902101
0806
0810
77
2000
0
0
0
0
154000
AFS600
CQFP208*
ZA617031,
ZA619115,
ZA617032
0623
0631
0629
129
500
0
0
TOTAL Units for 0.13 µm Flash FPGA =
206
64500
Total Test Time Hours =
218500
TOTAL Failures for 0.13 µm Flash FPGA = 0
Note: *Not commercially available (i.e., the engineering package is for reliability testing only)
Table 80: Retention (eNVM) at 250°C after 1000 Program/Erase Cycles
Test Hours / Failures
Product
Package
Wafer Lot
AFS600
CQFP208*
ZA617031,
ZA619115,
ZA617032
Date
Code
Number
Units
Test
Time
72
500
0623
129
500
0
0
1000
3000
Unit
Hours
64500
0631
0629
TOTAL Units for 0.13 µm Flash FPGA =
129
Total Test Time Hours =
64500
TOTAL Failures for 0.13 µm Flash FPGA = 0
Note: *Not commercially available (i.e., the engineering package is for reliability testing only)
SoC Reliability Report
65
0.13 µm Infineon Flash FPGA Reliability Summary
(SmartFusion – A2F)
Table 81: High Temperature Operating Life (HTOL) after 550 Program/Erase Cycles
Test Hours / Failures
Number
of Units
Test
Time
TJ
(°C)
Test
Time @
Tj 125°C
168
500
Product
Package
Wafer Lot
Date
Code
A2F200
FBGAG484*
ZA917060
ZA91706101
ZA94100501
0923
0943
0947
247
2000
133
2990
0
0
0
A2F200
FBGAG484*
ZA925010
1004
82
1000
133
1495
0
0
0
122597
A2F500
FBGAG484*
ZA01402801
1018
82
1000
136
1731
0
0
0
141977
A2F200
FBGA484
ZA027289
1216
76
1000
133
1495
0
0
0
113626
TOTAL Units for 0.13µm FPGA =
487
1000 2000
0
Unit
Hours
738571
Total Test Time Hours 1116771
TOTAL Failures for 0.13 µm FPGA = 0
Note: *G indicates lead-free.
Table 82: High Temperature Storage (HTS), 150°C
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
200
500
1000
A2F200
FBGAG484*
ZA917060
ZA91706101
ZA94100501
0923
0943
0947
90
1000
0
0
0
A2F200
FBGA484
ZA027289
1216
47
1000
0
0
TOTAL Units for 0.13 µm FPGA =
137
2000
Unit
Hours
90000
0
47000
Total Test Cycles =
137000
TOTAL Failures for 0.13 µm FPGA = 0
Note: *G indicates lead-free.
Table 83: Temperature Humidity Bias (THB), 85°C / 85% RH
Test Hours / Failures
Product
Packages
Wafer Lot
Date
Code
Number
of Units
Test
Time
168
500
1000
A2F200
FBGA484
ZA027289
1216
53
1008
0
0
0
Total Units for 0.13 µm FPGA =
53
2000
Unit
Hours
53424
Total Test Time Hours =
53424
TOTAL Failures for 0.13 µm FPGA = 0
66
SoC Reliability Report
Table 84: Endurance (eNVM)
Product
Package
Wafer Lot
Date
Code
Number of
Units
Test
Cycles
100
500
1000
Cycles
A2F2002
FBGAG4841
ZA917060
ZA91706101
ZA9410050
0923
0943
0947
201
1100
0
0
0
221100
A2F2002
CQFP2084
ZA917060
ZA91706101
ZA9410050
0923
0943
0947
117
1100
0
0
0
128700
A2F2003
FBGAG4841
ZA917060
ZA91706101
ZA94100501
0923
0943
0947
128
1100
0
0
0
140800
TOTAL Units for 0.13 µm FPGA =
446
Total Test Cycles =
490600
TOTAL Failures for 0.13 µm FPGA = 0
Notes:
1. G indicates lead-free.
2. Room temperature, 25°C
3. Temperature +55°C Tj 85°C
4. Not commercially available (i.e., the engineering package is for reliability testing only)
Table 85: Retention (eNVM) after 1100 Program/Erase Cycles
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
TJ
(°C)
10
500
1000
Unit
Hours
A2F2002
CQFP2084
ZA917060
ZA91706101
ZA94100501
0923
0943
0947
117
1000
250
0
0
0
117000
A2F2003
FBGAG4841
ZA917060
ZA91706101
ZA94100501
0923
0943
0947
128
10
125
0
TOTAL Units for 0.13 µm Flash FPGA =
245
1280
Total Test Time Hours =
118280
TOTAL Failures for 0.13 µm Flash FPGA = 0
Notes:
1. G indicates lead-free.
2. HTDR after 1100 program/erase cycles at 25°C
3. HTDR per JEDEC after 1100 program/erase cycles at +55°C Tj 85°C
4. Not commercially available (i.e., the engineering package is for reliability testing only)
Table 86: Low Temperature Retention and Read Disturb (eNVM) at 25° after 1100 Program/Erase Cycles, 25°C
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
10
50
100
500
Unit
Hours
A2F200
FBGAG484*
ZA917060
ZA91706101
ZA94100501
0923
0943
0947
120
500
0
0
0
0
60000
TOTAL Units for 0.13 µm Flash FPGA =
120
Total Test Time Hours =
60000
TOTAL Failures for 0.13 µm Flash FPGA = 0
Note: *G indicates lead-free.
SoC Reliability Report
67
0.13 µm UMC Flash FPGA Reliability Summary
(IGLOO – AGL/AGLE; IGLOO PLUS – AGLP; IGLOO nano – AGLN)
Table 87: High Temperature Operating Life (HTOL) after 550 Program/Erase Cycles
Test Hours / Failures
Test Time
@ TJ 125°C 168
Date
Code
AGLE3000 FBGAG4841
QHC25
QHC3T
0809
0813
45
1000
130
1288
0
AGL1000
FBGAG4841
QHF28
0816
129
1000
132
1423
AGL600
FBGAG2561 QH4GT1,
QH4GW,
QH4H01
0728,
0730,
0722,
0727,
0726,
0732
129
4000
130
AGLN250
VQFPG1001
QHT2W
0915
129
2000
AGLP125
VQFP100
QHJFP
0823
129
2000
AGL030
VQFP100
Package
AGL600
FBGAG256
AGL1000
FBGAG484
1
Number Test
of Units Time
TJ
(°C)
Wafer Lot
Product
1000 2000
Unit
Hours
0
(3)3
57968
0
0
0
183569
5152
(1)2
0
0
664608
128
2330
0
0
0
128
2330
0
0
0
300563
500
0
300563
QH6MQ
0745
77
168
130
216
0
QHSYQ
0925
79
1000
130
1288
0
0
0
101767
QL1Y6
1250
75
1000
132
1423
0
0
0
106726
TOTAL Units for 0.13 µm FPGA =
792
16632
Total Test Time Hours 1732396
TOTAL Failures for 0.13 µm FPGA = 0
Notes:
1. G indicates lead-free.
2. 1 unit failed HTOL post 168 hours due to bond wire shorting. Failure will be screened by post assembly electrical test,
hence not counted towards device FIT. No other failures were observed until 5152 hrs.
• Microsemi SoC implemented I/O-to-I/O short test, 100% screening for production.
• STATS enhanced the wire loop height control of the affected wires and optimized mold parameter settings.
3. 3/48 failed IIH and IIL post 1000 hrs HTOL. All three failures confirmed to be due to VCCI overshoots on the ATE tester
during qualification read points, not counted towards device FIT. Implemented new VIH/L test vectors to eliminate the
VCCI overshoots and updated Test Program release procedures to include over/undershoot verification prior to release.
Table 88: Low Temperature Operating Life (LTOL) at –55°C after 550 Program/Erase Cycles
Test Hours / Failures
Date
Code
Number
of Units
Test Time
168
500
1000
QH4GT1,
QH4GW,
QH4H01
0728,
0730,
0722,
0727,
0726,
0732
129
1000
0
0
0
QH6MQ
0745
77
168
0
Product
Package
Wafer Lot
AGL600
FBGAG256*
AGL030
VQFP100
TOTAL Units for 0.13 µm FPGA =
206
2000
Unit
Hours
129000
12936
Total Test Time Hours =
141936
TOTAL Failures for 0.13 µm FPGA = 0
Note: *G indicates lead-free.
68
SoC Reliability Report
Table 89: Temperature Cycle (TC), –55°C to +125°C
Product
Number of Test Cycles/Failures
Date
Code
Number
of Units
Test Cycles
200
500
1000
Package
Wafer Lot
AGL600
FBGAG2561
QH4GT1,
QH4GW,
QH4H01
0728,
0730,
0722,
0727,
0726,
0732
129
1000
0
0
(1)2
129000
AGL600
FBGA256
QHCFR
0820
80
1000
0
0
0
80000
AGL030
VQFP100
QH62A
0739,
0741,
0743
77
1000
0
0
0
77000
AGLN020
QNG681
QHSKK
0909
0910
77
1000
0
0
0
77000
AGL060
CSG1211
QHR76
0928
45
1000
0
0
0
45000
AGLP125
VQFP100
QHJFP
0823
129
1000
0
0
0
129000
AGLP030
VQFPG1281,3
QJY60
1345
47
500
0
0
23500
Total Test Cycles =
560500
TOTAL Units for 0.13 µm FPGA =
584
2000
Cycles
TOTAL Failures for 0.13 µm FPGA = 0
Notes:
1. G indicates lead-free.
2. 1 unit failed after 1000 hours TC due to bond wire shorting. Failure will be screened by post assembly electrical test.
• Microsemi SoC implemented I/O-to-I/O short test, 100% screening for production.
• STATS enhanced the wire loop height control of the affected wires and optimized mold parameter settings.
3. Condition C, –65ºC to +150ºC
Table 90: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH
Test Hours / Failures
Date
Code
Number
of Units
Test Time
50
100
200
250
Unit
Hours
QH4GT1,
QH4GW,
QH4H01
0728,
0730,
0722,
0727,
0726,
0732
129
264
0
0
0
0
34056
VQFPG1001
QHT2W
0915
77
264
0
0
0
0
20328
AGL0602
CSG1211
QHR76
0928
45
264
0
0
0
0
11880
AGLP030
VQFPG1281,2
QJY60
1345
47
96
0
AGL1000
CSG2811, 2
QLMWN
1417
45
264
Product
Package
Wafer Lot
AGL600
FBGAG2561
AGLN250
TOTAL Units for 0.13 µm FPGA =
343
4512
0
Total Test Time Hours =
11880
826565
TOTAL Failures for 0.13 µm FPGA = 0
Notes:
1. G indicates lead-free.
2. Unbiased HAST (JESD22 A118), 130°C and RH = 85%.
SoC Reliability Report
69
Table 91: High Temperature Storage (HTS), 150°C
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
AGL1000
PQFP208
QHR6N
0850
99
3000
0
0
0
AGL600
FBGAG256*
QH4GT1,
QH4GW,
QH4H01
0728,
0730,
0722,
0727,
0726,
0732
129
1000
0
0
0
129000
AGLN250
VQFPG100*
QHT2W
0915
77
1000
0
0
0
77000
AGLN250
VQFPG100*
QHT2W
0915
77
3000
0
0
0
AGLP125
VQFP100
QHJFP
0823
129
1000
0
0
0
129000
AGL030
VQFP100
QH62A
0739,
0741,
0743
77
1000
0
0
0
77000
AGLN020
QNG68*
QHSKK
0909
0910
77
1000
0
0
0
77000
AGLP030
VQFPG128*
QJY60
1345
47
1000
0
0
0
47000
TOTAL Units for 0.13 µm FPGA =
Number
of Units
Test Time
200
500
1000
2000
Unit Hours
0
297000
712
0
231000
Total Test Cycles =
1064000
TOTAL Failures for 0.13 µm FPGA = 0
Note: *G indicates lead-free.
Table 92: Endurance 550 Program/Erase Cycles
Number of Cycles / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
50
100
500
1000
Cycles
AGL10002
PQFP208
QHR6N
0850
99
550
0
0
0
0
54450
AGL6002
FBGAG2561
QH4GT1,
QH4GW,
QH4H01
0728,
0730,
0722,
0727,
0726,
0732
129
550
0
0
0
70950
AGLN2502
VQFPG1001
QHT2W
0915
77
550
0
0
0
42350
TOTAL Units for 0.13 µm Flash FPGA =
305
Total Test Cycles =
167750
TOTAL Failures for 0.13 µm Flash FPGA = 0
Notes:
1. G indicates lead-free.
2. Room temperature, 25°C
70
SoC Reliability Report
Table 93: Retention at 250°C after 550 Program/Erase Cycles
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
72
500
1000
3000
Unit
Hours
AGL10001
CQFP2082
QHRYQ
0910
80
3000
0
0
0
0
240000
AGL6001
CQFP2082
QH4GT1,
QH4GW,
QH4H01
0728,
0730,
0722,
0727,
0726,
0732
129
1000
0
0
0
AGLN2501
CQFP2082
QHT2W
0915
77
3000
0
0
0
TOTAL Units for 0.13 µm Flash FPGA =
286
129000
0
Total Test Time Hours =
231000
600000
TOTAL Failures for 0.13 µm Flash FPGA = 0
Note:
1. Program/erase cycles at room temperature, 25°C
2. Not commercially available (i.e., the engineering package is for reliability testing only)
SoC Reliability Report
71
0.13 µm UMC Flash FPGA Reliability Summary
(ProASIC3, ProASIC3E – A3P, A3PE; ProASIC3L, ProASIC3EL – A3PL, A3PEL;
ProASIC3 nano – A3PN, RT ProASIC3 – RT3P)
Table 94: High Temperature Operating Life (HTOL) after 550 Program/Erase Cycles
Test Hours / Failures
Product
Package
Wafer
Lot
Test Time
@ TJ
Date Number Test TJ
Code of Units Time (°C) 125°C
168 500 1000 2000 3000
A3P600
FBGAG2561
QH4H0
0728
81
1000
130
1288
0
0
0
A3PE3000
FBGAG484
QHC9T
0806
0808
0809
1
2000
135
3298
0
0
0
128
6000
135
9895
0
0
Unit
Hours
104343
0
12
3298
0
0
0
1266552
RT3PE3000L
CGA896
QHR8G
0925
81
1000
142
2307
0
0
0
0
186896
RT3PE3000L
CGA896
QJA2G
1205
47
1000
142
2307
0
0
0
0
108446
RT3PE3000L
CGA484
QKN6Y
1341
80
1000
125
1000
0
0
0
80000
RT3PE3000L
CGA484
QJA2G
1031
78
1000
125
1000
0
0
0
78000
RT3PE3000L
LGA896
QJA2G
1123
6
1000
125
1000
0
0
0
6000
TOTAL Units for 0.13 µm FPGA =
502
Total Test Time Hours
1833535
TOTAL Failures for 0.13 µm FPGA = 1
Notes:
1. G indicates lead-free.
2. One CMOS failure was observed at 3000 hours, Tj 135.24°C (equivalent to 44 years of operation at 55°C); failure
counted toward device FIT (used Ea of 0.7 eV as FA inconclusive; root cause could not be established). 128 units from
this lot (QHC9T) continued to 6000 hours without failures.
Table 95: Low Temperature Operating Life (LTOL) at –55°C after 550 Program/Erase Cycles
Test Hours / Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
168
500
1000
A3P600
FBGAG256*
QH4H0
0728
82
1000
0
0
0
TOTAL Units for 0.13 µm FPGA =
82
2000
Unit
Hours
82000
Total Test Time Hours =
8200
TOTAL Failures for 0.13 µm FPGA = 0
Note: *G indicates lead-free.
72
SoC Reliability Report
Table 96: Temperature Cycle (TC), –55°C to +125°C
Number of Test Cycles/Failures
Product
Date
Code
Number
of Units
Test
Cycles
100
200
500
1000
Cycles
0
0
77000
Package
Wafer Lot
A3PE3000
FBGAG4841
QHC9T
0806,
0808,
0809
77
1000
0
0
A3P600
FBGAG2561
QL7H0
1323
45
700
0
0
31500
VQFPG1001,2
QL5CL
1309
45
500
0
0
22500
A3PN250
TOTAL Units for 0.13 µm FPGA =
167
Total Test Cycles =
131000
TOTAL Failures for 0.13 µm FPGA = 0
Note:
1. G indicates lead-free.
2. Condition C, –65ºC to +150ºC
Table 97: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH
Test Hours / Failures
Product
Date
Code
Number
of Units
Test Time
50
100
200
250
Unit
Hours
QHC9T
0806,
0808,
0809
77
264
0
0
0
0
20328
FBGAG4841
QHR8G
0921
72
3000
0
0
0
0
231000
VQFPG1001,2
QL5CL
1309
45
1000
0
0
Package
Wafer Lot
A3PE3000
FBGAG4841
A3PE3000
A3PN250
TOTAL Units for 0.13 µm FPGA =
194
4500
Total Test Time Hours =
296328
TOTAL Failures for 0.13 µm FPGA = 0
Notes:
1. G indicates lead-free.
2. Temperature Humidity Bias (THB), 85°C / 85% RH
Table 98: High Temperature Storage (HTS), 150°C
Test Hours / Failures
Product
Date
Code
Number
of Units
Test
Time
500
1000
2000
QHC9T
0806,
0808,
0809
77
2000
0
0
0
154000
FBGAG256*
QL7H0
1323
45
1000
0
0
0
45000
VQFPG100*
QL5CL
1309
45
1000
0
0
0
45000
Package
Wafer Lot
A3PE3000
FBGAG484*
A3P600
A3PN250
TOTAL Units for 0.13 µm FPGA =
167
3000
Total Test Cycles =
Unit Hours
244000
TOTAL Failures for 0.13 µm FPGA = 0
Note: *G indicates lead-free.
SoC Reliability Report
73
0.065 μm UMC Flash FPGA Reliability Summary
(SmartFusion2 – M2S (S,T,TS), IGLOO2 – M2GL (S,T,TS)
Product Families
Table 99: High Temperature Operating Life (HTOL)
Test Hours / Failures
Date Number Test
Wafer Lot Code of Units Time
Product
Package
M2S050
FBGAG896
SH5Y8
1
SK1P8
SK1P7
TJ
(°C)
Test
Time
@ TJ
125°C 48 168 500 1000 2000 6000
Unit
Hours
478940
1303
1252
1304
244
1000 138.6
1963
0
0
0
M2S050
FBGAG896
SQ4L9
1318
80
6000 138.6 11777
0
0
0
0
M2S050
FBGAG896
SQ4L9
1318
19
2000 146.8
5772
0
0
0
0
M2S150
FCG11521
SAYLT
SCCTJ
1406
1407
1408
136
6000 133.2
9059
0
0
0
0
M2S090
FGG6771, 2
SCMSP
1409
246
1000
140
2099
0
0
0
3615
48
140.3
102
M2S090
FGG6771, 2
SCTAY
1409
SCTCA
1414
SCMSP
1409
SCTAY
1409
SCTCA
1414
SFKSN
1434
SFPRP14
1436
0
0
942177
109673
0
1232067
516276
369576
SGGAA20 1438
SFKSN
1439
SFPRP14
1441
SGGAA20 1443
TOTAL Units for 0.065 µm FPGA =
4340
Total Test Time Hours 3648709
TOTAL Failures for 0.065 µm FPGA = 0
Notes:
1. G indicates lead-free.
2. Automotive (AEC-Q100).
74
SoC Reliability Report
Table 100: Low Temperature Operating Life (LTOL)
Test Hours / Failures
TJ
Product
Package
Wafer Lot
Date
Code
Number
of Units
M2S050
FBGAG896*
SK1P7
1304
35
1000
M2S050
FBGAG896*
SQ4L9
1318
34
M2S150
FCG1152*
SCCTJ
1406
37
TOTAL Units for 0.065 µm FPGA =
168
500
1000
Unit
Hours
-47
0
0
0
35000
1000
-51
0
0
0
34000
1000
-50
0
0
0
37000
Test Time (°C)
106
Total Test Time Hours =
106000
TOTAL Failures for 0.065 µm FPGA = 0
Note: *G indicates lead-free.
Table 101: Temperature Cycle (TC), –55°C to +125°C
Number of Test Cycles/ Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
200
500
700
1000
Cycles
0
84000
M2S050
FBGAG896
SH5Y8
SK1P8
SK1P7
1303
1252
1304
84
1000
0
0
0
M2S150
FCG11521
SCCTJ
1406
1407
1408
81
700
0
0
0
M2S090
FGG6771, 2
SCMSP
1409
237
1000
0
0
0
225
500
0
0
225
700
0
0
225
500
0
0
225
700
0
0
0
225
1000
0
0
0
M2S010
1
FCG11521
SCTAY
1409
SCTCA
1414
SCCTJ
1406
56700
0
237000
112500
1407
1408
M2S150
FCG11521
SCCTJ
1406
0
157500
1407
1408
M2S010
TQG1441, 3
SGQJF
1439
112500
1441
1414
M2S090
FCS325
SCTAY
1421
157500
1425
1426
M2S090
FCS325
SFAKR
1421
0
225000
1422
1423
Note:
1. G indicates lead-free.
2. Grade1, -55ºC to +150ºC.
3. Cond C, -65ºC to +150ºC
SoC Reliability Report
75
Table 101: Temperature Cycle (TC), –55°C to +125°C (continued)
Number of Test Cycles/ Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
200
500
700
M2S150
FCSG5361
SHNNJ
1510
225
700
0
0
0
225
1000
0
0
0
0
225000
1000
Cycles
157500
1511
1512
M2S090
SHTGO
FG676
1505
1506
1507
M2S090
FGG6761
SCMSP
1407
25
1000
0
0
0
0
25000
M2S050
VFG4001
SN9Y144
1325
25
1000
0
0
0
0
25000
M2S050
FGG8961
SK1P8
1301
225
1000
0
0
0
0
225000
SG3N704
1303
SH5Y8
1304
TOTAL Units for 0.065 µm FPGA =
2252
Total Test Cycles=
1800200
TOTAL Failures for 0.065 µm FPGA = 0
Note:
1. G indicates lead-free.
2. Grade1, -55ºC to +150ºC.
3. Cond C, -65ºC to +150ºC
Table 102: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH
Test Hours/Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test Time
50
100
200
264
M2S050
FBGAG8961
SH5Y8
SK1P8
SK1P7
1303
1252
1304
84
264
0
0
0
0
22176
M2S150
FCG11521
SCCTJ
1422
1423
1424
80
264
0
0
0
0
21120
M2S150
FCG11521
SCCTJ
1406
225
264
0
0
0
0
59400
225
264
0
0
0
0
59400
225
264
0
0
0
0
59400
225
264
0
0
0
0
59400
528
Unit
Hours
1407
M2S010
TQG144
1, 2
SGQJF
1408
1439
1441
M2S090
FCS325
SCTAY
1441
1421
1425
M2S090
FCS325
SFAKR
1426
1421
1422
1423
Note:
1. G indicates lead-free.
2. Unbiased HAST(JED22 A118), 130°C and RH = 85%.
76
SoC Reliability Report
Table 102: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH (continued)
Test Hours/Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test Time
50
100
200
264
M2S150
FCSG5361
SHNNJ
1510
225
264
0
0
0
0
SHTGO
1512
1505
225
528
0
0
0
0
528
Unit
Hours
59400
1511
M2S090
FG6762
0
118800
1506
M2S090
FGG6761, 2
SCMSP
1507
1407
25
264
0
0
0
0
6600
M2S050
VFG4001
SN9Y144
1325
25
264
0
0
0
0
6600
M2S050
FGG8961
SK1P8
1301
225
264
0
0
0
0
59400
SG3N704
1303
1304
SH5Y8
TOTAL Units for 0.065 µm FPGA =
2265
Total Test Time Hours=
659360
TOTAL Failures for 0.065 µm FPGA = 0
Note:
1. G indicates lead-free.
2. Unbiased HAST(JED22 A118), 130°C and RH = 85%.
Table 103: High Temperature Storage (HTS), 150°C
Test Hours/Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test Time
500
1000
M2S050
FBGAG896*
SH5Y8
SK1P8
SK1P7
1303
1252
1304
84
1000
0
0
M2S150
FCG1152*
SCCTJ
1406
1407
1408
81
4000
0
0
M2S090
FCG676*
SCMSP
1409
62
1000
0
0
62000
SCTAY
1409
SCTCA
SCCTJ
1414
1406
225
1000
0
0
225000
225
1000
0
0
225000
225
1000
0
0
225000
M2S150
FCG1152*
2000
3000
4000
Unit
Hours
84000
0
81000
1407
M2S010
TQG144*
SGQJF
1408
1439
1441
M2S090
FCS325
SCTAY
1441
1421
1425
1426
Note: *G indicates lead-free.
SoC Reliability Report
77
Table 103: High Temperature Storage (HTS), 150°C (continued)
Test Hours/Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test Time
500
1000
M2S090
FCS325
SFAKR
1421
225
1000
0
0
225000
225
1000
0
0
225000
225
1000
0
0
225000
2000
3000
4000
Unit
Hours
1422
M2S150
FCSG536*
SHNNJ
1423
1510
1511
M2S090
FG676*
SHTGO
1512
1505
1506
M2S090
FGG676*
SCMSP
1507
1407
25
1000
0
0
25000
M2S050
VFG400*
SN9Y144
1325
25
1000
0
0
25000
M2S050
FGG896*
SK1P8
1301
225
1000
0
0
225000
SG3N704
1303
1304
SH5Y8
TOTAL Units for 0.065 µm FPGA =
1850
Total Test Cycles =
2087000
TOTAL Failures for 0.065 µm FPGA = 0
Note: *G indicates lead-free.
Table 104: Endurance/Non-Volatile Memory Cycling Endurance (NVCE): FPGA NVM
Number of Cycles/Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
50
100
500
550
Cycles
M2S050
FBGAG8961, 2
SA1A8
SK1P8
SK1P9
1246
1301
1301
360
550
0
0
0
0
198000
M2S050
FBGAG8961, 3
SQ4L9
1318
94
550
0
0
0
0
51700
M2S150
FCG11521, 4
SAYLT
1402
319
550
0
0
0
0
175450
M2S010
WL5
SLASS
NA
106
500
0
0
0
TOTAL Units for 0.065 µm FPGA =
879
53000
Total Test Cycles =
478150
TOTAL Failures for 0.065 µm FPGA = 0
Notes:
1. G indicates lead-free.
2. NVCE performed at 25°C (225units) & 75°C (135units)
3. NVCE performed at 25°C (47units) & 75°C (47units)
4. NVCE performed at 25°C (239units) & 78°C (80units)
5. Wafer Level
78
SoC Reliability Report
Table 105: Endurance/Non-Volatile Memory Cycling Endurance (NVCE): eNVM
Number of Cycles/Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Cycles
1000
3000
5000
10000
Cycles
M2S050
FBGAG8961, 2
SA1A8
SK1P8
SK1P9
1246
1301
1301
360
10000
0
0
0
0
3600000
M2S150
FBGAG8961, 3
SQ4L9
1318
94
10000
0
0
0
0
940000
M2S010
WL4
SLASS
NA
45
10000
0
0
0
0
45000
TOTAL Units for 0.065 µm FPGA =
499
Total Test Cycles =
4990000
TOTAL Failures for 0.065 µm FPGA = 0
Notes:
1. G indicates lead-free.
2. NVCE performed at 25°C (225units) and 75°C (135units)
3. NVCE performed at 25°C (47units) and 75°C (47units)
4. Wafer Level
Table 106: High Temperature Data Retention (HTDR) for Non-Volatile Memory: After NVCE
Test Hours/Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
M2S050
FBGAG8961, 2
SA1A8
SK1P8
SK1P9
1246
1301
1301
135
10
125
0
M2S050
CQFP2083, 6
SK1P9
SK1P8
SK1P7
1308
132
3000
250
0
M2S050
FBGAG8961, 2
SQ4L9
1318
47
10
125
0
470
M2S150
FCG11521, 4
SAYLT
1402
80
10
125
0
800
M2S150
CQFP2085, 6
SAYLT
1411
80
3000
250
0
TOTAL Units for 0.065 µm FPGA =
Test Time TJ (°C)
474
10
2000
3000
Unit
Hours
1350
0
0
0
0
Total Test Time Hours =
396000
240000
638620
TOTAL Failures for 0.065 µm FPGA = 0
Notes:
1. G indicates lead-free.
2. NVCE: 10K eNVM cycles; 550 NVM cycles performed at 75°C
3. NVCE: 10K eNVM cycles; 550 NVM cycles performed at 25°C
4. NVCE: 550 NVM cycles performed at 78°C (M2S050 eNVM NVCE data is applicable to M2S150, eNVM size is same)
5. NVCE: 550 NVM cycles performed at 25°C (M2S050 eNVM NVCE data is applicable to M2S150, eNVM size is same)
6. Not commercially available (i.e., the engineering package is for reliability testing only)
SoC Reliability Report
79
Table 107: Low Temperature Retention and Read Disturb (LTDR) for Non-Volatile Memory: After NVCE
Test Hours/Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test
Time
168
1000
2000
3000
M2S050
FBGAG8961,2
SA1A8
SK1P8
SK1P9
1246
1301
1301
135
3000
0
0
0
0
M2S050
FBGAG8961,2
SQ4L9
1318
47
1000
0
0
M2S150
FCG11521,3
SAYLT
1402
80
4000
0
0
TOTAL Units for 0.065 µm FPGA =
262
4000
Unit
Hours
405000
47000
0
0
0
Total Test Time Hours=
320000
772000
TOTAL Failures for 0.065 µm FPGA = 0
Note:
1. G indicates lead-free.
2. NVCE: 10K eNVM cycles; 550 NVM cycles performed at 25°C
3. NVCE: 550 NVM cycles performed at 25°C (M2S050 eNVM NVCE data is applicable to M2S150, eNVM size is same)
4. LTDR performed at 25°C
Table 108: High Temperature Storage Life (HTSL), 150°C: After NVCE
Test Hours/Failures
Product
Package
Wafer Lot
Date
Code
Number
of Units
Test Time
500
1000
2000
3000
Unit
Hours
M2S050
FBGAG8961,2
SA1A8
SK1P8
SK1P9
1246
1301
1301
135
3000
0
0
0
0
405000
M2S150
FCG11521,3
SAYLT
1402
79
3000
0
0
0
0
237000
TOTAL Units for 0.065 µm FPGA =
214
Total Test Cycles =
642000
TOTAL Failures for 0.065 µm FPGA = 0
Note:
1. G indicates lead-free.
2. NVCE: 10K eNVM cycles; 550 NVM cycles performed at 25°C
3. NVCE: 550 NVM cycles performed at 25°C (M2S050 eNVM NVCE data is applicable to M2S150, eNVM size is same)
80
SoC Reliability Report
List of Changes
The following table lists critical changes that were made in the current version of the document.
Revision
Revision 13
December 2015
Changes
Table 1: Reliability Summary: FIT Rate by Device Technology (SAR 74739)
Page
4, 6
FIT rates for the following device technology have been updated
•
•
0.065 um UMC Flash CMOS FPGA
0.13 um Infineon Flash CMOS FPGA (ProASIC3- A3P)
Table 2: Reliability Summary: FIT Rate by Device Technology and Product Family (SAR
74739)
•
5
Added Note 3 for IGLOO2 on Accelerated Programming Qualification.
Updated "0.13 µm Infineon Flash FPGA Reliability Summary (ProASIC3 – A3P)" (SAR
74739)
56
Table 65: Low Temperature Operating Life (LTOL) at –55°C after 550 Program/Erase
Cycles (SAR 74739)
57
•
Added A3P250-VQG, W/L ZA418036, 231 pcs, 500cycles@ -65°C to +150°C
Table 66: Temperature Cycle (TC), –55°C to +125°C (SAR 74739)
•
Added A3P250-VQG, W/L ZA418036, 231 pcs, 500cycles@ -65°C to +150°C
Table 67: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH (SAR 74739)
•
•
•
60
Added A3P250-VQG100,W/L ZA418036, 77pcs, 1000hrs at 150ºC
Table 100: Low Temperature Operating Life (LTOL) (SAR 74739)
•
59
Added A3P250-VQG100,W/L ZA418036, 231pcs, 96hrs UHAST at 130ºC and 85%
RH
Added A3P250-VQG100,W/L ZA418036, 231pcs, 96hrs Biased HAST at 130ºC and
85% RH
Added A3P1000-FGG256, W/L ZA424029, 45pcs, 264rs UHAST at 130ºC and 85%
RH
Table 68: High Temperature Storage (HTS), 150°C (SAR 74739)
•
58
75
Added A3P250-VQG100,W/L ZA418036
Updated "0.065 μm UMC Flash FPGA Reliability Summary (SmartFusion2 – M2S (S,T,TS),
IGLOO2 – M2GL (S,T,TS) Product Families" Product Families, FIT changed from 6.05 to
3.22 (SAR 74739)
74
Table 99: High Temperature Operating Life (HTOL) (SAR 74739)
74
•
Added M2S150-FCG1152, W/L SAYLT/SCCTJ, 136pcs, 4000hrs @ 133.2°C
Table 101: Temperature Cycle (TC), –55°C to +125°C (SAR 74739)
•
•
•
•
•
•
•
•
•
SoC Reliability Report
75
Added M2S150-FCG1152, W/L SCCTJ, 225pcs, 700cycles @ -55°C to +125°C
Added M2S010-TQ/TQG144, W/L SGQJF, 225pcs, 500cycles @ -65°C to +150°C
Added M2S090-FCS325, W/L SCTAY,225pcs,700cycles @ -55°C to +125°C
Added M2S090-FCS325, W/L SFAKR,225pcs,1000cycles @ -55°C to +125°C
Added M2S150-FCSG536,W/L SHNNJ, 225pcs, 700cycles @ -55°C to +125°C
Added M2S090-FG676,W/L SHTGQ, 225pcs, 1000cycles @ -55°C to +125°C
Added M2S090-FGG676,W/L SCMSP, 25pcs, 1000cycles @ -55°C to +125°C
Added M2S050-VF400, W/L SN9Y144, 25pcs, 1000cycles @ -55°C to +125°C
Added M2S050-FGG896, W/L SK1P8,SG3N704,SH5Y8, 225pcs, 1000cycles @ 55°C to +125°C
81
Table 102: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH (SAR 74739)
•
•
•
•
•
•
•
•
•
•
Table 103: High Temperature Storage (HTS), 150°C (SAR 74739)
•
•
•
•
•
•
•
•
•
•
77
Added M2S150-FCG1152, W/L SCCTJ, 81pcs, 4000hrs @ 150°C
Added M2S150-FCG1152, W/L SCCTJ, 235pcs,1000hrs @ 150°C
Added M2S010-TQ/TQG144, W/L SGQJF, 225pcs, 1000hrs @ 150°C
Added M2S090-FCS325, W/L SCTAY, 225pcs, 1000hrs @ 150°C
Added M2S090-FCS325, W/L SFAKR, 225pcs, 1000hrs @ 150°C
Added M2S150-FCSG536, W/L SHNNJ, 225pcs, 1000hrs @ 150°C
Added M2S090-FG676, W/L SHTGQ, 225pcs, 1000hrs @ 150°C
Added M2S090-FGG676, W/L SCMSP, 25pcs, 1000hrs @ 150°C
Added M2S050-VF400,W/L SN9Y144,25pcs, 1000hrs @ 150°C
Added M2S050-FGG896, W/L SK1P8,SG3N704,SH5Y8, 225pcs,1000hrs @ 150°C
Table 104: Endurance/Non-Volatile Memory Cycling Endurance (NVCE): FPGA NVM (SAR
74739)
•
Revision 12
September 2014
80
Added M2S150-FCG1152, W/L SCCTJ,80pcs, 4000hrs
Updated Table 1: Reliability Summary: FIT Rate by Device Technology.
4
FIT rates for the following device technology have been updated:
•
•
•
•
•
•
•
•
•
82
79
Added M2S150-FCG1152, W/L SCCTJ,80pcs, 3000hrs
Table 107: Low Temperature Retention and Read Disturb (LTDR) for Non-Volatile Memory:
After NVCE (SAR 74739)
•
79
Added M2S010-WL SLASS, 45pcs, 1000 cycles
Table 106: High Temperature Data Retention (HTDR) for Non-Volatile Memory: After NVCE
(SAR 74739)
•
78
Added M2S010-WL SLASS, 106pcs, 500cycles
Table 105: Endurance/Non-Volatile Memory Cycling Endurance (NVCE): eNVM (SAR
74739)
•
76
Added M2S150-FCG1152, W/L SCCTJ, 225pcs, 264hrs at 110ºC and 85% RH
Added M2S010-TQ/TQG144, W/L SGQJF, 225pcs,264hrs at 130ºC and 85% RH
Added M2S090-FCS325, W/L SCTAY, 225pcs, 264hrs at 110ºC and 85% RH
Added M2S090-FCS325, W/L SFAKR, 225pcs, 264hrs at 110ºC and 85% RH
Added M2S150-FCSG536, W/L SHNNJ, 225pcs, 264hrs at 110ºC and 85% RH
Added M2S090-FG676,W/L SHTGQ 225pcs, 264hrs at 110ºC and 85% RH
Extended M2S090-FG676,W/L SHTGQ, 225pcs, to 528hrs at 110ºC and 85% RH
Added M2S090-FGG676,W/L SCMSP, 25pcs, 264hrs at 110ºC and 85% RH
Added M2S050-VF400,W/L SN9Y144, 25pcs, 264hrs at 110ºC and 85% RH
Added M2S050-FGG896, W/L SK1P8,SG3N704,SH5Y8, 225pcs, 264hrs at 110ºC
and 85% RH
0.45 µm CSM CMOS FPGA
0.45 µm UMC CMOS FPGA
0.25 µm UMC CMOS FPGA
0.22 µm UMC CMOS FPGA
0.22 µm UMC Flash CMOS FPGA
0.15 µm UMC CMOS FPGA
0.13 µm IFX Flash CMOS FPGA
0.13 µm UMC Flash CMOS FPGA
0.065 µm UMC Flash CMOS FPGA
SoC Reliability Report
Updated Table 2: Reliability Summary: FIT Rate by Device Technology and Product Family.
•
•
•
•
•
•
•
•
•
•
Table 3: Summary of ESD Performance for All Product Families (TM 3015/JESD22-A114)
•
•
5
0.45 µm CSM CMOS FPGA (A42MX)
0.45 µm CSM CMOS FPGA (A42MX)
0.25 µm UMC CMOS FPGA (RTSX-SU)
0.22 µm UMC CMOS FPGA (SX-A)
0.22 µm UMC Flash CMOS FPGA (APA)
0.15 µm UMC CMOS FPGA (RTAX-S)
0.13 µm IFX Flash CMOS FPGA (A3P & A2F)
0.13 µm UMC Flash CMOS FPGA (A3P/RT3PEL & AGL)
0.065 µm UMC Flash CMOS FPGA (M2S/M2GL)
Added footnote 2 “IGLOO2 – M2GL family of devices is covered under 0.065um
SmartFusion2 – M2S FPGA family by similarity”.
7
Added SmartFusion2 and IGLOO2 device family members
Updated footnote 9
Updated 0.45um CSM FPGA Reliability Summary, FIT changed from 19.62 to 18.05.
Table 23: High Temperature Operating Life (HTOL)
25
Added: A42MX36-CQ208, W/L HPY9H00, 80pcs, 2000hrs @ 125°C
Updated 0.45um UMC FPGA Reliability Summary, FIT changed from 35.79 to 24.06
27
Table 27: High Temperature Operating Life (HTOL)
Added: A42MX24-PQ208,W/L HPY9H00, 80pcs, 2000hrs @ 125°C
Updated 0.25µm UMC FPGA Reliability Summary, FIT changed from 1.18 to 1.17.
34
Table 45: CMOS Reliability – High Temperature Operating Life (HTOL)
•
•
•
Added RTSX72SU-CQ256, W/L D6AA61, 80pcs, 1000hrs @ 125°C
Corrected WL# from D1N8F1 to D1N8A1 for RTSX72SU, DC 0641, 15units,
1000hrs @ 125°C
Added Reliability Summary for Silicon Sculptor Programming Software
Updated 0.22um UMC FPGA Reliability Summary, FIT changed from 1.78 to 1.76.
40
Table 49: CMOS High Temperature Operating Life (HTOL)
Added: A54SX72A-CQ208, W/L D77SP1, 80pcs, 1000hrs @ 125°C
Updated 0.22um UMC Flash FPGA Reliability Summary, FIT changed from 13.28 to 10.77.
45
Table 53: High Temperature Operating Life (HTOL)
•
•
•
Revision 12
September 2014
(continued)
Added APA300-CQ208, W/L MK91G, 24pcs, 2000hrs @ 125°C
Added APA1000-CQ208, W/L MWJ9W, 78pcs, 1000hrs @ 125°C
Added APA300-CQ208, W/L R21A5, 80pcs, 1000hrs @ 125°C
Updated 0.15 μm UMC FPGA Reliability Summary, FIT changed from 7.04 to 6.82.
47
Table 59: High Temperature Operating Life (HTOL)
SoC Reliability Report
•
•
•
•
•
Added RTAX2000S-CQ256, W/L D71CM1, 79pcs, 1000hrs @ 125°C
Added RTAX2000SL-CQ256, W/L D6CTH1, 23pcs, 2000hrs @ 125°C
Added RTAX2000S-CQ352, W/L D6CN21, 24pcs, 2000hrs @ 125°C
Added RTAX4000DL-CQ352, W/L D64NH1, 7pcs, 2000hrs @ 125°C
Added Reliability Summary for Silicon Sculptor Programming Software
83
Updated 0.13μm Infineon Flash FPGA Reliability Summary (ProASIC3 – A3P), FIT
changed from 4.18 to 4.01.
56,
58–60
Table 64: High Temperature Operating Life (HTOL) After 550 Program/Erase Cycles
Added A3P1000-BGAG484, W/L ZA252062, 77pcs, 1000hrs @ 134°C
Table 66: Temperature Cycle (TC), –55°C to +125°C
•
Added A3P1000-PQG208, W/L ZA31005102, 47pcs, 500cycles at -65ºC to +150ºC
(Condition C)
• Added A3P250-QNG132, W/L ZA249133, 47pcs, 500cycles at -65ºC to +150ºC
(Condition C)
Table 67: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH
•
Added A3P1000-PQG208, W/L ZA31005102, 47pcs, 96hrs UHAST at 130ºC and
85% RH
• Added A3P250-QNG132, W/L ZA249133, 47pcs, 96hrs UHAST at 130ºC and 85%
RH
Table 68: High Temperature Storage (HTS), 150°C
•
•
Added A3P1000-PQG208, W/L ZA31005102, 45pcs, 1000hrs at 150ºC
Added A3P250-QNG132, W/L ZA249133, 47pcs, 1000hrs at 150ºC
Updated 0.13μm Infineon Flash FPGA Reliability Summary (SmartFusion – A2F), FIT
changed from 11.70 to 10.51.
66
Table 81: High Temperature Operating Life (HTOL) after 550 Program/Erase Cycles
Added A2F200-FGG484, W/L ZA027289, 76pcs, 1000hrs @ 133°C
Table 82: High Temperature Storage (HTS), 150°C
Added A2F200-FGG484, W/L ZA027289, 47pcs, 1000hrs @ 150°C
Table 83: Temperature Humidity Bias (THB), 85°C / 85% RH
Added A2F200-FGG484, W/L ZA027289, 53pcs, 1008hrs @ 85°C / 85% RH
Updated 0.13μm UMC Flash FPGA Reliability Summary (IGLOO – AGL/AGLE; IGLOO
PLUS – AGLP; IGLOO nano – AGLN), FIT changed from 7.22 to 6.78.
68–70
Table 87: High Temperature Operating Life (HTOL) after 550 Program/Erase Cycles
Added AGL1000-FGG484, W/L QL1Y6, 75pcs, 1000hrs @ 132°C
Table 89: Temperature Cycle (TC), –55°C to +125°C
Added AGLP030-VQG128, W/L QJY60, 47pcs, 500cycles @ -65ºC to +150ºC
(Condition C)
Table 90: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH
Added AGLP030-VQG128, W/L QJY60, 47pcs, 96hrs at 130ºC and 85% RH
Table 91: High Temperature Storage (HTS), 150°C
Added AGL1000-FGG484, W/L QL1Y6, 47pcs, 1000hrs @ 150°C
Revision 12
September 2014
(continued)
Updated 0.13μm UMC Flash FPGA Reliability Summary (ProASIC3, ProASIC3E – A3P,
A3PE; ProASIC3L, ProASIC3EL – A3PL, A3PEL;ProASIC3 nano – A3PN,
RT ProASIC3 – RT3P), FIT changed from 15.54 to 14.15
72, 73
Table 94: High Temperature Operating Life (HTOL) after 550 Program/Erase Cycles
• Added RT3PE3000L-CGA484, W/L QKN6Y, 80pcs, 1000hrs @ 125°C
• Added RT3PE3000L-CGA484, W/L QJA2G, 78pcs, 1000hrs @ 125°C
• Added RT3PE3000L-LGA896, W/L QJA2G, 6pcs, 1000hrs @ 125°C
Table 96: Temperature Cycle (TC), –55°C to +125°C
•
•
Added A3P600-FGG256, W/L QL7H0, 45pcs, 700cycles @ -55°C to +125°C
Added A3PN250-VQG100, W/L QL5CL, 45pcs, 500cycles @ -65ºC to +150ºC
(Condition C)
Table 97: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH
Added A3PN250-VQG100, W/L QL5CL, 45pcs, 1000hrs @ 85°C / 85% RH
Table 98: High Temperature Storage (HTS), 150°C
•
•
84
Added A3P600-FGG256, W/L QL7H0, 45pcs, 1000hrs @ 150°C
Added A3PN250-VQG100, W/L QL5CL, 45pcs, 1000hrs @ 150°C
SoC Reliability Report
Revision 12
September 2014
(continued)
Updated 0.065μm UMC Flash FPGA Reliability Summary (SmartFusion2 – M2S (S,T,TS),
IGLOO2 – M2GL (S,T,TS) Product Families, FIT changed from 24.51 to 6.05
73,
75–80
Table 99: High Temperature Operating Life (HTOL)
• Added M2S050-FG896, W/L SQ4L9, 80pcs, 6000hrs @ 138.6°C
• Added M2S050-FG896, W/L SQ4L9, 19pcs, 2000hrs @ 146.8°C
• Added M2S150-FCG1152, W/L SAYLT/SCCTJ, 136pcs, 2000hrs @ 133.2°C
Table 100: Low Temperature Operating Life (LTOL)
• Added M2S050-FG896, W/L SQ4L9, 34pcs, 1000hrs @ -51°C
• Added M2S150-FCG1152, W/L SCCTJ, 37pcs, 1000hrs @ -50°C
Table 101: Temperature Cycle (TC), –55°C to +125°C
Added M2S150-FCG1152, W/L SCCTJ, 81pcs, 700cycles @ -55°C to +125°C
Table 102: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH
Added M2S150-FCG1152, W/L SCCTJ, 80pcs, 264hrs at 110ºC and 85% RH
Table 103: High Temperature Storage (HTS), 150°C
Added M2S150-FCG1152, W/L SCCTJ, 81pcs, 1000hrs @ 150°C
Table 104: Endurance/Non-Volatile Memory Cycling Endurance (NVCE): FPGA NVM
•
For M2S050-FG896, W/L SA1A8/SK1P8/SK1P9 corrected total units from 231 to
360
• Added M2S050-FG896, W/L SQ4L9, 94pcs, 550cycles
• Added M2S150-FCG1152, W/L SAYLT, 319pcs, 550cycles
• Added footnotes to clarify NVCE test temperatures
Table 105: Endurance/Non-Volatile Memory Cycling Endurance (NVCE): eNVM
•
For M2S050-FG896, W/L SA1A8/SK1P8/SK1P9 corrected total units from 231 to
360
• Added M2S050-FG896, W/L SQ4L9, 94pcs, 10,000cycles
• Added footnotes to clarify NVCE test temperatures
Table 106: High Temperature Data Retention (HTDR) for Non-Volatile Memory: After NVCE
•
Updated M2S050-CQ208, W/L SA1A8/SK1P8/SK1P9, 132pcs, from 1000hrs to
3000hrs @ 250°C (additional hrs completed), knowledge based testing
• Added M2S050-FG896, W/L SQ4L9, 47pcs, 10hrs @ 125°C (per JEDEC 47)
• Added M2S150-FCG1152, W/L SAYLT, 80pcs, 10hrs @ 125°C (per JEDEC 47)
• Added M2S150-CQ208, W/L SAYLT, 80pcs, 2000hrs @ 250°C, knowledge based
testing
• Added footnotes to clarify NVCE cycles and test temperatures
Table 107: Low Temperature Retention and Read Disturb (LTDR) for Non-Volatile Memory:
After NVCE
•
Updated M2S050-CQ208, W/L SA1A8/SK1P8/SK1P9, 135pcs, from 1000hrs to
3000hrs @ 25°C (additional hrs completed)
• Added M2S050-FG896, W/L SQ4L9, 47pcs, 1000hrs @ 25°C
• Added M2S150-FCG1152, W/L SAYLT, 80pcs, 2000hrs @ 25°C
• Corrected footnote 2 from 1K to 10K eNVM cycles
• Added footnote 3
Table 108: High Temperature Storage Life (HTSL), 150°C: After NVCE
•
•
•
Updated M2S050-FG896, W/L SA1A8/SK1P8/SK1P9, 90pcs, from 1000hrs to
3000hrs @ 150°C (additional hrs completed)
Added M2S150-FCG1152, W/L SAYLT, 79pcs, 3000hrs @ 150°C
Added footnote 3
General update, footnote added for all Flash retention 250ºC testing to clarify units
assembled in CQFP packages are not commercially available (i.e., the engineering
package is for reliability testing only)
NA
General correction: Package type corrected from FPGA to FBGA
NA
SoC Reliability Report
85
Updated Table 1: Reliability Summary: FIT Rate by Device Technology.
Revision 11
Added FIT rate for 0.065 µm UMC Flash CMOS FPGA device technology.
May 2013,
51000001-11/05.13
4
Updated Table 2: Reliability Summary: FIT Rate by Device Technology and Product Family.
5
Added FIT rate for 0.065 µm UMC Flash CMOS FPGA (SmartFusion2 - M2S) device
technology.
Updated Table 3: Summary of ESD Performance for All Product Families (TM 3015/
JESD22-A114). Added SmartFusion2 ESD performance data and footnote 9.
Added reliability data for 0.065 µm UMC Flash CMOS FPGA (SmartFusion2 - M2S) device
technology Table 99: High Temperature Operating Life (HTOL) to Table 108: High
Temperature Storage Life (HTSL), 150°C: After NVCE.
Updated Table 1: Reliability Summary: FIT Rate by Device Technology. FIT rates for the
Revision 10,
November 2012,
following device technology have been updated:
51000001-10/11.12
• 1.0 µm CMOS FPGA
• 0.45 µm CSM CMOS FPGA
• 0.45 µm UMC CMOS FPGA
• 0.22 µm UMC CMOS FPGA
• 0.22 µm UMC Flash CMOS FPGA
• 0.15 µm UMC CMOS FPGA
• 0.13 µm UMC Flash CMOS FPGA
Updated Table 2: Reliability Summary: FIT Rate by Device Technology and Product Family.
FIT rates for following device technology have been updated:
•
•
•
•
•
•
•
7
74- 80
4
5
1.0 µm CMOS FPGA (ACT1)
0.45 µm CSM CMOS FPGA (A42MX)
0.45 µm CSM CMOS FPGA (A42MX)
0.22 µm UMC CMOS FPGA (SX-A)
0.22 µm UMC Flash CMOS FPGA (APA)
0.15 µm UMC CMOS FPGA (RTAX-S)
0.13 µm UMC Flash CMOS FPGA (ProASIC3 – A3P/RT3PEL)
Updated Table 3: Summary of ESD Performance for All Product Families (TM 3015/
JESD22-A114): Added footnote 4 to A3P125: “Passed 2000V HBM on all pins except
VCC_PLL, which meets 500V."
7
Updated 1.0 µm FPGA reliability data, FIT changed from 5.68 to 5.62.
9
Table 6: High Temperature Operating Life (HTOL)
Added: A1020B-CQ84B, W/L FP6502401, 79pcs, 615hrs @ 125°C.
25
Updated 0.45 µm CSM FPGA reliability data, FIT changed from 22.30 to 19.62.
Table 23: High Temperature Operating Life (HTOL)
•
•
Added: A42MX36-CQ256, W/L 2ACH323581, 80pcs, 1000 hrs @ 125°C.
Added: A42MX36-CQ256, W/L 2ACG311291, 79pcs1000 hrs @ 125°C.
27
Updated 0.45 µm UMC FPGA reliability data, FIT changed from 69.06 to 35.79
Table 27: High Temperature Operating Life (HTOL)
• Added: A42MX24-PQ208, W/L HMGN000, 79pcs, 2000hrs @ 125°C.
• Corrected units hours for A40MX04-PL84, W/L HKJAH00 from 9,000 to 90,000
• Corrected unit hours for A42MX24-PQ208, W/L HLF8Q0G from 8,000 to 80,000
• Updated total unit hours accordingly
Table 30: High Temperature Storage (HTS), 150°C
•
•
•
86
Corrected units hours for A40MX04-PL84, W/L HKJAH00 from 8,000 to 80,000
Corrected unit hours for A42MX24-PQ208, W/L HKJNS00 from 8,000 to 80,000
Updated total unit hours accordingly to 160,000
SoC Reliability Report
Updated 0.25 µm UMC FPGA reliability data
Revision 10,
November 2012,
Table 45: CMOS Reliability – High Temperature Operating Life (HTOL)
51000001-10/11.12
• Corrected product name from RTSX32SU to RTSX72SU for, W/L D1N8A1, DC
(continued)
0831, 12pcs, 1000hrs @ 125°C
• Corrected product name from RTSX32SU to RTSX72SU and DC from 0831 to 0939
for W/L D1SG01, 100pcs, 168hrs @ 125°C
Updated 0.22 µm UMC FPGA reliability data, FIT changed from 1.83 to 1.78.
34
39
Table 48: Unit-hours of Life Test Data Accumulated on Radiation-Tolerant FPGAs
•
•
Added: A54SX32A-CQ208, W/L D5GTW1, DC 1125, 80pcs, 1000hrs @ 125°C
Added: A54SX72A-PQ208, W/L D54RJ1, DC 1036, 100pcs, 168hrs @ 125°C
Updated 0.22 µm UMC Flash FPGA reliability data, FIT changed from 15.85 to 13.28
45
Table 53: High Temperature Operating Life (HTOL)
•
•
•
Added: APA1000-CQ352, W/L MR91L, DC 1025, 24pcs, 2000hrs @ 125°C
Added: APA300-PQ208, W/L MTG7J02, DC 1045, 77pcs, 168hrs @ 125°C
Added: APA600-CQ208, W/L R00KY, DC 1226, 80pcs, 1000hrs @ 125°C
Updated 0.15 µm UMC FPGA reliability data, FIT changed from 7.25 to 7.04
47
Table 59: High Temperature Operating Life (HTOL)
•
•
•
•
•
Added: RTAX2000S-CQ352, W/L D55A21, DC 1049, 7pcs, 1000hrs @ 125°C
Added: RTAX2000SL-CQ256, W/L D55A31, DC 1052, 22pcs, 2000hrs @ 125°C
Added: RTAX2000S-CQ352, W/L D54C81, DC 1106, 8pcs, 1000hrs @ 125°C
Added: RTAX2000S-CQ352, W/L D63WS1, DC 1225, 80pcs, 1000hrs @ 125°C
Added: RTAX4000SL-CQ352, W/L D41891, DC 1110, 24pcs, 1000hrs @ 125°C
Updated 0.13 µm UMC Flash FPGA reliability data, FIT changed from 8.14 to 7.87
72
(ProASIC3, ProASIC3E – A3P, A3PE; ProASIC3L, ProASIC3/EL – A3PL, AEPEL;
ProASIC3 nano – A3PN, RT ProASIC3 – RT3P)
Table 94: High Temperature Operating Life (HTOL) after 550 Program/Erase Cycles
•
•
Revision 9,
August 2011,
51000001-9/8.11
Added: RT3PE3000L-CG896, W/L QJA2G, DC 1205, 47pcs, 2307hrs @ 125°C
Corrected number of units tested from 82pcs to 81pcs for RT3PE3000L-CG896,
W/L QHR8G, DC 0925
Updated Table 1: Reliability Summary: FIT Rate by Device Technology. FIT rates for the
following device technology have been updated:
•
•
•
•
•
•
1.0 µm CMOS FPGA
0.25 µm UMC CMOS FPGA
0.22 µm UMC Flash CMOS FPGA
0.15 µm UMC CMOS FPGA
0.13 µm Infineon Flash CMOS FPGA
0.13 µm UMC Flash CMOS FPGA
Updated Table 2: Reliability Summary: FIT Rate by Device Technology and Product Family.
FIT rates for following device technology have been updated:
•
•
•
•
•
•
•
SoC Reliability Report
4
5
1.0 µm CMOS FPGA (ACT 2)
0.25 µm UMC CMOS FPGA (RTSX-SU)
0.22 µm UMC Flash CMOS FPGA (SX-A)
0.15 µm UMC CMOS FPGA (RTAX-S)
0.13 µm Infineon Flash CMOS FPGA (SmartFusion – A2F)
0.13 µm UMC Flash CMOS FPGA (IGLOO - AGL)
0.13 µm UMC Flash CMOS FPGA (ProASIC3 – A3P/RT3PEL)
87
Revision 9,
August 2011,
51000001-9/8.11
(continued)
Updated 1.0 µm FPGA reliability data, FIT changed from 5.57 to 5.68.
9
Table 6: High Temperature Operating Life (HTOL): Fit increased slightly as four duplicate
entries were removed and added one new.
Removed:
• A1280A-CQ172, W/L U1H363, 58pcs, 615hrs at 125°C.
• A1280A-CQ172, W/L U1H83, 45pcs, 1671hrs at 125°C.
• A1280A-PGA176, W/L U1H511, 77pcs, 615hrs at 125°C.
• A1280A-CQ172, W/L U1H439, 18pcs, 1000 hrs at 125°C.
Added: A1280A-CQFP172, W/L FP5986501, 80pcs, 1000 hrs at 125°C.
Updated 0.45 µm UMC FPGA Reliability Summary Table 27 to Table 30. Corrected the W/L
numbers and date codes for all line items.
27
Updated 0.25 µm FPGA reliability data, FIT improved from 1.25 to 1.18.
Table 45: CMOS Reliability – High Temperature Operating Life (HTOL), added three new line
items:
•
•
•
RTSX72SU-CQ256, W/L D303Y1,80 pcs, 6000 hrs at 125°C
RTSX72SU-CQ208, W/L D1SG11, 24 pcs, 2000 hrs at 125°C
RTSX32SU-CQ84, W/L D1RH51, 24 pcs, 2000 hrs at 125°C
34
Updated 0.22 µm FPGA reliability data, FIT changed from 1.834 to 1.831.
Table 48: Unit-hours of Life Test Data Accumulated on Radiation-Tolerant FPGAs, added
one new line item:
• A54SX72A-CQ208, W/L D4TW61, 80 pcs, 1000 hrs at 125°C
Correction to Table 48: Unit-hours of Life Test Data Accumulated on Radiation-Tolerant
FPGAs for total devices tested:
•
•
In Revision 8, total devices was incorrectly reported as 4770 (typo); should have
been 4470 (Total Device Hrs and corresponding FIT were reported correctly).
For Revision 9, total device tested = 4470 + 80 = 4550.
39
Updated 0.15 µm FPGA reliability data, FIT changed from 7.58 to 7.25.
Table 59: High Temperature Operating Life (HTOL), added six new line items:
• RTAX2000S-CQFP352, W/L D517P1, 79 pcs, 1500 hrs at 125°C
• RTAX2000S-CQFP352, W/L D4CYF1, 80 pcs, 1000 hrs at 125°C
• RTAX2000S-CQFP352, W/L D4CYF1, 8 pcs, 2000 hrs at 125°C
• RTAX4000S-CQFP352, W/L D3T0N1, 44 pcs, 1000 hrs at 125°C
• RTAX4000S-CGA1152, W/L D404N1, 6 pcs, 1000 hrs at 125°C
• RTAX4000D-CQFP352, W/L D4LJQ1, 47 pcs, 1000 hrs at 125°C
47
Table 62: Temperature Cycle:
• Added new line RTAX4000D-CQFP352, W/L D4LJQ1, 15 pcs, 100 cycles at –65°C
to 150°C.
• Removed reference to note as all TC line items tested from –65°C to 150°C.
54
Updated 0.13 µm Infineon Flash FPGA (ProASIC3 – A3P) reliability data:
Table 66: Temperature Cycle (TC), –55°C to +125°C: Added new line
• A3P250-VQFP100, W/L ZA840056, 47 pcs, 500 cycles at –65°C to +150°C
58
Table 67: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH: Added new
line
•
A3P250-VQFP100, W/L ZA840056, 47pcs, 100 hrs of UHAST at 130 °C, 85% RH
59
Updated 0.13 µm Infineon Flash FPGA (Fusion – AFS) reliability data:
Table 74: Temperature Cycle (TC), –55°C to +125°C: Added new line
•
88
AFS600-FPGAG4881, W/L ZA932055, 47 pcs, 1000 cycles at –55°C to +125°C
64
SoC Reliability Report
Revision 9,
August 2011,
51000001-9/8.11
(continued)
Updated 0.13 µm Infineon Flash FPGA (SmartFusion – A2F) reliability data, FIT improved
from 30.11to 11.7
Table 81: High Temperature Operating Life (HTOL) after 550 Program/Erase Cycles:
Updated additional HTOL hrs and a new line for A2F500:
•
•
•
Updated A2F200-FGG484, W/L ZA917060/ZA91706101/ZA94100501, 247 pcs to
2000 hrs
Updated A2F200-FGG484, W/L ZA925010, 82 pcs to 1000 hrs
Added A2F500-FGG484, W/L ZA0140281, 82 pcs, 1000 hrs at 136°C
66
Updated 0.13 µm UMC Flash FPGA Reliability Data (IGLOO – AGL/AGLE; IGLOO PLUS –
AGLP; IGLOO nano - AGLN).
Table 87: High Temperature Operating Life (HTOL) after 550 Program/Erase Cycles: Added
HTOL data, FIT improved from 7.70 to 7.22
•
Added AGL600-FGG256, W/L QHSYQ, 79 pcs, 1000 hrs at 130°C
68
Updated 0.13 µm UMC Flash FPGA reliability data (ProASIC3, ProASIC3E – A3P, A3PE;
ProASIC3L, ProASIC3/EL – A3PL, AEPEL; ProASIC3 nano – A3PN, RT ProASIC3 –
RT3P).
Table 94: High Temperature Operating Life (HTOL) after 550 Program/Erase Cycles:
Reformatted entire table to show data correctly.
Updated units and Tj for line item below, FIT improved from 17.86 to 16.60.
RT3PE3000L-CGA896, W/L QHR8G, 82 pcs, 1000 hrs at 142°C
– Updated Tj to 142°C from 125°C (Ta)
– Updated units from 79 to 82
Table 96: Temperature Cycle (TC), –55°C to +125°C: Added new line:
72
•
• RT3PE3000L-CGA8962, W/L QHR8G, 15 pcs, 100 cycles at –65°C to +150°C
Table 98: High Temperature Storage (HTS), 150°C: Added new line:
•
Revision 8,
May 2010,
51000001-8/5.10
·A3PE3000-FPGAG484, W/L QHR8G, 72 pcs, 3000 hrs at 150°C
Updated Table 1: Reliability Summary: FIT Rate by Device Technology.
73
73
4
FIT rates for the following device technology have been updated:
• 1.0 µm CMOS FPGA
• 0.8 µm CMOS FPGA
• 0.45 µm CSM CMOS FPGA
• 0.45 µm UMC CMOS FPGA – Added
• 0.25 µm UMC CMOS FPGA
• 0.22 µm UMC Flash CMOS FPGA
• 0.15 µm UMC CMOS FPGA
• 0.13 µm Infineon Flash CMOS FPGA
• 0.13 µm UMC Flash CMOS FPGA
Added footnote for MTBF versus MTTF under Table 1.
For 0.8 µm CMOS FPGA, Table 1 had a typo of 1 failure (Table 2 and Table 13 were
correct).
SoC Reliability Report
89
Revision 8,
May 2010,
51000001-8/5.10
(continued)
Updated Table 2: Reliability Summary: FIT Rate by Device Technology and Product
Family. FIT rates for following device technology have been updated:
•
•
•
•
•
1.0 µm CMOS FPGA, ACT1 & ACT2
0.8 µm CMOS FPGA (ACT3)
0.45 µm CSM CMOS FPGA
0.45 µm UMC CMOS FPGA – Added
0.25 µm UMC CMOS FPGA (RTSX-SU)
•
•
•
•
•
•
•
0.22 µm UMC Flash CMOS FPGA (ProASICPLUS)
0.15 µm UMC CMOS FPGA (RTAX-S)
0.13 µm Infineon Flash CMOS FPGA (ProASIC3 – A3P)
0.13 µm Infineon Flash CMOS FPGA (Fusion – AFS)
0.13 µm Infineon Flash CMOS FPGA (SmartFusion – A2F)
0.13 µm UMC Flash CMOS FPGA (IGLOO - AGL)
0.13 µm UMC Flash CMOS FPGA (ProASIC3 – A3P/RT3PEL)
5
Updated Table 3: Summary of ESD Performance for All Product Families (TM 3015/
JESD22-A114).
7
Updated 1.0 µm FPGA reliability data, FIT improved from 6.49 to 5.57.
9
Table 6: High Temperature Operating Life (HTOL): Added HTOL data and footnote 3.
Removed duplicate entry for A1280A-CQ172B, W/L U1H486, 1000 hrs at 125°C.
Updated 0.8 µm FPGA reliability data, Table 13: High Temperature Operating Life (HTOL).
Added HTOL data; FIT improved from 5.46 to 4.47.
16
Updated 0.45 µm CSM FPGA reliability data, Table 23: High Temperature Operating Life
(HTOL). Added HTOL data; FIT improved from 26.8 to 22.3.
25
Updated 0.45 µm UMC FPGA Reliability Data to ORT Report: Added the following tables:
27
Table 27: High Temperature Operating Life (HTOL)
Table 28: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH
Table 29: Temperature Cycle (TC), –55°C to +125°C
Table 30: High Temperature Storage (HTS), 150°C
Updated 0.25 µm UMC FPGA reliability data, Table 45: CMOS Reliability – High
Temperature Operating Life (HTOL): Added HTOL data, FIT improved from 1.26 to 1.25.
34
Updated 0.22 µm UMC FPGA reliability data, Table 53: High Temperature Operating Life
(HTOL): Added HTOL data, FIT improved from 18.59 to 15.85.
45
Updated 0.15 µm FPGA reliability data, FIT improved from 10.47 to 7.58.
Table 59: High Temperature Operating Life (HTOL): Added RTAX-S HTOL data.
Table 60: Low Temperature Operating Life (LTOL): Added RTAX-S LTOL data.
47, 53
Updated 0.13 µm Infineon Flash FPGA (ProASIC3 – A3P) reliability data, Table 64: High
Temperature Operating Life (HTOL) After 550 Program/Erase Cycles: Added ProASIC3
HTOL data. FIT improved from 4.40 to 4.18.
56
Updated 0.13 µm Infineon Flash FPGA (Fusion – AFS) reliability data, Table 72: High
Temperature Operating Life (HTOL) after 550 Program/Erase Cycles: Added AFS HTOL
data, FIT improved from 6.61 to 6.51.
63
Added 0.13 µm Infineon Flash FPGA (SmartFusion – A2F) reliability data. Added the
following tables:
Table 81: High Temperature Operating Life (HTOL) after 550 Program/Erase Cycles
Table 82: High Temperature Storage (HTS), 150°C
Table 84: Endurance (eNVM)
Table 85: Retention (eNVM) after 1100 Program/Erase Cycles
Table 86: Low Temperature Retention and Read Disturb (eNVM) at 25° after 1100 Program/
Erase Cycles, 25°C
90
66 – 67
SoC Reliability Report
Revision 8,
May 2010,
51000001-8/5.10
(continued)
Updated 0.13 µm UMC Flash FPGA Reliability Data (IGLOO – AGL/AGLE; IGLOO PLUS –
AGLP; IGLOO nano - AGLN)
•
•
•
•
•
Table 87: Added HTOL data, FIT improved from 10.94 to 7.70
Table 89: Added TC Data
Table 91: Added HTS Data
Table 92: Added Endurance Data
Table 93: Added Retention Data
68 – 71
Updated 0.13 µm UMC Flash FPGA reliability data (ProASIC3, ProASIC3E – A3P, A3PE;
ProASIC3L, ProASIC3/EL – A3PL, AEPEL; ProASIC3 nano – A3PN)
•
•
Table 94: Added HTOL Data, one failure reported at 3000 hrs of HTOL operation at
Tj 135.24C, which is equivalent to 44 years of operation at 55C. Footnote added
Table 98: Added HTS Data
Updated Table 1: Reliability Summary: FIT Rate by Device Technology: FIT rates for
Revision 7,
following Device Technology have been updated:
March 2009,
51000001-13/12.15
• 0.45 µm CMOS FPGA
• 0.15 µm UMC CMOS FPGA
• 0.13 µm Infineon Flash CMOS FPGA
• 0.13 µm UMC Flash CMOS FPGA
Updated Table 2: Reliability Summary: FIT Rate by Device Technology and Product Family:
FIT rates for following Device Technology have been updated:
•
•
•
•
•
•
4
5
0.45 µm CMOS FPGA
0.15 µm UMC CMOS FPGA (RTAX-S)
0.13 µm Infineon Flash CMOS FPGA (ProASIC3 – A3P)
0.13 µm Infineon Flash CMOS FPGA (Fusion - AFS)
0.13 µm UMC Flash CMOS FPGA (IGLOO – AGL)
0.13 µm UMC Flash CMOS FPGA (ProASIC3 – A3P)
Updated Table 3: Summary of ESD Performance for All Product Families (TM 3015/
JESD22-A114):
•
•
72, 73
7
Updated ESD data for A3P, AFS, A3PL, and AGL
Added ESD data for AGLP and RTAX4000S
Added Table 4: Summary of ESD Performance for AEC-Q100 Qualified Product Families
(AEC-Q100-002); new table.
8
Updated 0.45 µm (MX) FPGA Reliability Data, Table 23: High Temperature Operating Life
(HTOL), Table 25: Unbiased Humidity, and Table 26: Temperature Cycle.
25 – 26
•
•
•
Updated HTOL table 22: A42MX36-CQ208, 1/77units failed at 168 hrs, total 1000
hrs @ 125ºC
Updated Un biased HAST table 24: A42MX24-PQG208, 47 units, 100 hrs
Updated TC table 25: A42MX24-PQG208, 47 units, 1000 cycles
Updated "Antifuse FIT Rate Calculator" section.
•
•
Updated 0.22 µm (SXA) UMC FPGA Reliability Data Table 51: Biased Humidity (HAST) and
Table 52: Temperature Cycle.
•
•
SoC Reliability Report
46
Updated TC table 52: APA1000-PQG208, 46 units, 1000 cycles
Updated 0.15 µm UMC CMOS FPGA (RTAX-S) Reliability Data, Table 59: High
Temperature Operating Life (HTOL).
•
43, 44
Updated Un biased HAST table 45: A54SX72A-PQG208, 47 units, 100 hrs
Updated TC table 46: A54SX72A-PQG208, 46 units, 1000 cycles
Updated 0.22 µm Flash (APA) FPGA Reliability Data in Table 58: Temperature Cycle.
•
38
Updated Antifuse FIT from 23 to 17
Updated the version of calculator
47
Updated and added additional 1494138 Unit Hrs of RTAX-S data, 1 SRAM failure at
1000 hrs
91
Revision 7,
March 2009,
51000001-13/12.15
(continued)
Updated 0.13 µm Infineon Flash FPGA (ProASIC3 – A3P) Reliability Data, Table 64: High
Temperature Operating Life (HTOL) After 550 Program/Erase Cycles, Table 66:
Temperature Cycle (TC), –55°C to +125°C, Table 67: Biased Humidity Accelerated Stress
Test (HAST), 110°C / 85% RH, and Table 69: Temperature Humidity Bias (THB), 85°C / 85%
RH:
•
•
•
•
Updated HTOL table 57: A3P1000-FGG484, 231 units, 1000 hrs @ 134ºC (total
2008 hrs)
Updated TC table 59: A3PE1500-PQG208, 48 units, 1000 cycles
Updated Biased HAST table 60: A3PE1500-PQG208, 47units, 100 hrs
Updated THB table 62:
– A3P1000- PQG208, 22units, 2000 hrs
– A3P1000- PQG208, 22units, 2000 hrs
– A3P1000- FGG256, 22units, 2000 hrs
– A3P250- FGG256, 22units, 2000 hrs
Updated "0.13 µm Infineon Flash FPGA Reliability Summary (Fusion – AFS)" section, Table
72: High Temperature Operating Life (HTOL) after 550 Program/Erase Cycles through
Table 80: Retention (eNVM) at 250°C after 1000 Program/Erase Cycles.
•
•
•
•
•
•
•
•
•
•
Revision 6,
June 2008,
51000001-6/6.08
92
4
Updated 0.13 µm Infineon Flash CMOS FPGA
Added 0.13 µm UMC Flash CMOS FPGA
Updated Table 2: FIT rates for following Device Technology have been updated/added:
•
•
•
•
72
A3PE3000-FGG484, 129 units, additional 1000 hrs @ 135ºC (total 2000 hrs)
Updated Table 1: FIT rates for following Device Technology have been updated/added:
•
•
68 – 70
Updated HTOL table 74:
– AGLE3000-FGG484, 45 units, 1000 hrs @ 130ºC
– AGL1000-FGG484, 129 units, 1000 hrs @ 132ºC
– AGLP125-VQ100, 129 units, 1000 hrs @ 128ºC
Updated LTOL table 75: Corrected typo for total number of units
Updated TC table 76:
– AGL600-FG256, 80 units, 1000 cycles
– AGLP125-VQ100, 129 units, 1000 cycles
Updated HTS table 78: AGLP125-VQ100, 129 units, 1000 cycles
Added to "0.13 µm UMC Flash FPGA Reliability Summary (ProASIC3, ProASIC3E – A3P,
A3PE; ProASIC3L, ProASIC3EL – A3PL, A3PEL; ProASIC3 nano – A3PN, RT ProASIC3 –
RT3P)" section, Table 94: High Temperature Operating Life (HTOL) after 550 Program/
Erase Cycles:
•
63 – 65
Updated HTOL table 65:
– AFS1500-FGG256/FG256, 110 units, 1000 hrs @ 135ºC
– AFS600-FG256, 68 units, additional 2200 hrs @ 141ºC (total 3200 hrs)
Updated LTOL table 66: AFS1500-FGG256, 68 units, 1000 hrs @ –55ºC
Updated TC table 67: AFS1500-FGG256, 48 units, 1000 cycles
Updated HTS table 68: AFS1500-FGG256, 50 units, 1000 cycles
Updated HAST table 69: AFS1500-FGG256, 69 units, 264 hrs
Updated Endurance NVM table 70: AFS1500-FGG256/FG256, 77 units, 550 cycles
Updated Retention table 72: AFS1500-CQ208, 77 units, 168 hrs
Updated "0.13 µm UMC Flash FPGA Reliability Summary (IGLOO – AGL/AGLE; IGLOO
PLUS – AGLP; IGLOO nano – AGLN)" section, Table 87: High Temperature Operating Life
(HTOL) after 550 Program/Erase Cycles, Table 88: Low Temperature Operating Life (LTOL)
at –55°C after 550 Program/Erase Cycles, Table 89: Temperature Cycle (TC), –55°C to
+125°C, and Table 91: High Temperature Storage (HTS), 150°C.
•
56 – 60
5
Updated 0.13 µm Infineon Flash CMOS FPGA (ProASIC3 – A3P)
Added 0.13 µm Infineon Flash CMOS FPGA (Fusion – AFS)
Added 0.13 µm UMC Flash CMOS FPGA (IGLOO – AGL)
Added 0.13 µm UMC Flash CMOS FPGA (ProASIC3 – A3P)
SoC Reliability Report
Revision 6,
June 2008,
51000001-6/6.08
(continued)
Updated Table 3: ESD Performance
•
•
•
7
Format ESD data reported for eX, SX-A, RTSX-S and RTSX-SU
Updated ESD data for A3P
Added ESD data for AFS and AGL
Updated entire "0.13 µm Infineon Flash FPGA Reliability Summary (ProASIC3 – A3P)"
section, Table 64 to Table 71:
56 – 62
Formatted all table headers added more information (test conditions, etc.)
Updated Table 64: High Temperature Operating Life (HTOL) After 550 Program/Erase
Cycles:
• A3P125- FGG144, 82 units, 1000 hrs @ 130°C
• A3P1000-FGG484, 231 units, 1008 hrs @ 134°C
• A3P1000-FGG484, 2427 units, 48 hrs @ 134°C
• A3PE1500-FGG484, 77 units, 1000 hrs @ 134°C
Updated Table 65: Low Temperature Operating Life (LTOL) at –55°C after 550 Program/
Erase Cycles: A3PE1500-FGG484, 77 units, 1000 hrs @ –55°C
Updated Table 66: Temperature Cycle (TC), –55°C to +125°C:
• A3P1000-FGG484, 231 units, 1000 cycles
• A3PE1500-FGG484, 77 units, 1000 cycles
Updated Table 67: Biased Humidity Accelerated Stress Test (HAST), 110°C / 85% RH:
• A3P1000-FGG484, 231 units, 96 hrs
• A3PE1500-FGG484, 77 units, 264 hrs
Added new data and tables for Table 68: High Temperature Storage (HTS), 150°C and
Table 69: Temperature Humidity Bias (THB), 85°C / 85% RH.
Updated Table 70: Endurance (Room Temperature):
• A3P1000-FGG484, 231 units, 550 cycles
• A3PE1500-FGG484, 77 units, 550 cycles
Updated Table 71: Retention at 250°C after 550 Program/Erase Cycles:
•
•
•
Revision 5,
April 2007,
51000001-5/4.07
A3P1000-CQ208, 231 units, 1008 hrs @ 150°C
A3P1000-CQ208, 149 units, 3000 hrs @ 250°C
A3PE1500-CQ208, 77 units, 1000hrs @ 250°C
Added the "0.13 µm Infineon Flash FPGA Reliability Summary (Fusion – AFS)" section,
Table 72 to Table 80.
63 – 65
Added the "0.13 µm UMC Flash FPGA Reliability Summary (IGLOO – AGL/AGLE; IGLOO
PLUS – AGLP; IGLOO nano – AGLN)" section, Table 87 to Table 93.
68 – 71
Added the "0.13 µm UMC Flash FPGA Reliability Summary (ProASIC3, ProASIC3E – A3P,
A3PE; ProASIC3L, ProASIC3EL – A3PL, A3PEL; ProASIC3 nano – A3PN, RT ProASIC3 –
RT3P)" section, Table 94 to Table 98.
72 – 73
ORT Report updates are not done quarterly, usually updated twice a year or by request
from Actel Technical Review Board (TRB). Labels referencing quarter/year are being
replaced with a revision number. This version of the ORT report is Rev 4.
Updated Table 1: FIT rates for following Device Technology have been updated
•
•
•
•
4
0.25 µm UMC CMOS FPGA
0.22 µm UMC Flash CMOS FPGA
0.15 µm UMC CMOS FPGA
0.13 µm Infineon Flash CMOS FPGA
Updated Table 2: FIT rates for following Device Technology have been updated
SoC Reliability Report
N/A
•
0.25 µm UMC CMOS FPGA
•
•
•
•
0.22 µm UMC Flash CMOS FPGA
(ProASICPLUS)
0.15 µm UMC CMOS FPGA
(Axcelerator)
0.15 µm UMC CMOS FPGA
(RTAX-S)
0.13 µm Infineon Flash CMOS FPGA (ProASIC3)
5
(RTSX-SU)
93
Revision 5,
April 2007,
51000001-5/4.07
(continued)
34
Updated Table 45: 0.25 µm UMC RTSX-SU HTOL data
•
•
•
Updated test time (added 250 hrs) for RTSX32SU, CQFP208, W/L D1JW21 and
D1AYJ1, DC 0519 and 0502: 150 units, Test Time = 750, Unit Hrs = 112500
Added new data: RTSX32SU, CQFP208, W/L D1JW21 and D1AYJ1, DC 0519 and
0502, 150 units, Test Time = 750, Unit Hrs = 112500
Updated the TOTAL Units for 0.25 µm FPGA to 4744 and Total Test Time Hours =
9299758
37
Updated Table 46: 0.25 µm UMC RTSX-SU LTOL data
•
•
•
Updated test time (added 500 hrs) for RTSX32SU, CQFP208, W/L D1JW21 and
D1AYJ1, DC 0519 and 0502: 150 units, Test Time = 1000, Unit Hrs = 150000
Added new data: RTSX32SU, CQFP208, W/L D1JW21 and D1AYJ1, DC 0519 and
0502, 150 units, Test Time = 500, Unit Hrs = 75000
Updated the TOTAL Units for 0.25 µm FPGA to 1376 and TOTAL Test Time Hours
to 1767244
43
Updated Table 51: 0.22 µm UMC SX-A Biased Humidity (HAST) data
•
•
Added new data: A54SX32A, PBGA329, W/L D26E61, DC 0610, 45 units, Test
Time = 528, Unit Hrs = 23760
Updated the TOTAL Units for 0.22 µm FPGA to 195 and TOTAL Test Time Hours to
38760
Updated Table 52: 0.22 µm UMC SX-A Temperature Cycle data
•
•
•
44
Added new data: A54SX32A, PBGA329, W/L D26E61, DC 0610, 22units, Test
Cycles = 1000, Unit Cycles = 22000
Updated the TOTAL Units for 0.22 µm FPGA to 577 and Total Test Cycles to 539000
Removed the generic (-65ºC - +150ºC) row and added footnotes for (-65ºC +150ºC) and (-55ºC - +125ºC) for each line in the table
Updated Table 53: 0.22 µm UMC Flash APA HTOL data
•
•
94
45
Updated test time (added 500hrs) for APA1000, CQFP352, W/L MK3KA, DC 0517,
132 units, Test Time = 1115 Unit Hrs = 147180
Updated the Total Test Time Hours = 631548
SoC Reliability Report
Revision 5,
April 2007,
51000001-5/4.07
(continued)
Updated Table 56 and Table 57: 0.22 µm UMC Flash APA Retention Programmed and
Erased
•
The W/L numbers for APA1000, CGA391, 73 units was incorrectly stated as
ZA026941, corrected to MAE49, MC147, MC148.
Updated Table 59: 0.15 µm UMC Axcelerator and RTAX-S HTOL data
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
56
Changed the table format to report TJ and Test Time during HTOL testing and Test
Time at TJ 125ºC
Added new data: A3P060, FPGA256, W/L ZA612052, DC 0626, 129 units, Test
Time @ 133ºC = 1000, Unit Hrs @ 125ºC = 192855
Added new data: A3P250, FPGA256, W/L ZA628252.05, DC 0628, 77 units, Test
Time @ 133ºC = 1000, Unit Hrs @ 125ºC = 115115
Added new data: A3P400, FPGA256, ZA614042, DC 0637, 77units, Test Time @
133ºC = 1000, Unit Hrs @ 125ºC = 115115
Updated Table 70 and Table 71: Removed text “Room Temperature” as these are run at
250ºC
SoC Reliability Report
53
Added new data: RTAX2000S, CQFP352, W/L D1KHN1, 78 units, Test Time = 168,
Unit Hrs = 13104
Updated the TOTAL Units for 0.15 µm FPGA = 992 and Total Test Time Hours =
481604
Updated the TOTAL Units for 0.13 µm FPGA = 633 and Total Test Time Hours =
1531494
Updated Table 64: 0.13 µm IFX A3P HTOL data
•
47
Updated test time (added 1000 hrs@132ºC) for RTAX1000S, CGA624, W/L
D1GAH1, DC 0444, 120 units, Test Time @ 132ºC = 6000, Unit Hrs @ 125ºC =
1024560
Updated test time (added 832 hrs @132ºC) for RTAX1000S, CGA624, W/L
D1KH51, 37 units, Test Time @ 132ºC = 1000, Unit Hrs @125ºC = 52651
Updated test time (added 832 hrs @ 132ºC) for RTAX1000S, CQFP352, W/L
D1KH51, 8units, Test Time @ 132ºC = 1000, Unit Hrs @125ºC = 11384
Added new data: AX2000, FPGA896, W/L D2A5A1, DC 0620, 77 units, Test Time =
1000 @ 125ºC, Unit Hrs @ 125ºC = 77000
Added new data: RTAX1000S, CGA624, W/L D1KH51, 24 units, Test Time @
132ºC = 168, Unit Hrs @125°C = 5736
Added new data: RTAX2000S, CQFP352, W/L D1NSG1, 14 units, Test Time @
132ºC = 168, Unit Hrs @ 125ºC = 3346
Added new data: RTAX250S, CQFP208, W/L D1H381, 6 units, Test Time @ 125ºC
= 1000, Unit Hrs @ 125ºC = 6000
Added new data: RTAX2000S, CQFP352, W/L D1KHN1, 78 units, Test Time @
125ºC = 1000, Unit Hrs @125ºC = 78000
Added new data: RTAX1000S, CQFP352, W/L D1NR91, 24 units, Test Time @
132ºC = 168, Unit Hrs @ 125ºC = 5736
Added new data: RTAX2000S, CQFP352, W/L D1KHN1, 14 units, Test Time @
132ºC = 168, Unit Hrs @ 125ºC = 3346
Added new data: RTAX2000S, CQFP352, W/L D21PH1, 6 units, Test Time @
125ºC = 168, Units Hrs @ 125ºC = 1008
Updated the TOTAL Units for 0.15 µm FPGA to 1397 and Total Test Cycles =
2310665
Updated Table 60: 0.15 µm UMC Axcelerator and RTAX-S LTOL data
•
46
62
95
Q2 CY2006,
August 2006,
51000001-4/8.06
Added tables Table 64 through Table 71 for 0.13 µm IFX CMOS FPGA (ProASIC3).
56–62
Updated Table Table 59 and Table 60.
47, 53
•
•
Added AX2000-FPGA896, W/L D16T91, DC0431 to Table 59.
Added RTAX-S Data to Table 59 and Table 60.
45
Updated Table 53.
•
Added APA1000-CQ256, W/L MK3K1, DC 0517, 132 units, Test Time = 615, Unit
Hrs = 81180.
34
Updated Table 45, 0.25 µm UMC RTSX-SU HTOL data.
Updated RTSX72SU, CQFP208, W/L D1AYH1 and D1KT11, DC 0519 and 0445:
• 73 units, Test Time = 31,237, Unit Hrs = 2280268
• 5 units, Test Time = 20,824, Unit Hrs = 104122
Added RTSX32SU, CQFP208, W/L D1JW21 and D1AYJ1, DC 0519 and 0502: 150units,
Test Time = 500, Unit Hrs = 75000.
Added RTSX72SU, CQFP256, W/L D1N2W1, 77units, Test Time = 1000, Unit Hrs = 7000.
37
Updated Table 46, 0.25 µm UMC RTSX-SU LTOL data.
Added RTSX32SU, CQFP208, W/L D1JW21and D1AYJ1, DC 0519 and 0502: 150 units,
Test Time = 500, Units Hrs = 75000.
Updated RTSX32SU, CQFP208, W/L D122H1 and D1JW21, DC 0434 and 0442:
• 152 units, Test Time = 5000, Unit Hrs = 760000
• 2 units, Test Time = 4000, Unit Hrs = 8000
Updated RTSX32SU, CQFP208, W/L D1AYH1 and D1KT11, DC 0445 and 0519:
•
75 units, Test Time = 6000, Unit Hrs = 450000.
Updated Table 3 ESD Performance for RTAX-S and ProASIC3.
7
Updated Table 2.
5
•
•
•
•
Updated 0.25 µm UMC CMOS FPGA (RTSX-SU) data
Updated 0.15 µm UMC CMOS FPGA (Axcelerator) data
Added 0.15 µm UMC CMOS FPGA (RTAX) data
Added 0.13 µm IFX CMOS FPGA (ProASIC3) data
Updated Table 1.
•
•
•
Q1 CY2006,
May 2006,
51000001-3/5.06
Note relating to UMC 0.25 µm RTSX-SU antifuse FIT rates added to Table 1.
4
XL and DX devices in 0.8 µm CMOS FPGA were removed from Table 2 and Table 14.
5, 18
Removed “Table 9. Thermal Shock." Table had header only; no data.
N/A
Revised entire section "0.25 µm UMC FPGA Reliability Summary" and added new data
from UMC 0.25 µm RTSX-SU antifuse reliability testing.
34
Revised entire section "0.22 µm UMC FPGA Reliability Summary " and added new data
from UMC 0.22 µm A54SX72A antifuse reliability testing.
40
Started including the Date Codes for the packages used in the reliability studies.
N/A
New ORT data has been added, 0.22 µm Flash FPGA (Table 51).
43
0.22/0.25 µm CMOS FPGA results have been updated with new test results.
96
4
Updated 0.25 µm UMC CMOS FPGA data
Updated 0.15 µm UMC CMOS FPGA data
Added 0.13 µm IFX CMOS FPGA data
30–45
SoC Reliability Report
Q2 CY2005,
August 2005,
51000001-1/8.05
Product 1010A was removed from 1.0 µm FPGA, ACT1 Family.
8
All the earlier devices manufactured by TI were removed from 1.0 µm FPGA, ACT1, and
ACT2 Families.
8
Industry standard nomenclature was used for the package names
N/A
All the FIT rates were checked and corrected as necessary
N/A
The "Group E Inspection—Generic Data (Radiation Hardness)" section has been added.
ESD performance data has been removed.
9
N/A
For more information, visit our website at www.microsemi.com/soc.
SoC Reliability Report
97
98
SoC Reliability Report
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