AN-198: PD69104B Based Design of a 4-port Auto Mode System (IEEE802.3af/802.3at Compliant)

C
TM
O N F I D E N T I A L
PD69104B Based Design of a 4-port Auto Mode
System (IEEE802.3af/802.3at Compliant)
APPLICATION N OTE
Introduction _________________
This document allows circuitry designers to integrate PoE
capabilities, as specified in the IEEE802.3af and
IEEE802.3at standards, into an Ethernet switch.
PD69104B, 4 port PoE manager implements real time
functions as specified in IEEE 802.3af and IEEE802.3at
standards. These include detection, classification and
port-status monitoring. Furthermore it implements system
level activities such as power management and MIB
(Management Information Base) support for system
management. The PoE manager is designed to detect
and disable disconnected PDs (Powered Devices), using
DC disconnection method, as specified in the standard.
Applicable Documents




IEEE 802.3af-2003 standard, DTE Power via MDI
IEEE802.3at-2009 standard, DTE Power via MDI
PD69104B datasheet, catalogue number
DS_PD69104B
PD69104B Reg Map User guide, catalogue number
PD69104B-HP_UG_Reg_Map
Background
PD69104B operates in Auto mode, managed by using a
2
Host Control or by using an E PROM that configures the
system when it turns on.
This application note defines:
2
 Communication with the Host Controller via an I C
bus
 PD69104B configuration

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IEEE 802.3af-2003 compliant
IEEE802.3at-2009 compliant, including two-event
classification
Configurable AT/AF modes
Single DC voltage input (44-57V)
Supports pre-standard PD detection
Supports Cisco devices detection
Low power dissipation (0.36Ω sense resistor and
0.3Ω internal MOSFET RDS_ON)
Internal power on reset
Includes Reset command pin
4 direct address configuration pins
Continuous port monitoring and system data
Configurable load current setting
Configurable standard and legacy detection mode
Power soft start mechanism
On-chip thermal protection
Voltage monitoring/protection
Built in 3.3V and 5V regulators
Low internal MOSFET RDS_ON of 0.3Ω
Emergency power management supporting four
configurable power bank I/Os
Can be cascaded to up to 12 PoE devices (48 ports)
LED Support for every port
Auto mode for standalone systems
MAX_LED for indicating max power budget
2
I C or UART communication
Power Management
2
E PROM support
Wide temperature range: -10°C to +85°C
RoHS compliant
4 Pairs support
W W W. Microsemi .CO M
This application note provides detailed information and
circuitry design guidelines for the implementation of a 4port Power over Ethernet Technology consortium system,
based on Microsemi’s™ 4-channel PoE manager;
2
PD69104B An I C or UART interface is available for
communication with a hosting system.
Features ___________________
Integration__________________
The system can work with up to 48-port switch. Same
design can be applied to 1 to 12 PoE managers
controlling 4 ports each (from 4 to 48 ports in multiplies
of 4).
Copyright © 2012
Microsemi
Rev. 1.4 / 30-Jan-12
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
1
AN-198
PoE-system daughter board can be easily integrated on
top of a switch and thereby provides the capability to
add any PoE application while using a different
daughter application.
C
O N F I D E N T I A L
PD69104B Based Design of a 4-port Auto Mode
System (IEEE802.3af/802.3at Compliant)
TM
APPLICATION N OTE
System Configuration_________
An Automode system with PD69104B
configured through one of 3 options:
be
2
Host I C communication
2
E PROM configuration
Hardware configuration (see Figure 1)
Overall Description___________
Circuit includes the following blocks:
1. PD69104B 4 Ports Auto Mode Circuit.
See Figure 1.
2
2. An Isolation Circuit for I C bus. See Figure 2.
2
2
3. An E PROM to configure PD69104B by I C
communication. See Figure 1.
General Circuit Description____
A 4-port configuration for a PoE Automode system,
shown in Figure 1, comprises 1 PoE manager circuit
(PD69104B) that functions as slaves to a Host
2
controller. Host controller utilizes the I C bus to control
PD69104B. “Extended Registers Support” operations
are performed automatically by PoE manager circuits,
while the PoE Host controller performs power
management and other tasks.
Communication Flow
2
Host CPU issues commands, utilizing a dedicated I C
Communication Protocol to PD69104B through an
isolation component.
This isolation is a basic requirement of IEEE802.3 PoE
standards.
Isolation
Used isolation circuitry comprises opto-coupler and
digital isolator destined to provide 1500Vrms isolation
required by standards (IEEE802.3af/IEEE802.3at) See
Figure 2.
Following are Isolation signals that cross over the
isolation circuitry:
I C (SDA,SCL)
Reset (xPoE_RESET)
Interrupt (nINT See Figure 3)
Isolation voltage parameters from host side:
 VIH > 1.6V
 VIL < 0.4V
 VOH > 3V
 VOL < 0.2V
Grounds
Several grounds are utilized in the system:
 Analog
 Digital
 Chassis
 Floating
Digital and analog grounds are electrically same
ground. However, to reduce noise coupling, grounds
are physically separated and connected only at a single
point U3 @ Figure 1.
Chassis ground is connected to switch’s chassis
ground. This ground plane should be 1500Vrms isolated
from PoE circuitry.
Floating ground is actually controller’s digital ground.
3.3V Regulator
The PD69104B comprises a built in regulator used for
the PD69104B internal circuitry and PoE domain side
isolation circuit. The host (switch domain) should
provide 3.3V/5mA (2.7V ≤ VDD1 ≤ 3.6) to the host
domain side of the isolation circuit.
Detailed Circuit Description____
The following sections describe the overall block
diagram of a PD69104B (refer to Figure 1).
Communication Interfaces
Interface between Ethernet switch and PoE ICs is a
2
1500Vrms isolation I C interface. Note that each side of
the circuitry is fed by a separate power supply. Isolation
circuit is detailed in Figure 2 .
Control and Indication Signals
Control/Indication signals are of single H/W lines type
that runs between Host controller and PoE manager.
These signals are isolated to achieve 1500Vrms isolation
(Refer to Figure 2 & Figure 3).

nINT: When this pin is configured to work as an
interrupt pin, a signal generating by the PoE
manager indicates events such as Port On,
Port
Off,
Port
Fault,
PoE
Manager
Fault,
Voltage
Out
of
Range,
etc.
nINT pin output voltage shall be >3V with a 10KΩ
external pull-up resistor to 3.3V. If not utilizing as
Copyright © 2012
Microsemi
Rev. 1.4 / 30-Jan-12
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
2
AN-198



2
PoE system operates within a supply range of 44V to
57V (802.3at high power port's supply range is 50 to
57V). To comply with UL SELV regulations, maximum
output voltage should not exceed 60V. System Power
supply should supply power for 4 ports.
Each port can consume up to 40W, 720mA depending
on the current set (see Table 4 line 33)
W W W. Microsemi .CO M



can
Main Supply
C
PD69104B Based Design of a 4-port Auto Mode
System (IEEE802.3af/802.3at Compliant)
TM

O N F I D E N T I A L
Reference Current Source
Reference for internal voltages within the PoE manager
is set by a precision resistor of 30.1KΩ (R15). See
Figure 1.
I2C Interface
Host controller can communicate with PoE managers
2
using I C communication.
2
I C communication between Host CPU and PD69104B
is managed by setting the address of the ICs. This is
done by selecting add0-add3 pins which can be
connect to 3.3V or GND.
2
These pins set I C address as shown in Figure 1.
2
APPLICATION N OTE
dedicated I C lines (pins 42 43) as shown in Figure 1. In
multi PoE managers system each one should have its
2
own E PROM.
2
(Note for EVB - When E PROM is needed to be
programmed, R6 and R7 should be removed in order to
allow the programmer to communicate with the
2
E PROM and not to the PoE manager).
LED indication


When PD69104B turns one of its ports on, the LED
of this port is activated (pins 7,8,29,30).
MAX_LED
analog
output
indication
that
consumption is below Power Guard Band
determined by the user
Output Protection
W W W. Microsemi .CO M
nINt, the pin functions as a CAP or RES detection
configuration pin as explained in Table 4 line 36
xPoE_RESET signal generate by the Host, resets all
PoE managers throw an isolation reset line See
Figure 2. All PoE managers reset input lines should
be connected together with a pull-up resistor.
F1-F4 is a current limiting device, operating as specified
in the IEC 60950-1:2001 requirements.
The fuse is not required in case power supply is lower
than 100W.
Ground Interface Connection (AGND)
Power Supplies Ground connector enables the current
path back to power supply.
Ground connection should be capable of carrying all
strings current back to power supplies.
Thermal Design
Design for IEEE802.3at PoE standard should take into
account power dissipation of PoE manager, associated
circuitry and maximum ambient operating temperature
of the switch. Adequate ventilation and airflow should
be part of the design so as to avoid thermal over-stress
on components detailed below.
Ambient Temperature
Application's thermal design should take into account
temperature derived by the power dissipation of the
switch and by PoE daughter board when powered at
maximum load.
4 Pairs
PD69104B can be configured to work in a 4-pairs
mode, which means ports 1&2 or ports 3&4 are
synchronized to be turned on together when PD 4 pairs
is connected.
In order to work in a 4 pairs mode, pin 32 (4_pairs)
should be connected to VCC or open as explained in
Table 4 row 32.
The second port of each pair is the master and the first
one in the slave, (port 1 and 3 are masters, port 0 and 2
are slaves)
When working in mode half IC 4 pair and half is 2 pairs
,the first 2 ports are working as 4 pairs (port0 & port1)
and ports 2&3 working as normal 2 pair ports.
Current set
E2PROM
AN-198
When a port is in Auto mode, ICUT and ILIM shall be
set automatically after port powers up successfully.
Levels for ICUT and ILIM shall depend on:
 Chip hardware configured in pin 33
2
 E PROM configured by communication
 Host CPU configuration by communication
See Current set description for full parameters (Table 4
line 33).
2
When PD69104B is configured to work with E PROM,
2
pin 34 (COMM_MODE) should be open. E PROM (U1
at Figure 1) communicates with PoE manager by
Copyright © 2012
Microsemi
Rev. 1.4 / 30-Jan-12
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
3
C
O N F I D E N T I A L
PD69104B Based Design of a 4-port Auto Mode
System (IEEE802.3af/802.3at Compliant)
TM
APPLICATION N OTE
Table 1: LED Indication
LED<3:0>
MAX_LED
Status
Port Power On
Power Management
event
Port Over Load
Port Short Circuit
Port failed at Startup
Vmain Out of Range
or Over Temp
Port Off
4 Pairs on
4 Pairs off
Total power consumption
is below Power Guard
Band determined by the
user
Total power consumption
is above Power Guard
Band but below total
budget.
Total power consumption
is above total budget, or
Power Integral is still
positive
LED
W W W. Microsemi .CO M
PIN
On
0.4Hz Blink
0.8Hz Blink
All LEDs :3.3Hz
Blink
Off
2 Leds On
2 Leds Bilnks
Off
On
Blink
AN-198
Copyright © 2012
Microsemi
Rev. 1.4 / 30-Jan-12
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
4
C
O N F I D E N T I A L
PD69104B Based Design of a 4-port Auto Mode
System (IEEE802.3af/802.3at Compliant)
TM
APPLICATION N OTE
Bill of Materials for PoE System
Block
QTY
2
C2,C3
1
4
C4
C6,C7,C24,C
25
1
C9
1
C19
C20,C21,C22,
C23
D1,D15,D16,
D17,D18,D19
4
6
Main
Reference
Description
CAP CRM 4.7uF 10V 10%^^X7R 0805
SMT
CAP CRM 47nF 100V 10%++X7R 0805
SMT
CAP CER 0.1uF 10V X7R 10% ^^0402
SMT
CAP CRM 47nF 100V 10%^^X7R 0805
SMT
CAP ALU 22uF 100V 20% 105C 8X10.2
2000Hr
CAP CRM 47nF 100V 10%^^X7R 0805
SMT
LED SuperYelGrn 100-130o 20-40mcd
h=1 0603 SMD
DIO RECOV. REC 400V 1A++SMA
SILICON SMT
PCB Footprint Manufacturer
Manufacturer's Part Number
PD-SMA
Diodes Inc.
S1G
PD-1206
MOL-10P-2R90130-21
SWITCHCRA
FT-RAPC722
AVX
F1206B1R50FW-TR
Molex
90130-2114
Switchcraft
RAPC722-TB13
PD-0402
Vishay
CRCW0402-1002F RT7
PD -0805
Taiyo Yuden
LMK212B7475KG-T
PD-0805
Murata
GRM40X7R473K100
PD-0402
Walsin
0402B104K100CT
PD-0805
D8H10_2F9P
3_2-SMD
Novacap
0805B473K101CTM
Sanyo
100CE22FS
PD-0805
Vishay
VJ0805Y473KXBAT
led-0603-a
Everlight
19-21-SYGCS530E3TR8
4
D2,D3,D4,D5
4
F1,F2,F3,F4
1
JP1
FUSE 1.5A 63V V. FST BLO++1206 SMT
Header Shrouded 2X5pin^^Vertical Voided
Pins Tin
1
4
J1
R1,R9,R12,R
14
CON DC POWER JACK RA^^2.0X6.3 T/H
RES TCK FLM 10K 1% 62.5mW ^^0402
SMT
3
R5,R6,R7
Resistor, 0 Ohm, 5%, 1/16W 0402
PD-0402
ASJ
CR10-000ZK
3
R8,R11,R13
R10,R18,R29,
R30,R31,R32
Resistor, 0 Ohm, 5%, 1/16W 0402
PD-0402
ASJ
CR10-000ZK
RES TK FLM 51.1K 125mW^^1% 0805
RES TCK FLM 30.1K 1% 62.5mW ^0402
SMT
RES TCK FLM 0.360R 1% 0.5W
200PPM^1210 SMT
PD-0805
Yageo
RC0805FR-0751K1L
PD-0402
Panasonic
ERJ2RKF3012X
PD-1210
PD-QFN488x8-1
Rohm
MCR25JZHFLR360
Microsemi
PD69104AILQ
PD-TSSOP8
Atmel
Analog
Devices
AT24C02-10TU-2.7
6
1
4
R15
R25,R26,R27,
R28
1
U3
1
U4
Ori, 4 Ports PSE IC Auto mode
IC MEM E2PROM 2WIRE 2K^^256X8
TSSOP8 SMT
1
U1
IC Dig.Iso
PD- SOW16
W W W. Microsemi .CO M
Table 2: Main Components
AD80273ARWZ RL**
**Special part number for Microsemi PoE application; preferential pricing for Microsemi customers.
AN-198
Copyright © 2012
Microsemi
Rev. 1.4 / 30-Jan-12
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
5
C
PD69104B Based Design of a 4-port Auto Mode
System (IEEE802.3af/802.3at Compliant)
TM
Vmain Connector
h1
22u 100V
X7R
PD-0805
UART
E2PROM
I2C
Vmain
VAUX3P3
R13
0
PD-0402
N.C
2
J1
RAPC722-TB13
SWITCHCRAFT-RAPC722
R10
51.1K
PD-0805
COMM_MODE
0
open
1
1
C4
47n 100V
D1
R5
0
PD-0402
1
AADVARK to E2PROM connector
2
4
6
8
10
1 2
3 4
5 6
7 8
9 10
D
WP
SCL_E2
U4
E2PROM
A0 VCC
A1
WP
A2 SCL
GND SDA
8
7
6
5
AT24C02-10TU-2.7
PD-TSSOP8
R14
10K
PD-0402
1
VAUX3P3
SDA_E2
SCL_E2
48
47
46
45
44
43
42
41
40
39
38
37
C20
47n 100V
X7R
D3
S1G
PD-0805
C9
100V 47n
R9
10K
R12
PD-0402
10K
PD-0402
2
2
Vmain
36
RES_CAP_INT
35
ALT_A/B
34
COMM_MODE
33
Current_set
32
31
AGND
30
LED2
29
LED3
28 R27 0.360 PD-1210
27 VPORT_NEG2
26 R28 0.360 PD-1210
25 VPORT_NEG3
1
RES_CAP/INT_OUT
ALT_A/B
COMM_MODE
CURRENT_SET
4PAIRS
AGND
LED2
LED3
PORTS_SENSE2
VPORT_NEG2
PORTS_SENSE3
VPORT_NEG3
VPORT_NEG1
C21
47n 100V
X7R
D4
S1G
PD-0805
PD-SMA
VPORT_NEG2
1
2
D
1
Vmain
U3B
HS_Pad1
HS_Pad2
HS_Pad3
VPORT_NEG2
F3
PD-1206
50
49
51
C23
47n 100V
X7R
D5
S1G
PD-0805
PD-SMA
VPORT_NEG3
2
PD69104B
1
2
I2C_SDA_in/Rx
I2C_SDA_out/Tx
I2C_SCL
DGND_45
DVDD
E2_SDA
PS_PGD3/E2_SCL
PS_PGD2
PS_PGD1
PS_PGD0
MODE1
MODE0
RESET_N
ADD0
ADD1
ADD2
ADD3
AGND_6
LED0
LED1
PORT_SENSE0
VPORT_NEG0
PORT_SENSE1
VPORT_NEG1
1
2
VPORT_NEG3
F4
PD-1206
PD69104BILQ
PD-QFN48-8x8-1
D19
Vmain
R18
51.1K
PD-0805
X7R
X7R
X7R
X7R
PD-0402 pd-0805 PD-0402 pd-0805
1
2
3
4
Vmain
R8
0
PD-0402
N.C
F2
PD-1206
VAUX3P3
VAUX5
C3
C2
C6
C7
0.1uf10V 4.7uF10V 0.1uf10V 4.7uF 10V
VAUX3P3
COMM_MODE
R11
0
PD-0402
N.C
VPORT_NEG1
ATB_N/REG_EN_N
NC_14
VMAIN
VAUX5
DRV_VAUX5
AGND_18
VAUX3P3_INT
VAUX3P3
QGND
IREF
VZAP
MAX_LED
xPoE_RESET1
2
ADD0
3
ADD1
4
ADD2
5
ADD3
6
AGND
7
LED0
8
LED1
R25 0.360 PD-1210 9
VPORT_NEG0 10
R26 0.360 PD-1210 11
VPORT_NEG1 12
X7R
PD-0805
MOL-10P-2R-90130-21
SDA_E2
U3A
2
E2PROM
JP1
VPORT_NEG0
PD-SMA
13
14
15
16
17
18
19
20
21
R15 30.1K PD-0402 22
VAUX3P3 23
1MAX_LED 24
R7
0
PD-0402
D
X7R
PD-0402
VMAIN
SCL
SDA_in
D
Current_set
C24
0.1uf10V
SDA_in
SDA_out
SCL
1
R1
10K
PD-0402
1
3
5
7
9
2
F1
PD-1206
1
VAUX3P3
R6
0
PD-0402
PD-0805
PD-SMA
VPORT_NEG0
h2
I2C
C22
47n 100V
X7R
D2
S1G
2
C19
+
W W W. Microsemi .CO M
APPLICATION N OTE
Current Set
0
AF
open
600mA
1
720mA
1
Vmain
1
3
2
O N F I D E N T I A L
Vmain
R29 51.1K
R30 51.1K
R31 51.1K
R32 51.1K
PD-0805
PD-0805
PD-0805
PD-0805
2D18
2D17
2D16
2D15
1
1
1
1
LED0
LED1
LED2
LED3
WP
SCL_E2
SDA_E2
C25
0.1uf10V
X7R
PD-0402
U3
D
SHORT
D
Copyright © 2012
Rev. 1.4 / 30-Jan-12
Microsemi
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
LX2304
Figure 1: 4 Ports Auto Mode Circuit
6
C
O N F I D E N T I A L
PD69104B Based Design of a 4-port Auto Mode
System (IEEE802.3af/802.3at Compliant)
TM
APPLICATION N OTE
VAUX3P3
3_3V_MB
N.C
R6
3.32K
PD-0402
N.C
SCL IN
R4
10K
X7R
PD-0402
X7R
PD-0402
U1
1
2
3
4
5
6
7
8
PO_RST
2
3_3V_MB
R10
3.32K
PD-0402
N.C
SDA
C5
0.1uf10V
C4
0.1uf10V
1
3
D1
PD-SOT23
BAT54-GS08E3
VDD1
VDD2
GND1GND2 _15
VIA
VOA
VIB
VOB
VIC
VOC
VOD
VID
CTRL1 CTRL2
GND1_8 GND2
AD80273
PD-SOW16
16
15
14
13
12
11
10
9
VAUX3P3
D
xPoE_RESET
SCL
SDA_in
SDA_out
R21 49.9 PD-0402
R7 49.9 PD-0402
R9 1K PD-0402
C21
1n50V
R8
3.32K
PD-0402
X7R
PD-0402
D
D
2
Figure 2: I C and reset isolation
W W W. Microsemi .CO M
PD-0402
3_3V_MB
3_3V_MB
3_3V_MB
VAUX3P3
R13
499
PD-0402
6
1
5
8
2 RES_CAP_INT
3
PD-SO8
MOC217 R2
U2
4
nINT
VAUX3P3
R14
10K
PD-0402
TP5
1
N.C
7
R12
4.99K
PD-0402
Figure 3: Interrupt Isolation Circuitry
Table 3: MODE of Operation
Mode 1 Mode 0
Pin38 Pin37
0
0
1
1
0
1
1
MSCC
Extended Auto
Mode
Semi Auto
mode
Test mode
Auto mode
Comm. to the IC
Functionality
2
I C or UART
fully autonomous operation
(see COMM_MODE pin) without a host with Extended
Registers Map support
Default: No interrupt
2
I C or UART
(see COMM_MODE pin)
2
I C or UART
(see COMM_MODE pin)
(can be enabled by communication)
Host should manage the ports
fully autonomous operation
without a host controller with
interrupt out support
Remarks
2
I C or UART Protocol to
Host with extended register
map and PM support
2
I C Protocol to Host
AN-198
0
Mode
For internal use only
2
I C Protocol to Host
Copyright © 2012
Microsemi
Rev. 1.4 / 30-Jan-12
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
7
C
O N F I D E N T I A L
PD69104B Based Design of a 4-port Auto Mode
System (IEEE802.3af/802.3at Compliant)
TM
APPLICATION N OTE
Table 4: PD69104B PIN Description
PIN
PIN NAME
PIN TYPE
Gnd
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
RESET_N
ADDR0
ADDR1
ADDR2
ADDR3
AGND
LED0
LED1
PORT_SENSE0
VPORT_NEG0
PORT_SENSE1
VPORT_NEG1
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Power
Analog output
Analog output
Analog Input
Analog I/O
Analog Input
Analog I/O
13.
REG_EN_N
Analog I/O
14.
NC
Analog I/O
15.
VMAIN
Power
16.
VAUX5
Power
17.
DRV_VAUX5
Power
18.
AGND
Power
19.
VAUX3P3_INT
Power
20.
VAUX3P3
Power
21.
22.
23.
QGND
IREF
TRIM
Power
Analog Input
Test Input
24.
MAX_LED
Analog output
25.
26.
27.
28.
29.
30.
VPORT_NEG3
PORT_SENSE3
VPORT_NEG2
PORT_SENSE2
LED3
LED2
Analog I/O
Analog Input
Analog I/O
Analog Input
Analog output
Analog output
Copyright © 2012
Microsemi
Rev. 1.4 / 30-Jan-12
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
AN-198
PAD
W W W. Microsemi .CO M
0.
DESCRIPTION
Exposed PAD: Connect to analog ground.
A decent ground plane should be deployed around this pin whenever
possible (refer to PD69104B Layout Design Guidelines)
Reset input – active low ('0' = reset)
Address bus to set chip address
Address bus to set chip address
Address bus to set chip address
Address bus to set chip address
Analog ground
Port 0 LED indication – Active low ('0' - LED on)
Port 1 LED indication – Active low ('0' - LED on)
Sense resistor port input
Negative port output
Sense resistor port input
Negative port output
An input pin that enables control of the 3.3VDC internal regulator.
Disables internal 3.3VDC regulator in case external 3.3VDC is used to
supply the chip.
If connected to GND – internal regulator is enabled.
If connected to 3.3VDC – internal regulator is disabled
A test pin used only during production.
Keep unconnected.
Main High Voltage Supply voltage. A low ESR 1µF (or higher)
bypass capacitor, connected to AGND should be placed as close
as possible to this pin through low resistance traces.
Regulated 5V output voltage source; needs to be connected to
filtering capacitor (at least 4.7µF).
Driven output terminals for 5VDC external regulations. In case internal
regulation is used, connect to pin 16.
In case an external NPN is used to regulate the voltage, connect this
pin to "Base".
Analog ground
In case internal 3.3 VDC regulator is used, connect to VAX3P3 (pin
20).
In case external 3.3VDC regulator is used, connect to VAUX5 (pin 16).
Regulated 3.3V output voltage source. Connect a 4.7µF capacitor
between this pin and AGND.
Quiet analog ground
Reference resistor pin. Connect a 30.1 KΩ ±1% resistor to QGND
Test Input pin; Connect to Vdd
MAX LED analog output; Indication that consumption is below Power
Guard Band determined by the user
Negative port output
Sense resistor port input
Negative port output
Sense resistor port input
Port 3 LED indication – Active low ('0' - LED on)
Port 2 LED indication – Active low ('0' - LED on)
8
C
O N F I D E N T I A L
PD69104B Based Design of a 4-port Auto Mode
System (IEEE802.3af/802.3at Compliant)
TM
APPLICATION N OTE
PIN NAME
AGND
PIN TYPE
Power
32.
4_Pairs
Analog Input
33.
Current_SET
Analog Input
34.
COMM_MODE
Analog Input
35.
ALT A/B
Digital Input
36.
RES_CAP / INT_OUT Digital I/O
37.
38.
39.
40.
41.
Mode0
Mode1
PS_PGD0
PS_PGD1
PS_PGD2
Digital Input
Digital Input
Digital input
Digital input
Digital input
42.
PS_PGD3 / E2_SCL
Digital I/O
43.
E2 SDL
Digital I/O
44.
45.
46.
47.
48.
DVDD
DGND
I2C SCL
I2C_SDA_out / Tx
I2C_SDA_in / Rx
Power
Power
Digital Input
Digital Output
Digital I/O
DESCRIPTION
Analog ground
3 state input pin. - select 4 pairs mode
• “0” (GND) - 4 ports of 2 pairs
• “open” (N.C) - 2 ports of 2 pair & 1 of 4 pair
• “1” (VCC) - 2 ports of 4 pair.
3 state input pin – select output current and AF/AT mode
• “0” (GND) – AF mode,
• “open” (N.C) – AT 600 mA ,
• “1” (VDD) – High AT Mode 720mA
3 state input pin communication select.
• “0” (GND) – UART active,
2
• “open” (N.C) – E PROM connected
2
• “1” (VDD) – I C active
User input pin to set chip working mode
• “0”: ALT B mode (Midspan, Back Off,)
• “1”: ALT A mode (Endspan / Switch, NO Back off, )
A user input pin to set chip working mode
• “1”: IEEE802.3af compliant resistor detection only
• “0”: AF/AT Detection and Legacy (non-standard) line
detection
When working in extended PoE mode, used as an interrupt out
pin, indicating an interrupt event has occurred
An external 10K pull-up resistor should be connected between this
pin and DVDD.
IC operational mode select – See Table 3
IC operational mode select – See Table 3
Power good 0; Power Budget Set pin – for Fast Power Control
Power good 1; Power Budget Set pin – for Fast Power Control
Power good 2; Power Budget Set pin – for Fast Power Control
PGD3: Power good 3; Power Budget Set pin – for Fast Power Control
Or
2
E2_SCL: I C Clock Out to EPROM
2
2
E PROM I C data I/O pin – for Stand Alone Auto Mode systems Power Up Configuration
Digital 3.3V Power input
Digital GND
2
I C bus, serial clock input
2
I C bus, data output / UART Tx output
2
I C bus, data input / UART Rx input
W W W. Microsemi .CO M
PIN
31.
AN-198
Copyright © 2012
Microsemi
Rev. 1.4 / 30-Jan-12
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
9
C
O N F I D E N T I A L
PD69104B Based Design of a 4-port Auto Mode
System (IEEE802.3af/802.3at Compliant)
TM
APPLICATION N OTE
W W W. Microsemi .CO M
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Revision History
Revision Level / Date
0.1 / 29 Nov 10
Para. Affected
-
Description
Initial Release
Detailed Circuit
Description
Information and a table were added
0.2 / 24 Oct 11
1.0 / 01 Dec 11
1.1 / 04 Dec 11
Structural changes
1.2/ 01 Jan 12
PG pins names were changed
1.3/ 11 Jan 12
Res_cap_int pin description with pull up
1.4/ 30 Jan 12
Adding 4 pairs description
AN-198
© 2012 Microsemi Corp.
All rights reserved.
For support contact: [email protected]
Visit our web site at: www.microsemi.com
Catalog Number: 06-0134-080
Copyright © 2012
Microsemi
Rev. 1.4 / 30-Jan-12
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
10
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