AND9120/D An Introduction to LDO Early Warning Function Abstract In today’s world of high speed, high power processors, new demands have been placed on the power source regulator. One example is the need to inform the processor in advance of an impending drop in supply voltage below a critical value. A common supervisory feature found in automotive LDOs is the Reset signal. When the input voltage is disconnected or lower than minimum operating voltage, the output voltage of regulator will decreases below the reset function threshold and the LDO activates a processor reset output. When an unanticipated Reset signal is received by the processor, important data is often lost because it has no time to save that data. This application note describes in detail the LDO Early Warning feature, which prevents the aforementioned loss of data by monitoring the input voltage and warning the processor in advance of an impending condition where a Reset signal will occur. http://onsemi.com APPLICATION NOTE Introduction Low−dropout (“LDO”) series regulators are often selected to power microprocessor (μP) devices in critical systems. LDO devices designed for these applications typically include a logic−level Reset output to interface with the processor. When the regulator output voltage is within tolerance limits, the Reset output will be high. When the output voltage falls below a preset or user−programmed level, either due to overload or low input voltage, the Reset output is asserted low. Often, assertion of the Reset output is delayed by interposing a timer between the comparator and output. The delay timer provides immunity to transient events that will not pose a threat to the system. Figure 1 depicts the block diagram and operating input−output waveforms of a basic LDO series regulator with Reset function. Despite the control advantages afforded by LDO devices with integrated Reset functions, they may not protect the system against all potential consequences of loss or interruption of the regulator input voltage. If the input voltage drops below the minimum level required to maintain the output in regulation, an unanticipated Reset output state change can occur, which may reset the processor before critical data has been saved and/or benign system conditions established. Figure 2 represents a graphical depiction of this scenario. LDO input voltage, output voltage, and Reset output (RO) are all plotted as a function of time during an input voltage ramp down. As input voltage decays, three distinct operational regions are encountered: © Semiconductor Components Industries, LLC, 2013 February, 2013 − Rev. 0 Figure 1. Basic LDO with Reset Regulation region. Here, the input−output differential voltage ( VIN – VOUT ) exceeds the LDO maximum dropout voltage and Vout is relatively independent of Vin. Pre−dropout region. This region, which begins approximately where the decaying input−output differential voltage crosses the LDO maximum dropout voltage, is characterized by degraded line regulation. Vout may remain within the specified tolerance band, but exhibits a marked VIN dependence. Dropout region. From this point onward, the LDO is in dropout and Vout falls in lockstep with decaying VIN. The LDO output is no longer in regulation and RO is asserted. 1 Publication Order Number: AND9120/D AND9120/D output SO is designed to change state as VIN crosses 5.9 V, and the Reset output (RO) is designed to change state when the regulator output voltage crosses 4.65 V. The consequential Warning time (labeled Twarning) is a direct function of the difference between the SI and Reset thresholds, and an inverse function of the rate of regulator input voltage decay. Figures 4a and 4b depict simplified block diagrams of an LDO regulator product family with integral early warning function, the NCV8667. In both figures, the elements that comprise the early warning function are outlined by a dashed line. The early warning input pin is labeled SI (sense in) and the early warning output logic−level pin is labeled SO (sense out). Figure 2. LDO Reaction to Decaying Input Voltage One practical solution to this problem is the detection of VIN approaching the pre−dropout region, combined with an additional logic path between LDO and processor. This logic output allows the LDO regulator to provide the host processor with early warning of an impending unplanned assertion of the Reset output. (4a) (4b) Figure 4. LDO Devices Incorporating an Early Warning Function Figure 3. Early Warning Implemented by Input Voltage Detection The regulator of Figure 4a includes an internal resistor divider to scale the input sense (SI) threshold, whereas the regulator of Figure 4b does not. With the latter device, an external resistor divider is required to set the threshold. The internal divider resistance of 1 MW can achieve a lower quiescent current contribution than practical values of precision external resistors, and is switched out when the regulator is not enabled, markedly reducing standby current. The processor can then be programmed to implement appropriate countermeasures to prevent loss of data or other undesirable consequential events. LDO regulator devices are now available with an integrated Early Warning VIN monitoring function, typically consisting of a reference, comparator, and logical output driver. Figure 3 describes the operating characteristics of this feature during decay on the regulator input voltage, Vin. For this example, the input voltage sense (early warning) http://onsemi.com 2 AND9120/D New EW resistor divider idea * IDIV is current flowing through external EW resistor divider, Iq is quiescent current of an LDO Consider Adjustable Early Warning Threshold option where is the EW threshold is adjusted by external EW resistor divider as shown in Figure 5. The values for RSI1 and RSI2 are selected for a typical threshold (i.e. 1.25 V) on the SI pin according to eq.1 and eq.2 where Vin_EW(th) is demanded value of input voltage at which Early Warning signal has to be generated. The higher the values of resistors RSI1 and RSI2 are, the lower is current flowing through the resistor divider. Because the divider is put outside the chip more quiescent current flows from the battery. The values of resistors are usually limited to few hundreds of kilohms (i.e. 200 kW or 250 kW). VBAT IBAT IDIV RSI_ext = 150 kW IBAT = Iin = IDIV + Iin_IC* = 50.6 mA Iout Iin Cin The advantage of an internal (on chip) EW resistor divider is that these resistor values can be significantly higher than external resistors and hence, lower quiescent current from batter. In the NCV8667/69 family the total internal EW divider resistance value is 1 MW (i.e. RSI_int1 = 480 kW and RSI_int2 = 520 kW). If Vin_EW_th is required to be set to 5.9 V using NCV8667 with internal EW divider only one external resistor RSI_ext is required: Vin Vout VDD RSI1 * IDIV includes current flowing through EW resistor divider including also RSI_ext current, Iin_IC is quiescent current of the rest of IC @Vin = 13.2 V Cout SI RSI2 Microprocessor LDO RM OFF ON EN SO I/O RO RESET The quiescent current from battery is 30 mA lower when the EW resistors are internal comparded to when they are external. GND Application Shutdown Current Reduction Quiescent current savings become more apparent in shutdown mode. During shutdown, the internal EW resistor divider of the NCV8667 is disconnected from battery via an internal switch. Figure 5. An LDO with External EW Divider ǒ V in_EW(th)_Low + 1.25 1 ) R SI1 + R SI2 ǒ R SI1 R SI2 Ǔ (eq. 1) IBAT = IDIV + IDIS = 52.6 mA + 1 mA = 53.6 mA Ǔ V in_EW(th)_Low *1 1.25 * IDIV is current flowing through external EW resistor divider, IDIS is shutdown current of an LDO (eq. 2) The benefit of internal EW resistor divider is shown in following example. There is an LDO with external EW divider shown in Figure 5 and NCV8667 with internal EW divider shown in Figure 6. VBAT IBAT Iin Vin To rest of IC SI IBAT = IDIV + IDIS = 0 mA + 1 mA = 1 mA Iout Iin_IC Vout IDIV Cin In case of NCV8667 there is no current flowing through the EW resistor divider because it is disconnected from supply by an internal switch and then: * IDIV is current flowing through internal EW resistor divider (~0 mA in shutdown mode), IDIS is shutdown current VDD Cout RSI1_int The difference is 52.6 mA which is significant reduction of battery current in shutdown mode. Microprocessor To Comparator RSI2_int RSI_ext DT OFF ON EN SO I/O RO RESET NCV8667 Setting EW threshold using RSI_ext Preset Early Warning Threshold options can be adjusted externally using RSI_ext resistor connected between input monitor SI and GND as shown in Figure 6. The value for RSI_ext is recommended to be selected in range from 50 kW to 250 kW and the voltage of EW threshold can be set according to Figure 7. The higher the RSI_ext resistance is the lower the overall Quiescent Current of the application (see Figure 8) is. General formulas for calculation of Vin_EW(th)_L and RSI_ext for selected preset Early Warning options are described by eq.3 and eq.4. GND Figure 6. NCV8667 with Internal EW Divider Application Quiescent Current Reduction If Vin_EW_th is required to be set to 5.9 V using an Ultra Low Iq LDO with external EW resistor divider then: RSI1 = 200 kW RSI2 = 51 kW IBAT = IDIV + Iin = 52.6 mA + 28 mA = 80.6 mA http://onsemi.com 3 AND9120/D V in_EW(th)_Low + 1.1 ǒ R SI1 1) Ǔ ǒR SI2 ) R SI_extǓ R SI2 R SI_ext ǒ R SI_ext + 1.1 ) 0.25 R SI1 R SI2 R SI2 V in_EW(th)_Low * 0.25) * 1.1 (eq. 4) (eq. 3) Vin_EW(th)_L vs. RSI_ext @ Present Options (Internal RSI1/RSI2) 11.0 10.5 10.0 9.5 Vin_EW(th)_L (V) 9.0 400/600 kW 480/520 kW 560/440 kW 640/360 kW 720/280 kW 760/240 kW 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 50 100 150 200 250 RSI_ext (kW) − E24 series Figure 7. Input Voltage EW Threshold Low vs. RSI_ext (calculated using E24 series) Iq&RSI_ext vs. RSI_ext @ Present Options (Internal RSI1/RSI2) 60 58 Vin = 13.2 V 56 Iq&RSI_ext (mA) 54 400/600 kW 480/520 kW 560/440 kW 640/360 kW 720/280 kW 760/240 kW 52 50 48 46 44 42 40 50 100 150 200 250 RSI_ext (kW) − E24 series Figure 8. Quiescent Current vs. RSI_ext (calculated using E24 series) http://onsemi.com 4 10 6 Ǔ AND9120/D Twarning Calculation necessary tasks before ressiting. Twarning time can be calculated by eq.5. The EW function can be used for checking minimum supply voltage required for reliable operation of the NCV8667. An on−chip comparator is available to provide the special signal to microprocessor. If the battery is decreasing (e.g. supply connector disconnection) the uP receives the information via SO signal which can be processed by dedicated DI pin of the uP. EW topology is illustrated in Figure 9. VBAT Iin IBAT SI RSI_ext OFF ON Vref Cout + − Microprocessor NCV8667 Iout Vin DT SO EN ǒVin_EW(th)_Low * V1Ǔ.Cin ) ǒ * Cin)Cout RCinCout More details related to Twarning calculation are shown in the Appendix 1. The Twarning time depends on input and output capacitors values, EW threshold value and output load current. For better understanding see simplified schematic in Figure 11. VDD Vout IDIV + ȣ Ǔȧ Ȥ I Cout 1 Iout(RCout*1) RCout Cout Vrt*V1)IoutR* (eq. 5) Iout Vin Cin T warning ȡ ȧ Ȣ Ln LDO Vout I/O RESET RO GND Cin VBAT Cout Load Figure 9. Early Warning Application Circuit Figure 11. Simplified Schematic for Twarning Calculation The early warning function compares a voltage defined by the user to an internal reference voltage (i.e. 1.25 V). Therefore the supervised voltage has to be scaled down by external or internal voltage divider in order to compare it. The timing of EW is shown in Figure 10. Operating Conditions: Vin = 13.2 V VEW_th_l = 5.89 V Vrt = 4.65 V Cin = 4.7 mF Cout = 1 mF Iout = 10 mA Vin Vin_EW(th)_L t Vout VRT Using eq.5 for calculation the Twarning is 890 ms. VRO t VSO t twarning For determination of Twarning also PSpice model of NCV8667[2] can be used. The schematic and simulation results for Twarning can be seen in Figure 12 and Figure 13. t Figure 10. Early Warning Timing When the input voltage decreases below preset EW threshold then SO output goes low. The input voltage drops continuously further and when output voltage decreases below reset threshold then RO output goes low as well causing uP reset. The time between assuring SO Low and RO Low is called Twarning and provides to uP time to finish R1, R2−ESR of Cin and Cout R3, R4−input inpedance of uP Figure 12. Simplified Schematic for Twarning Calculation http://onsemi.com 5 AND9120/D Figure 13. PSpice Simulation Results for Twarning Conclusion Reference: The NCV8667/69 families bring significant reduction of both quiescent and shutdown currents in the battery supplied applications, and hence, enable longer battery life thanks to unique idea of internal EW resistor divider and internal disconnect switch. The EW threshold can be adjusted with just one external resistor which saves number of components required for EW function and space on PCB. 1. NCV8667 datasheet http://www.onsemi.com/pub_link/Collateral/NCV 8667−D.PDF 2. PSpice model http://www.onsemi.com/PowerSolutions/supportD oc.do?type=models&rpn=NCV8667 http://onsemi.com 6 AND9120/D APPENDIX 1: CALCULATION OF Twarning Schematic: 1. i1(p)R ) i1 R Cin VBAT i2 I Cout Vrt(t) i2(p) + Iout * i1(p) ǒ Ǔ ǒ Ǔ 1 i1(p)ǒR ) 1 ) 1 Ǔ ) IoutǒR p * pCoutǓ + 0 å pCin pCout 1 ) Iout R i1(p) R ) 1 ) 1 p * pCout + 0 pCin pCout Figure 14. * Iout(RCout * 1) i1(p) + Step 1: Regulation and Pre−dropout region DV = Vin_EW(th)_Low − V1 (Input voltage before dropout) Then V1 = Vout + VDO t1 = DV .Cin/I And I = Iout + Iq Ǔ RCout ǒp ) Cin)Cout RCinCout 1 ´ e *at p)a i1(t) + * Iout(RCout * 1) Cin)Cout t2 e RCinCout RCout i2(t) + Iout * i1(t) i1 I 2. Cin Vrt(t) VCin(t) 1 IR Vrt i2(p) ) V1 p * p * p +0å pCout Vrt(t) + Figure 15. t1 + Vrt(t) + ǒVin_EW(th)_Low * V1Ǔ.Cin 1 i2(t) ) u1(t) * IoutR Cout ǒ Ǔ * Iout(RCout * 1) Cin)Cout t2 1 I* e RCinCout ) V1(t) RCout Cout 1 Vrt * V1 ) IoutR * Cout ǒ I ȡ ȧ ǒ Ȣ Ln R i2 Cin Cout VCin(t) VCout(t) Ǔ Iout(RCout*1) 1 Cout RCout Step 2: Dropout region DV = 5.3 V − Vrt (typ. 4.75 V) i1 i1(p) V1 V1 IR i2(p) ) p * p ) p * + 0, pCin pCout Iout Vrt*V1)IoutR* ȣ Ǔȧ Ȥ 1 Cout 1 Iout (RCout*1) Cout RCout Cin)Cout RCinCout Vrt(t) Cin)Cout + e RCinCout t å t2 + t2 T warning + t1 ) t2 Figure 16. VCin(0) = V1 VCout(0) = V1 − IR Iout = i1 + i2 T warning + ǒVin_EW(th)_Low * V1Ǔ.Cin Iout ȡ ȧ Ȣ Ln ) ȣ I Cout Iout(RCout*1) 1 RCout Cout Vrt*V1)IoutR* ǒ Ǔȧ Ȥ * Cin)Cout RCinCout ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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