### Configuring and Applying the MC74HC4046A Phase-Locked Loop

```AN1410/D
Configuring and Applying
the MC74HC4046A
Phase-Locked Loop
A versatile device for 0.1 to 16MHz
frequency synchronization
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APPLICATION NOTE
Prepared by: Cleon Petty, Gary Tharalson & Marten Smith
Logic Application Engineers
Abstract
the following information is useful for approximating a
design but, because of process, layout and other variables,
there can be substantial deviation between theory and actual
results. Therefore, it is highly recommended that
prototypes be built and checked before committing a
design to production.
Typical applications for the HC4046A usually involve a
configuration such as shown in Figure 1.
The MC74HC4046A (hereafter designated HC4046A)
phase–locked loop contains three phase comparators, a
voltage–controlled oscillator (VCO) and an output
amplifier. The user of this document should have a copy of
the HC4046A data sheet in ON Semiconductor Data Book
DL129 available for details of device operation and
operating specifications. The user should also be aware that
Phase Detector
Ref Osc
Low Pass Filter
VCO
fo
Feedback
÷N
Figure 1. Typical Phase–Locked Loop
VCO/OUTPUT FREQUENCY
and reworking it to obtain a formula that incorporates all the
detail to fit the HC4046A. First, the charge time of the device
for half–cycle time is obtained as follows:
The output frequency, Fo, is calculated as a function of the
Ref Osc input and the ÷N feedback counter:
Fo = Ref Osc * N
dt
(1)
The ability of the loop to emulate the above formula
makes it ideal for multiplying an input frequency by any
number up to the maximum of the VCO. The HC4046A
VCO frequency is controlled by the equation:
VCO freq = f(I * C)
or,
+ c dV
dt
 Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
Fo
+
and Fo
1
2CdV
I
+ 2dt1
I
+ 2CdV
(4)
where I and dV must be obtained for the HC4046A.
There are two components that comprise the I charge for
the HC4046A VCO, I1 and I2. I1 is the current that sets the
frequency associated with the VCO input and is a function
of R1, VCOin, and an internal current mirror that is ratioed
at 120/5 ≈ 24, resulting in the equation:
(2)
where I is controlled by the external resistors R1 and R2 and
C by external capacitor Cext .
Frequency of oscillation is calculated by starting with the
familiar equation:
I
+ dV CI
I1
in
+ VCO
R1
ǒ Ǔ
120
5
(5)
(3)
1
Publication Order Number:
AN1410/D
AN1410/D
I2 is set by R2 and adds a constant current to limit the Fo min
of the VCO and is a function of Vdd, R2, and an internal
current mirror of ratio 23/5, resulting in the equation:
I2
+
ǒ Ǔǒ Ǔ
2Vdd
3R2
23
5
1. Iconstant ratio versus R1
R1 (KΩ)
3.0
5.1
9.1
12
15
30
40
51
110
300
(6)
The dV of Equation ( 4 ) is determined by design to be ≈ 1/3
Vdd. Substituting this and I = I1 + I2 into Equation ( 4 ) results
in:
Fo
ǒ Ǔ ) ǒ Ǔǒ Ǔ
2Vdd
3R2
+
VCOin 120
5
R1
+
VCOin
(24)
R1
+
3VCOin
(24)
R1
2Cext
Vdd
3
)ǒ
2Vdd
3R2
23
5
Ǔ
(4.6)
Fo
2Vdd
(4.6)
R2
(7)
2Cext Vdd
Fo
+ 2C
)
For comparison, from Chart 14D in the HC4046A data
sheet, the Fo based on measurements is approximately 270
Hz. Thus, the calculated and measured values are not too far
apart taking into consideration such variables as process
variation, temperature, and breadboard inaccuracies. The
Cstray of a PCB layout will affect results if the Cext is not
Cstray. So for Cext ≤ 1000pF, adding Cstray to the Cext fixed
capacitance will result in better accuracy.
The gain of a VCO is calculated by knowing fmax at
VCOin max and fmin at VCOinmin and calculating the
following equation:
&
2Vdd
(4.6)
R2
) 3 * undershoot)
)
+ 2C (V
ext dd ) 3 * undershoot)
ext (Vdd
3VCOin(Iconstant ratio)
R1
9.2(Vdd)
R2
(3)(1)(31)
300K
+ 2(0.1 * 10-6)(4.5 ) 2.1)
+ 235Hz
It was found by experiment that when the Cext potential
reaches threshold (at Vdd/3), the inversion of the charging
voltage of Cext is forced below ground due to charge
coupling. Therefore, the dV is not just Vdd/3 as expected and
the charging time must start at a point below ground which
affects t and thus, Fo. An undershoot voltage must be added
to the equation for better accuracy in calculating t and Fo.
This modifies Equation ( 7 ) as follows:
3VCOin
(24)
R1
13.5
17.5
21.5
23.0
24.0
26.5
27.0
28.5
29.0
31.0
The VCO calculation [Equation ( 8 )] becomes a bit more
accurate by adjusting the VCOin and Iconstant ratio. For
example, with R1 = 300K, R2 = ∞, Cext = 0.1µF, VCOin =
1.0V, Vdd = 4.5V, and Iconstant ratio = 31, Equation ( 8 ) yields:
V
2Cext 3dd
)
Iconstant ratio
VCO gain
(8)
Equation ( 8 ) now contains all the factors to calculate an Fo
for the HC4046A VCO.
It was determined by experiment that the undershoot of
the charging waveform is a function of Cext and an on–chip
parasitic diode that clamps it at a maximum of –0.7V. The
size of the Cext capacitor limits the voltage and was found to
be near zero volts for Cstray ≈17pF ≤ Cext ≤ 30pF; the voltage
increases at 6 mV/pF for a 30pF ≤ Cext ≤ 150pF range of Cext.
The on–chip diode then takes over and limits the voltage to
–0.7V.
It was also found that the Iconstant ratio is a function of R1
and increases as R1 becomes larger. The change is attributed
to saturation of the current mirror at lower value resistances,
and to voltage divider problems at higher value resistances
combined with the resistance of the small FET in the current
mirror. Experimental data shows that Iconstant ratio follows
Table 1 somewhat. The ratio goes to 25 somewhere between
9.1KΩ and 51KΩ, and for those limits, 25 should give
reasonable results. In addition, these numbers seem to hold
for a range of Vdd of 3.0V ≤ Vdd ≤ 6V.
max * f min
+ VCO f max
* VCOin min
in
+ Dfreqńvolt
(9)
The gain of the VCO is needed to calculate a suitable loop
filter for a PLL system.
Fo is determined by VCOin and is clamped as a function
of a % of Vdd. The clamp voltage generally follows the slope
of 4%/V for Vdd changes from 3.5V ≤ Vdd ≤ 6V, starting at
56% at Vdd = 3.5V and going to 66% at Vdd = 6V. Knowing
this limit point allows picking a VCOin max point a few
hundred mV below it and keeps Fo in the linear range of
operation. It also best to pick a VCOin min point at a level
of a few hundred mV above 0V for the same reason given
above.
As an example, for a Cext =1100pF, R1 = 9.1K, R2 = ∞, Vdd
=5.0V, and VCOin min = 0.25V, VCOin max can be
determined and a gain calculated as follows. VCOin limit =
(4%/V)(1.5V) + 56% = (62%)(Vdd ) = 3.1V. So, for sake of
linearity, choose VCOin = 2.5V. Using Equation ( 8 ), VCOin
min and VCOin max can be used to calculate Fo min and Fo
max as follows:
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Fo min
Now choose a Cext of 200pF. Then, from above result,
(3)(0.25)(21.5)
9.1K
+ 2(1100 * 10-12)(5 ) 2.1) + 113.4KHz
Fo max
R1
(3)(2.5)(21.5)
9.1K
+ 2(1100 * 10-12)(5 ) 2.1) + 1.3MHz
This appears reasonable and there are standard values for
Cext = 200pF and R1 = 27K. Using these values, Equation (
8 ) can be adjusted according to the desired Fo min, Fo max,
and Fo center.
Then, using Equation ( 9 ), the VCO gain is:
VCO gain
6–0.11 * 106
+ 1.3 * 102.5–0.25
+ 528.9KHzńV
LOW PASS FILTER DESIGN
The design of low pass filters is well known and the intent
here is to simply show some typical examples. Reference
should be made to the HC4046A Data Sheet and to
Application Note AN535/D — “Phase–Locked Loop
Fundamentals” (available through ON Semiconductor
Literature Distribution).
Some simple types of low pass filters are shown in
Figure 2 and Figure 3.
This gain factor will be known as Kvco in the loop filter
equations.
R2 is used in applications where a minimum output
frequency is desired when VCOin is 0V. It is calculated at
VCOin = 0V causing Equation ( 8 ) to become:
Fo
(Vdd)
+ 2C (R2) (V9.2
dd ) 3 * undershoot)
charge current for Cext and increases the VCOin versus Fo
curve by a theoretical constant amount. In reality, the
amount of increase actually decreases at a slight rate as
VCOin increases. The decrease is slight and the use of
Equation ( 8 ) will give adequate accuracy for most
applications.
The Fmax of the HC4046A VCO was determined to be
about 16MHz. Beyond 16MHz, the output logic swing tends
to reduce and is therefore somewhat useless for driving a
CMOS input. The VCO will operate at ≈ 28MHz but the
output has a VOL≈ 2.0V and a VOH≈ 4.5V at Vdd = 5.0V.
The following table was generated to make calculation of
R1 and Cext a function of Fo with Vdd = 5V, VCOin = 1V, and
room temperature. Use of the table allows a rough estimate
of (R1)(Cext) for a given Fo. The final values can be adjusted
by use of Equation ( 8 ), Table 1 for Iconstant ratio, rules for
undershoot voltage, Vdd variations, and VCOin variations.
The example below shows a typical calculation.
∅det Charge Pump Output
Cext (pF)
3.0K ≤ R1 ≤ 9.0K
∅det Charge Pump Output
9.1K ≤ R1 ≤ 50K
50K ≤ R1 ≤ 900K
0 ≤ Cext ≤ 30
30 ≤ Cext ≤ 150
150 ≤ Cext ≤ ∞
7.50/Fo
5.77/Fo
5.28/Fo
0 ≤ Cext ≤ 30
30 ≤ Cext ≤ 150
150 ≤ Cext ≤ ∞
9.00/Fo
6.92/Fo
6.34/Fo
VCOin
C1
Figure 3. Simple Low Pass Filter B
The equations for calculating loop natural frequency (wn)
and damping factor (d) are as follows:
For Filter A (Figure 2):
d
+
Ǹ
KøKVCO
NC1R1
n
+ Kø0.5w
KVCO
where K∅ = phase detector gain, KVCO = VCO gain, and N =
divide counter.
For Filter B (Figure 3):
wn
Assume a desired value of Fo of 1MHz. From 2, choose
an R1 range of 9.1K ≤ R1 ≤ 50K and a Cext range of > 150pF;
this condition leads to (R1)(Cext) = 5.28/Fo. Thus,
(R1) (Cext)
R1
R2
(R1)(Cext)
5.40/Fo
4.15/Fo
3.80/Fo
VCOin
Figure 2. Simple Low Pass Filter A
wn
0 ≤ Cext ≤ 30
30 ≤ Cext ≤ 150
150 ≤ Cext ≤ ∞
R1
C1
2. (R1)(Cext) versus Fo
R1 (Ω)
5.28 * 10-6 + 26K
+ 200
* 10-12
d
+ 15.28
+ 5.28 * 10-6
* 106
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3
+
Ǹ
KøKVCO
NC1(R1 R2)
)
+ 0.5wn(R2C1 ) KøKNVCO)
( 10 )
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Figure 4 shows an active filter using an op amp from
Application Note AN535/D.
R1
∅det
(K∅)
Ref Osc
Fref
LP Filter
wn
KVCO
fo
C1
Feedback
÷N
R1
∅det Charge
Pump Output
OP
AMP
VCOin
Figure 5. Parametized PLL
To determine N, use equation (1) for Fo min = 200KHz,
and Fo max = 2MHz resulting in the following:
Figure 4. Op Amp Filter
Ǹ
N min = 200/100 = 2, and
N max = 2000/100 = 20
The results so far indicate the following starting parameters:
For Figure 4, the equations become:
wn
d
+
KøKVCO
NC1R1
( 11 )
R2
+ Kø2wKVCO
nNR1
A. A VCO with a 10:1 range is required
B. wn = Fref/10 = 10KHz
C. d = 0.707
D. R2 = ∞
E. Vdd = 5.0V
( 12 )
+ wnC21R2 , where Op Amp gain is large
The Fo center frequency ≈
F max
From the above equations, it is possible to design a
suitable filter to meet the needs of many PLL applications.
The inclusion of R2 in the equations for Figure 3 and
Figure 4 permits the capability to change wn and d
separately while Figure 2 equations do not. Normally, a
design is easier if wn and d can be chosen independently.
Both factors affect the loop acquisition time and stability. A
good starting value for d is 0.707 and Fref/10 for wn.
Manipulation of the equations allows calculation of R1,
R2, and C1 from the other measured, calculated, or picked
parameters. For example,
R1
) R2 + KNCøKVCO
w 2
( 13 )
R2
* N
+ C2d
1wn C1(KøKVCO)
( 14 )
C1
+ Nw K2ø(RKVCO
)R
C1
* N
+ R2d
2wn R2(KøKVCO)
2
1
2
Recalling that the clamp voltage % at Vdd = 5V is about
62, then Fmax VCOin limit = (0.62)(5) = 3.1V, but as
described earlier, this needs to be reduced by a factor to bring
it into linearity (≈ 350mV) so the final Fmax VCOin limit =
2.75V.
For the Fmin VCOin limit pick 0.25V. This results in a
center frequency VCOin of:
Center freq VCOin
+ 2.75 *2 0.25 + 1.25V
From 2, for picked values of 9.1K≤R1≤50K and 30≤Cext
≤150, obtain an estimate for (R1)(Cext) of 5.77/Fo. Thus, at
the Fo center frequency,
1 n
n
) F min + 2.0 ) 0.2 + 1.1MHz
(R1)(Cext)
+ 1.15.77
+ 5.245 * 10-6
* 106
Now, a reasonable starting point is established for setting the
values of the loop filter and the VCO range. Choosing R1 =
9.1K, Cext becomes
, or alternatively,
2)
Cext
+ 5.2459.1K* 10-6 + 576pF WHOOPS!
This value, 576pF, is outside of the original picked range for
Cext; therefore, we need to go back and pick a larger value
of R1, e.g., 42K should be sufficient. Then Cext becomes
Usually, C1, wn, and d are picked and the remaining
parameters calculated.
DESIGN EXAMPLE
Cext
The goal is to design a phase–locked loop that has an Fref
of 100KHz, an output Fo of 1MHz center frequency, and the
ability to move from 200KHz to 2MHz in 100KHz steps.
+ 5.24542K* 10-6 + 125pF
and now both R1 and Cext are within selected ranges.
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The final values used for the desired frequency range are
R1 = 42kΩ, Cext = 175pF, R2 = , VCOin max = 2.75V, and
VCOin min = 0.25V.
The next step is to determine the loop filter. Choosing a
filter like the one in Figure 3, calculate the component as
follows:
Now calculate Fmax and Fmin using Equation ( 8 ) with R1
= 42kΩ, R2 = , Vdd = 5.0V, Iconstant ratio = 27 (from 1. and
R1 = 42kΩ), Vundershoot = 0.57V (calculated from 6pF/mV
(125pF–30pF) = 0.57V), VCOin min = 0.25V, and VCOin
max = 2.75V:
1
1
0
Fo min
) R
+ (2)(125 * 10-12f) [5.0V
) 3(0.57V)]
(3)(0.25)(27)
42K
(9.2) (5.0)
20.25
+ 70.455
+ 287.4KHz
* 10-6
Fo max
(3)(2.75)(27)
42K
)
0
+
222.75
70.455 * 10-6
) 3(0.57V)]
Fo min
+ 10KHz * 2p + 62.83 * 103radńsec
+ 100KHz
10
where
K∅ = phase detector gain
Vdd = output swing
Fmax is > the required 2.0MHz, but the Fmin is not low
enough for required application. It is necessary to adjust
either Cext or R1 to achieve required specification of 0.2 to
2.0MHz Fo. Since R1 = 42kΩ is a standard resistor value, try
adjusting Cext to a higher value, such as 175pF. Because Cext
is now > 150pF, the Vundershoot must be adjusted to 0.7V, as
per earlier explanation:
So,
)
wn
N = 2 to 20
+ 3.16MHz
Choose C1 to be 0.01µF, N = 10 for approximate
mid–range Fo, and calculate R1 and R2 using Equations ( 13
) and ( 14 ):
R1
R2
)
+ 2250.52–514.4 + 1736W
0
R
(9.2) (5.0)
(2)(175 * 10-12f) [5.0V
Then, R1 = 4924.5 – 1736 = 3188.5Ω.
Since N is changeable, it is a good idea to check min and
Application Note AN535/D or the MC4044 Data Sheet in
the MECL Data Book DL122/D. The following examples
show sample calculations for N = 2 and 20.
For N = 20, use Equation ( 10 ) to calculate wn and d:
) 3(0.7V)]
222.75
+ 104.37
+ 2.13MHz
* 10-6
These values are adequate for the specified application.
The next item to determine is the VCO gain factor, KVCO,
using Equation ( 9 ):
* f min
* VCOin min
KVCO
+
KVCO
* 106 * 0.194 * 106 + 774.4KHzńV
+ 2.13 2.75V
* 0.25V
f max
VCOin max
+ C2d
* N
1wn C1(KøKVCO)
10
+ (0.01 (2)(0.707)
–
* 10-6) (62830) (0.01 * 10-6)(0.4)(4.86 * 106)
and
(3)(2.75)(27)
42K
1 n
0
(9.2) (5.0)
20.25
+ 104.37
+ 194.02KHz
* 10-6
Fo max
(0.4)(4.86 * 106)
) R2 + KNCøKVCO
+
2
w
(10)(0.01 * 10-6)(62.83 * 103)2
* 106 + 4924.5W
+ 1.944
394.76
+ (2)(175 * 10-12f) [5.0VR) 3(0.7V)]
(3)(0.25)(27)
42K
+ V4ddp + 5.0
4p
d = 0.707 (for starters), and
R
(9.2) (5.0)
(2)(125 * 10-12f) [5.0V
Kø
wn min
+
+
Ǹ
KøKVCO
NC1(R1 R2)
)
Ǹ
(0.4)(4.86 * 106)
(20)(0.01 * 10-6)(3188.5
) 1736)
+ 44.43 * 103radńsec [ 7KHz
+ (2p) (774.4 * 103) + 4.86 * 106RadńsecńV
2p
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AN1410/D
and
+ (0.5)(wn)
d min
+
ƪ
R2C1
ƪ
) KøKNVCO
and
ƫ
d max
(0.5)(44.43 * 103) *
(1736)(0.01 * 10-6)
20
) (0.4)(4.86
* 106)
(1736)(0.01 * 10-6)
ƫ
wn max
+
Ǹ
2
) (0.4)(4.86
* 106)
ƫ
+ 1.292
This shows the effect of changing n on loop performance and
If the components are not what is desired, choosing a
different wn and/or d allows them to be modified.
Alternatively, picking different C, R1 or R2 and
recalculating the other parameters can be done. If the filter
does not provide adequate performance, making wn smaller
or d larger may improve stability.
+ 0.6144
For N = 2:
ƪ
+ (0.5)(140.49 * 103) *
(0.4)(4.86 * 106)
(2)(0.01 * 10-6)(3188.5 1736)
)
+ 140.49 * 103radńsec + 22.36KHz
2p
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Notes
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Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email: [email protected]/* <![CDATA[ */!function(t,e,r,n,c,a,p){try{t=document.currentScript||function(){for(t=document.getElementsByTagName('script'),e=t.length;e--;)if(t[e].getAttribute('data-cfhash'))return t[e]}();if(t&&(c=t.previousSibling)){p=t.parentNode;if(a=c.getAttribute('data-cfemail')){for(e='',r='0x'+a.substr(0,2)|0,n=2;a.length-n;n+=2)e+='%'+('0'+('0x'+a.substr(n,2)^r).toString(16)).slice(-2);p.replaceChild(document.createTextNode(decodeURIComponent(e)),c)}p.removeChild(t)}}catch(u){}}()/* ]]> */
ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:
001–800–4422–3781
Email: [email protected]/* <![CDATA[ */!function(t,e,r,n,c,a,p){try{t=document.currentScript||function(){for(t=document.getElementsByTagName('script'),e=t.length;e--;)if(t[e].getAttribute('data-cfhash'))return t[e]}();if(t&&(c=t.previousSibling)){p=t.parentNode;if(a=c.getAttribute('data-cfemail')){for(e='',r='0x'+a.substr(0,2)|0,n=2;a.length-n;n+=2)e+='%'+('0'+('0x'+a.substr(n,2)^r).toString(16)).slice(-2);p.replaceChild(document.createTextNode(decodeURIComponent(e)),c)}p.removeChild(t)}}catch(u){}}()/* ]]> */
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549
Phone: 81–3–5740–2745
Email: [email protected]/* <![CDATA[ */!function(t,e,r,n,c,a,p){try{t=document.currentScript||function(){for(t=document.getElementsByTagName('script'),e=t.length;e--;)if(t[e].getAttribute('data-cfhash'))return t[e]}();if(t&&(c=t.previousSibling)){p=t.parentNode;if(a=c.getAttribute('data-cfemail')){for(e='',r='0x'+a.substr(0,2)|0,n=2;a.length-n;n+=2)e+='%'+('0'+('0x'+a.substr(n,2)^r).toString(16)).slice(-2);p.replaceChild(document.createTextNode(decodeURIComponent(e)),c)}p.removeChild(t)}}catch(u){}}()/* ]]> */
ON Semiconductor Website: http://onsemi.com