AN-769: 基于AD9540产生多时钟输出 (Rev. 0)

AN-769
One Technology Way P.O. Box 9106 Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com
AD9540
Ted Harris
(ADC)
OC-12
(DAC)
622.08 MHz
SYNC
AD9540 IC
(SNR)
(BER)
ADC
DAC
1
“AN-756””
(PLL)
PLL
ADI
AD9540
(IC)
ADI
AD9540
(CML)
655 MHz
ADC
DAC
VCO
(Kv)
AVDD AGND DVDD DGND VCML
VCO
VCO
VCP
CP_RSET
CP
REF, AMP
REFIN
R DIVIDER
PHASE
FREQUENCY
DETECTOR
R E F IN
N DIVIDER
SYNCIN/STATUS
CHARGE
PUMP
CP
CLK2
SYNC, PLL
LOCK
CLK2
CLK1
CML
CLK1
DIVIDER
1, 2, 4, 8
SDO
VCML
SERIAL
CONTROL
PORT
CS
CLK
TIMING AND
CONTROL LOGIC
S2
S1
S0
OUT0
O U T0
SCLK
SDI/O
CMLRSET
PHASE/
FREQUENCY
PROFILES
DIVCLK
48
14
1. AD9540
Rev. 0 | Page 1 of 2
DDS
10
DAC
DACRSET
IOUT
IO U T
AN-960
ᆌᆩԴऻ
ଷྔLjยऺටᇵႴᄲ੊୯࣍ୟ୳հഗ‫੻ټ‬Ljᅺྺ޿֖ຕฉ
‫ټ‬ሯำăഄْLjྺକํ၄‫ܠ‬ຕ้ዓ‫ۉ‬ୟ໯Ⴔ‫ڦ‬უӦ୲LjႴ
٪ሞᅃۨ‫ڦ‬඄࢚࠲ဣăᅃӯܸჾLj࣍ୟ‫੻ټ‬ሁ੻Lj࣍ୟ‫ڦ‬
ᄲॽᅃ߲ྔևԲডഗ֭෇้ዓ႑ࡽୟ০ăԨ૩ዐ჋ᆩ‫ڦ‬
֑णࢅ໮้ۨक़ሁ‫܌‬Lj‫ڍ‬ᄺࣷᆶ߸‫ܠ‬ઠጲएጚࢅ६ೕ६၎
ADCMP563ၳࡕ೤ॅă
ഗԨว‫ڦ‬ሯำཚࡗ࣍ୟăሞ้ዓᆌᆩዐLj੗ᅜཚࡗኄዖ඄
ፌዕ‫ۉڦڟڥ‬ୟ‫ڦ‬०ࣅ઀཮ස཮2໯๖ă๼෇CLK1/CLK1
࢚ൽปઠํ၄ড቏‫࣍ڦ‬ୟ‫੻ټ‬Ljဎึॺ૬้क़Ljᅜᆶ૧ᇀ
૾থ዁CLK2/CLK2ăഗॲ‫ڦ‬Պ‫ݛײ‬๕๟๑CMLൻ‫ۯ‬ഗ‫ڦ‬๼
࣍ୟዐ‫ڦ‬ሯำᅞ዆ă
෇ઠጲCLK1‫ڦ‬࿄‫ݴ‬ೕ๼෇Lj‫ڍ‬DDSᆯ‫ݴ‬ೕ๼‫้ࠃ༵؜‬ዓ
ຕጴ้ዓ໯Ⴔ‫ڦ‬৛ඓೕ୲ࢅ੗ۙ၎࿋੗ٗഗॲ‫ڦ‬኱থຕጴ
)622 MHz‫أ‬ᅜ2 = 311 MHz*ă཮ዐ၂๖କPLL REF๼෇‫ڦ‬ৗ
ೕ୲ࢇ‫ׯ‬ഗ(DDS)ዐׂิăAD9540ฉ‫ڦ‬DDS༵ࠃ48࿋ೕ୲
༹ና‫ږ‬ഗࠀీLjᄇ๖କഄᇑ38 MHzৗ༹ದࢇ๑ᆩ‫ڦ‬൧઄ă
ۙၿ‫ݴ‬Ր୲)1.42 μHzLjፌ‫้ٷ‬ዓ໏୲ྺ400 MHz*ࢅ14࿋၎
ଇ߲๼‫้؜‬ዓ၂๖ሞOUT0 )‫گ‬۶‫ۯ‬622 MHz้ዓ*ࢅOUT1
࿋ۙব)0.022‫*܈‬ăDDS‫ڦ‬๼‫؜‬๟ᅃዖዘࠓ‫ڦ‬ኟ၀հLjᅺُ
)၎࿋੗Պ‫ޤײ‬ዺ้ዓ*‫ت‬ăሞ‫ޤ‬ዺ้ዓዐLjՉᄂೋၽ)ई้
Ⴔᄲଇ߲‫ྔڦྔܮ‬և‫ۉ‬ୟă๯ံLjႴᄲ‫ܔ‬ዘࠓ‫ڦ‬ኟ၀հᆌ
क़ჽ‫*׿‬๟ཚࡗၠDDSዐՊ෇၎࿋ೋᅎઠํ၄‫ڦ‬Lj໲ࣷ߀Վ
ᆩᅃ߲ణՔ้ዓ໏୲‫ټڦ‬ཚ୳հഗăኄࣷၩ‫أ‬๼‫؜‬ೕ೷ዐ
Բডഗ‫ࢻت‬ց๼෇঍֮‫ڦ‬၎‫ۅ้ܔ‬ă
‫ܠڦ‬ຕ֑ᄣ࿁ၟLjཞ้ၩ‫أ‬ᅙᆅ෇዁DAC๼‫؜‬႑ࡽዐ‫੻ڦ‬
38.875MHz
OSCILLATOR
REFIN
M DIVIDER
R E F IN
N DIVIDER
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CLK2
S2
S1
S0
VCO
CLK2
CLK1
CML
CLK1
LOW-PASS
(LOOP) FILTER 622MHz
CLK2
PLL
LOCK
CLK2
CP
O U T0
DIVIDER
1, 2, 4, 8
PHASE/
FREQUENCY
PROFILES
IOUT
48
14
OUT0
DDS
10
཮2. ದዃྺມ้ዓׂิఇ๕‫ڦ‬AD9540
Rev. 0 | Page 2 of 12
ADCMP563
OUT1
DAC
IO U T
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registered trademarks are the property of their respective owners.
AN05356–0–4/05(0)
BAND PASS
FILTER
O U T1