CM1225 4-Channel Low Capacitance ESD Protection Arrays Product Description The CM1225 diode array has been designed to provide ESD protection for electronic components or subsystems requiring minimal capacitive loading. This device is ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading. Each ESD channel consists of a pair of diodes in series which steer the positive or negative ESD current pulse to the ground pins (VN). A Zener diode is embedded between the positive terminal of the diode pair to the ground. This eliminates the need for an external bypass capacitor to absorb positive ESD strikes to ground. The CM1225 protects against ESD pulses up to ±8 kV per the IEC 61000−4−2 standard. The CM1225 is particularly well−suited for protecting systems using high−speed ports such as HDMI, DVI, display, MDDI, USB 2.0, Serial ATA, IEEE1394 (FireWire and i.LINK), corresponding ports in removable storage, digital camcorders, DVD−RW drives and other applications where extremely low loading capacitance with ESD protection are required in a small package footprint. The CM1225 is available in a RoHS−compliant, uUDFN 10−pin package. http://onsemi.com uUDFN−10 DE SUFFIX CASE 517BB BLOCK DIAGRAM CH2 CH1 CH4 VN CH3 CM1225−04DE Features • Four Channels of ESD Protection • Provides ESD Protection to IEC61000−4−2 Level 4 • • • • • • MARKING DIAGRAM ±8 kV Contact Discharge Low Channel Input Capacitance of 0.8 pF (Typically) Channel Input Capacitance Matching (I/O to I/O) of 0.02 pF (Typically) is Ideal for Differential Signals Minimal Capacitance Change for Temperature and Voltage Zener Diode Eliminates the Need for External By−pass Capacitors Each I/O Pin Can Withstand Over 1000 ESD Strikes* These Devices are Pb−Free and are RoHS Compliant 1225 = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Applications • DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs, • • • • • • • 1225 MG G LCD Displays Display and MDDI Ports Serial ATA Ports in Desktop PCs and Hard Disk Drives PCI Express Ports USB2.0 Ports at 480 Mbps in desktop PCs, Notebooks and Peripherals IEEE1394 FireWire Ports at 400 Mbps / 800 Mbps General Purpose High−speed Data Line ESD Protection Protection of Interface Ports or IC Pins which are Exposed to High ESD Levels Device Package CM1225−04DE uUDFN−10 (Pb−Free) Shipping 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to ±8kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes. © Semiconductor Components Industries, LLC, 2011 February, 2011 − Rev. 3 1 Publication Order Number: CM1225/D CM1225 PACKAGE / PINOUT DIAGRAMS Table 1. PIN DESCRIPTIONS 4−Channel, 10−Lead uUDFN−10 Package Top View Pin 1 Marking Name Type Description 1 CH1 I/O ESD Channel 2 CH2 I/O ESD Channel (1) CH1 (2) CH2 3 VN GND Ground (3) VN 4 CH3 I/O ESD Channel 5 CH4 I/O ESD Channel (3) CH3 (4) CH4 6 NC No Connect 7 NC No Connect 8 VN 9 NC GND No Connect 10 NC No Connect 1225 Pin NC (10) NC (9) VN (8) NC (7) NC (6) 10−Lead uUDFN Ground SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units –40 to +85 °C Storage Temperature Range –65 to +150 °C DC Voltage at any Channel Input − 0.5 to + 5.5 V Operating Temperature Range Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. STANDARD OPERATING CONDITIONS Parameter Operating Temperature Range Rating Units –40 to +85 °C Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note1) Symbol VF Parameter Conditions Min Typ Max 0.65 −1.20 0.85 −0.85 1.20 −0.65 Units Diode Forward Voltage Top Diode Bottom Diode IF = 10 mA; TA = 25°C; Note 2 Channel Leakage Current TA = 25°C; VIN = 3.3 V, VN = 0 V ±0.1 ±1.0 mA Channel Input Capacitance At 1 MHz, VN = 0 V, VIN = 1.65 V 0.8 1.0 pF DCIN Channel Input Capacitance Matching At 1 MHz, VN = 0 V, VIN = 1.65 V 0.02 VESD ESD Protection − Peak Discharge Voltage at any Channel Input, in system Contact discharge per IEC 61000−4−2 standard TA = 25°C; (Notes 2 and 3) VCL Channel Clamp Voltage Positive Transients Negative Transients TA = 25°C, IPP = 1 A, tP = 8/20 mS; (Note 3) RDYN Dynamic Resistance Positive Transients Negative Transients IPP = 1 A, tP = 8/20 mS Any I/O pin to Ground; (Note 3) ILEAK CIN V pF kV 1. All parameters specified at TA = –40°C to +85°C unless otherwise noted. 2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded. 3. These measurements performed with no external capacitor. http://onsemi.com 2 ±8 +10 –4.5 1.3 1.3 V W CM1225 PERFORMANCE INFORMATION Input Channel Capacitance Performance Curves Figure 1. Typical Variation of CIN vs. VIN (f = 1 Mhz, VN = 0 V, T = 255C) http://onsemi.com 3 CM1225 PERFORMANCE INFORMATION (Cont’d) Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment) Figure 2. Insertion Loss (S21) vs. Frequency (0 V DC Bias) Figure 3. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias) http://onsemi.com 4 CM1225 APPLICATION INFORMATION Design Considerations As a general rule, the CM1225 ESD protection array should be located as close as possible to the point of entry of expected electrostatic discharges. Use minimum PCB trace lengths to ground planes and between the signal input and the ESD devices. Additional Information See also ON Semiconductor Application Note “Design Considerations for ESD Protection”. Figure 4. Typical HDMI ESD Protection with CM1225 Connection http://onsemi.com 5 CM1225 APPLICATION INFORMATION (Cont’d) Figure 5. Display Port ESD Protection with CM1225 Connection http://onsemi.com 6 CM1225 MECHANICAL DETAILS uUDFN−10 Mechanical Specifications, 0.5 mm The 10−lead, 0.5 mm pitch uUDFN package dimensions are presented below. Table 5. TAPE AND REEL SPECIFICATIONS Part Number Chip Size (mm) Pocket Size (mm) B0 X A0 X K0 Tape Width W Reel Diameter Qty per Reel P0 P1 CM1225 2.50 X 1.00 X 0.50 2.80 X 1.45 X 0.70 8 mm 178 mm (7”) 3000 4 mm 4 mm Po Top Cover Tape Ao + Ko For Tape Feeder Reference Only Including Draft, Concerning around B. 10 Pitches Cumulative Tolerance On Tape ±0.2 mm Embossment Bo + P1 User Direction of Feed http://onsemi.com 7 + Center Lines of Cavity W CM1225 PACKAGE DIMENSIONS UDFN10 2.5x1, 0.5P CASE 517BB−01 ISSUE O L L D PIN ONE REFERENCE 0.10 C 2X 2X A B L1 ÍÍÍ 0.10 C DETAIL A TOP VIEW EXPOSED Cu DETAIL B A3 0.10 C 10X OPTIONAL CONSTRUCTIONS E A A1 0.08 C A1 C SIDE VIEW 2X DETAIL A b2 1 10 10X ÇÇ ÇÇ ÉÉ MOLD CMPD A3 DETAIL B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. DIM A A1 A3 b b2 D E e L L1 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 0.35 0.45 2.50 BSC 1.00 BSC 0.50 BSC 0.30 0.40 --0.05 OPTIONAL CONSTRUCTION SEATING PLANE L 5 RECOMMENDED SOLDERING FOOTPRINT* 6 e 8X 10X 0.10 C A BOTTOM VIEW 2X 0.50 b 0.05 C 0.45 B NOTE 3 1.30 PACKAGE OUTLINE 0.50 PITCH 8X 0.25 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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