8-Channel Low Capacitance ESD Protection Arrays

CM1293
8-Channel Low
Capacitance ESD
Protection Arrays
Product Description
The CM1293 family of diode arrays has been designed to provide
ESD protection for electronic components or sub−systems requiring
minimal capacitive loading. These devices are ideal for protecting
systems with high data and clock rates or for circuits requiring low
capacitive loading. Each ESD channel consists of a pair of diodes in
series which steer the positive or negative ESD current pulse to either
the positive (VP) or negative (VN) supply rail. A Zener diode is
embedded between VP and VN, offering two advantages. First, it
protects the VCC rail against ESD strikes, and second, it eliminates the
need for a bypass capacitor that would otherwise be needed for
absorbing positive ESD strikes to ground. The CM1293 will protect
against ESD pulses up to (8 kV contact discharge) per the
IEC 61000−4−2 Level 4 standard.
This device is particularly well−suited for protecting systems using
high−speed ports such as USB2.0, IEEE1394 (FireWire®, i.LINKt),
Serial ATA, DVI, HDMI and corresponding ports in removable
storage, digital camcorders, DVD−RW drives and other applications
where extremely low loading capacitance with ESD protection are
required in a small package footprint.
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MSOP−10
MR SUFFIX
CASE 846AE
BLOCK DIAGRAM
CH8
CH7
CH1 CH2
VP
VN
CH6 CH5
CH3
CH4
CM1293−08MR
MARKING DIAGRAM
Features
• Eight Channels of ESD Protection
•
•
•
•
•
•
•
Note: For 2 and 4 Channel Devices, See the CM1293A Datasheet
Provides ESD Protection to IEC61000−4−2
• ±8 kV Contact Discharge
Low Loading Capacitance of 2.0 pF Max
Low Clamping Voltage
Channel I/O to I/O Capacitance 1.5 pF Typical
Zener Diode Protects Supply Rail and Eliminates the Need for
External By−Pass Capacitors
Each I/O Pin Can Withstand over 1000 ESD Strikes*
These Devices are Pb−Free and are RoHS Compliant
Applications
• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
D039
D039
= CM1293−08MR
ORDERING INFORMATION
Device
Package
Shipping†
CM1293−08MR
MSOP−10
(Pb−Free)
4000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
LCD Displays
• Serial ATA Ports in Desktop PCs and Hard Disk Drives
• PCI Express Ports
• General Purpose High−Speed Data Line ESD Protection
*Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to ±8 kV contact discharge for 1000 pulses. Discharges
are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production
test to verify that all of the tested parameters are within spec after the 1000 strikes.
© Semiconductor Components Industries, LLC, 2011
March, 2011 − Rev. 4
1
Publication Order Number:
CM1293/D
CM1293
PACKAGE / PINOUT DIAGRAM
Table 1. PIN DESCRIPTIONS
8−Channel, 10−Lead MSOP−10 Package
Top View
Name
Type
Description
1
CH1
I/O
ESD Channel
2
CH2
I/O
ESD Channel
3
CH3
I/O
ESD Channel
4
CH4
I/O
ESD Channel
5
VN
GND
Negative Voltage Supply Rail
6
CH5
I/O
ESD Channel
7
CH6
I/O
ESD Channel
8
VP
PWR
Positive Voltage Supply Rail
9
CH7
I/O
ESD Channel
10
CH8
I/O
ESD Channel
CH1
CH2
CH3
CH4
VN
1
2
3
4
5
D039
Pin
10
9
8
7
6
CH8
CH7
VP
CH6
CH5
10−Lead MSOP−10
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
6.0
V
Operating Temperature Range
−40 to +85
°C
Storage Temperature Range
−65 to +150
°C
(VN − 0.5) to (VP + 0.5)
V
Operating Supply Voltage (VP − VN)
DC Voltage at any Channel Input
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
Package Power Rating
MSOP−10 Package (CM1293−08MR)
Rating
Units
−40 to +85
°C
400
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2
mW
CM1293
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter
Conditions
VP
Operating Supply Voltage (VP−VN)
IP
Operating Supply Current
(VP−VN) = 3.3 V
VF
Diode Forward Voltage
Top Diode
Bottom Diode
IF = 8 mA, TA = 25°C
Channel Leakage Current
Min
Max
Units
3.3
5.5
V
8.0
mA
V
0.80
0.80
0.95
0.95
TA = 25°C, VP = 5 V, VN = 0 V
±0.1
±1.0
mA
Channel Input Capacitance
At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V
1.0
1.5
pF
DCIN
Channel Input Capacitance Matching
At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V
0.02
pF
CMUTUAL
Mutual Capacitance between Signal
Pin and Adjacent Signal Pin
At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V
0.11
pF
ILEAK
CIN
VESD
VCL
RDYN
1.
2.
3.
4.
ESD Protection
Peak Discharge Voltage at any
Channel Input, in System
Contact Discharge per
IEC 61000−4−2 Standard
0.60
0.60
Typ
kV
TA = 25°C (Notes 3 and 4)
Channel Clamp Voltage
Positive Transients
Negative Transients
TA = 25°C, IPP = 1 A, tP = 8/20 mS
(Note 4)
Dynamic Resistance
Positive Transients
Negative Transients
IPP = 1 A, tP = 8/20 mS
Any I/O Pin to Ground (Note 4)
±8
+8.8
−1.4
0.7
0.4
All parameters specified at TA = −40°C to +85°C unless otherwise noted.
Human Body Model per MIL−STD−883, Method 3015, CDischarge = 100 pF, RDischarge = 1.5 KW, VP = 3.3 V, VN grounded.
Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded.
These measurements performed with no external capacitor on VP (VP floating).
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3
V
W
CM1293
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves
Figure 1. Typical Variation of CIN vs. VIN
(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN, 255C)
Figure 2. Typical Variation of CIN vs. Temp
(f = 1 MHz, VIN = 30 mV, VP = 3.3 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN)
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4
CM1293
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (Nominal Conditions unless Specified Otherwise, 50 W Environment)
Figure 3. Insertion Loss (S21) vs. Frequency (0 VDC Bias, VP = 3.3 V)
Figure 4. Insertion Loss (S21) vs. Frequency (2.5 VDC Bias, VP = 3.3 V)
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CM1293
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground,
which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to power
supply is represented by L1 and L2. The voltage VCL on the line being protected is:
VCL = Fwd Voltage Drop of D1 + VSUPPLY + L1 x d(IESD ) / dt + L2 x d(IESD ) / dt
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(IESD)/dt can be
approximated by DIESD/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V
increment in VCL!
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
The CM1293 has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance
L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when
VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 mF ceramic chip
capacitor be connected between VP and the ground plane.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
L2
VP
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
D1
0.22 mF
D2
VN
ONE
CHANNEL
POSITIVE SUPPLY RAIL
VCC
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
PATH OF ESD CURRENT PULSE IESO
LINE BEING
PROTECTED
L1
CHANNEL
INPUT
25 A
0A
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
VCL
GROUND RAIL
CHASSIS GROUND
Figure 5. Application of Positive ESD Pulse between Input Channel and Ground
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CM1293
PACKAGE DIMENSIONS
MSOP 10, 3x3
CASE 846AE−01
ISSUE O
SYMBOL
MIN
NOM
A
E
E1
MAX
1.10
A1
0.00
0.05
0.15
A2
0.75
0.85
0.95
b
0.17
0.27
c
0.13
0.23
D
2.90
3.00
3.10
E
4.75
4.90
5.05
E1
2.90
3.00
3.10
e
L
0.50 BSC
0.40
0.60
L1
0.95 REF
L2
0.25 BSC
θ
0º
0.80
8º
DETAIL A
TOP VIEW
D
A
A2
END VIEW
c
A1
e
b
q
SIDE VIEW
L2
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L
L1
DETAIL A
FireWire is a registered trademark of Apple Computer, Inc.; i.LINK is a trademark of Sony Corporation.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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For additional information, please contact your local
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CM1293/D
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