150 mA LDO Linear Voltage Regulator with Delay, Reset, Adjustable Reset, and Early Warning

NCV8512
5.0 V Micropower 150 mA
LDO Linear Regulator with
DELAY, Adjustable RESET,
and Monitor FLAG
The NCV8512 is a 5.0 V precision micropower voltage regulator.
The output current capability is 150 mA.
The output voltage is accurate within ±2.0% with a maximum
dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature
drawing only 130 mA with a 100 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
Microprocessor control logic includes an active RESET (with
DELAY), and a FLAG monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending RESET
signal. The use of the FLAG monitor allows the microprocessor to
finish any signal processing before the RESET shuts the
microprocessor down.
The active RESET circuit operates correctly at an output voltage as
low as 1.0 V. The RESET function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.
The reset threshold voltage can be decreased by the connection of an
external resistor divider to RADJ lead.
The regulator is protected against reverse battery, short circuit, and
thermal overload conditions. The device can withstand load dump
transients making it suitable for use in automotive environments.
Features
•
•
•
•
•
•
•
•
•
•
•
•
5.0 V ± 2.0% Output
Low 130 mA Quiescent Current
Active RESET
Adjustable Reset
150 mA Output Current Capability
Fault Protection
− +60 V Peak Transient Voltage
− −15 V Reverse Voltage
− Short Circuit
− Thermal Overload
Early Warning through FLAG/MON Leads
Thermally Enhanced in SOW−16 Exposed Pad
NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
AEC Qualified
PPAP Capable
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2008
July, 2008 − Rev. 3
1
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MARKING
DIAGRAM
16
16
1
SOIC 16 LEAD
WIDE BODY
EXPOSED PAD
PW SUFFIX
CASE 751AG
A
WL
YY
WW
G
NCV8512
AWLYYWWG
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
PIN CONNECTIONS*
NC
VOUT
NC
NC
NC
NC
VIN
MON
1
16
FLAG
RESET
NC
GND
NC
NC
DELAY
RADJ
*Pin connections for reference only.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Publication Order Number:
NCV8512/D
NCV8512
VIN
VOUT
VDD
RADJ1
10 mF
10 mF
RADJ
RADJ2
NCV8512
Delay
RM1
RFLG
10 k
Microprocessor
VBAT
RRST
10 k
MON
RM2
CDELAY
FLAG
RESET
I/O
GND
I/O
Figure 1. Application Diagram
MAXIMUM RATINGS†
Rating
Value
Unit
−15 to 45
V
Peak Transient Voltage (46 V Load Dump @ VIN = 14 V). Voltage with respect to ground.
60
V
Operating Voltage
45
V
VOUT (DC)
16
V
Voltage Range (RESET, FLAG)
−0.3 to 10
V
Input Voltage Range (MON)
−0.3 to 10
V
VDELAY
−0.3 to 4.0
V
VRADJ
−0.3 to 10
V
2.0
kV
Junction Temperature, TJ
−40 to +150
°C
Storage Temperature, TS
−55 to 150
°C
VIN (DC)
ESD Susceptibility (Human Body Model)
Package Thermal Resistance, SOW−16 E Pad:
Junction−to−Case, RqJC
Junction−to−Ambient, RqJA
Lead Temperature Soldering:
16
57
Reflow: (SMD styles only) (Notes 1, 2. and 3)
Moisture Sensitivity Level at 260°C
265 peak
°C/W
°C
1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†During the voltage range which exceeds the maximum tested voltage of VIN, operation is assured, but not specified. Wider limits may apply.
Thermal dissipation must be observed closely.
1. 60 second maximum above 217°C.
2. −5°C/+0°C allowable conditions.
3. Per IPC/JEDEC J−STD−020C.
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NCV8512
ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, −40°C ≤ TJ ≤ 125°C; 6.0 V < VIN < 26 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
4.90
4.85
5.0
5.0
5.10
5.15
V
V
−
−
400
100
600
150
mV
mV
-30
5.0
30
mV
OUTPUT STAGE
Output Voltage
9.0 V < VIN < 16 V, 100 mA ≤ IOUT ≤ 150 mA
6.0 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA
Dropout Voltage (VIN − VOUT)
IOUT = 150 mA
IOUT = 1.0 mA
Load Regulation
VIN = 14 V, 5.0 mA ≤ IOUT ≤ 150 mA
Line Regulation
[VOUT(typ) + 1.0] < VIN < 26 V, IOUT = 1.0 mA
−
15
60
mV
Quiescent Current, (IQ)
Active Mode
IOUT = 100 mA, VIN = 12 V, Delay = 3.0 V, MON = 3.0 V
IOUT = 75 mA, VIN = 14 V, Delay = 3.0 V, MON = 3.0 V
IOUT ≤ 150 mA, VIN = 14 V, Delay = 3.0 V, MON = 3.0 V
−
−
−
130
4.0
12
200
6.0
19
mA
mA
mA
−
151
300
−
mA
Current Limit
Short Circuit Output Current
VOUT = 0 V
40
190
−
mA
Thermal Shutdown
(Guaranteed by Design)
150
180
−
°C
RESET Threshold
HIGH (VRH)
LOW (VRL)
VOUT Increasing
VOUT Decreasing
4.55
4.50
4.70
4.60
0.98 × VOUT
0.97 × VOUT
V
V
Output Voltage
Low (VRLO)
1.0 V ≤ VOUT ≤ VRL, RRESET = 10 k
−
0.1
0.4
V
RESET FUNCTION (RESET)
Delay Switching Threshold (VDT)
−
1.4
1.8
2.2
V
Lower Delay Switching Threshold
(VLD)
−
0.3
0.45
0.6
V
−
−
0.1
V
Reset Delay Low Voltage
VOUT < RESET Threshold Low(min)
Delay Charge Current
DELAY = 1.0 V, VOUT > VRH
6.0
9.0
15
mA
Delay Discharge Current
DELAY = 1.0 V, VOUT = 1.5 V
5.0
−
−
mA
1.23
1.31
1.39
V
1.10
1.20
1.31
V
20
50
100
mV
−0.5
0.1
0.5
mA
−
0.1
0.4
V
Reset Adjust Switching Voltage
(VR(ADJ))
−
FLAG/MONITOR
Monitor Threshold
Increasing and Decreasing
Hysteresis
−
Input Current
MON = 2.0 V
Output Saturation Voltage
MON = 0 V, IFLAG = 1.0 mA
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NCV8512
PACKAGE PIN DESCRIPTION
Package Pin Number
SOW−16 Exposed Pad
Pin Symbol
1, 3−6, 11, 12, 14
NC
2
VOUT
7
VIN
8
MON
Monitor. Input for early warning comparator. If not needed connect to VOUT.
9
RADJ
Reset Adjust. If not needed connect to ground.
10
DELAY
13
GND
15
RESET
16
FLAG
Function
No connection.
±2.0%, 150 mA output.
Input Voltage.
Timing capacitor for RESET function.
Ground. All GND leads must be connected to Ground.
Active reset (accurate to VOUT ≥ 1.0 V).
Open collector output from early warning comparator.
TYPICAL PERFORMANCE CHARACTERISTICS
5.01
1.2
VOUT = 5.0 V
VIN = 14 V
IOUT = 5.0 mA
VIN = 12 V
1.0
5.00
+125°C
IQ (mA)
VOUT (V)
0.8
4.99
+25°C
0.6
−40°C
0.4
0.2
4.98
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
0
95 110 125
Figure 2. Output Voltage vs. Temperature
14
5
10
15
IOUT (mA)
20
7
VIN = 12 V
T = 25°C
6
10
IQ (mA)
+25°C
6
−40°C
4
4
3
1
0
0
15
30
45
60 75 90
IOUT (mA)
IOUT = 50 mA
2
2
0
IOUT = 100 mA
5
+125°C
8
25
Figure 3. Quiescent Current vs. Output Current
12
IQ (mA)
0
105 120 135 140
IOUT = 10 mA
6
8
10
12
14
16 18
VIN (V)
20
22
24
Figure 5. Quiescent Current vs. Input Voltage
Figure 4. Quiescent Current vs. Output Current
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4
26
NCV8512
TYPICAL PERFORMANCE CHARACTERISTICS
150
450
IOUT = 100 mA
400
Dropout Voltage (mV)
145
IQ (mA)
140
T = 25°C
135
130
125
120
350
300
+125°C
250
+25°C
−40°C
200
150
100
50
6
10
14
18
22
0
26
0
25
50
VIN (V)
Figure 6. Quiescent Current vs. Input Voltage
75
IOUT (mA)
100
125
150
Figure 7. Dropout Voltage vs. Output Current
1000
1000
Unstable Region
Unstable Region
CVOUT = 10 mF
100
CVOUT = 0.1 mF
ESR (W)
ESR (W)
100
10
10
1
Stable Region
Stable Region
0.1
1
CVOUT = 10 mF
0.01
0 10 20 30 40 50 60 70 80 90 100110120130140150
OUTPUT CURRENT (mA)
0
10
20
30
40
50
60
70
80
90
100 110
OUTPUT CURRENT (mA)
Figure 8. Output Capacitor ESR
Figure 9. Output Stability with Output
Capacitor Change
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NCV8512
VOUT
VIN
Current Source
(Circuit Bias)
IBIAS
Current Limit
Sense
+
+
−
RADJ
IBIAS
+ −
VBG
RESET
+
−
VBG
1.8 V
Thermal
Protection
3.0 mA
Delay
Error Amplifier
IBIAS
Bandgap
Reference
VBG
VBG
IBIAS
+
−
MON
Figure 10. Block Diagram
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GND
FLAG
NCV8512
CIRCUIT DESCRIPTION
VIN
RESET Threshold
VOUT
1.8V VDT
0.45V VLD
DELAY
RESET
Td
Td
Power on
Reset
Input Under−voltage
V Dip
Secondary Output
Spike
Overload
Figure 11. Reset and Delay Circuit Wave Forms
REGULATOR CONTROL FUNCTIONS
The NCV8512 contains a microprocessor−compatible
control function RESET (Figure 11).
If the reset adjust option is not needed, the RADJ pin
should be connected to GND causing the reset threshold to
go to its default value (4.65 V typical).
As an example, select resistors to give a threshold voltage
of 4.0 V. This will allow the delay timer to start when the
output crosses the 4.0 V level.
VTHRES = 4.0 V = 1.31 V x (RADJ1 + RADJ2) / RADJ2
Let RADJ2 be 100 kW for low current consumption.
RADJ1 = 2.05 x 100 k = 205 kW
With 5 V on the output, the voltage on the RADJ pin will
be 1.64 V.
RESET Function
A RESET signal (low voltage) is generated as the IC
powers up. After VOUT increases above the RESET
threshold, the DELAY timer is started. When the DELAY
timer passes 1.8 V, the RESET signal goes high. A discharge
of the DELAY timer is started when VOUT drops and stays
below the RESET threshold. When the DELAY timer level
drops below 0.45 V, the RESET signal is brought low.
The RESET output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the RESET signal is valid for VOUT as low
as 1.0 V.
NCV8512
The reset threshold VRL can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from VOUT to the pin RADJ as
displayed in Figure 12. The resistor divider keeps the
voltage above the VRADJ.TH (typical 1.31 V) and overrides
the internal threshold detector. Adjust the voltage divider
according to the following relationship:
VTHRES + VRADJ.TH
VOUT
RADJ
RADJ2
Adjustable Reset Function
RADJ1 ) RADJ2
RADJ2
to mP and
System
Power
RADJ1
Delay
RRST
RESET
CDELAY
6.4 V
COUT
to mP and
RESET
Port
Figure 12. Adjustable RESET
(2)
DELAY Function
Where;
VTHRES is the desired output threshold voltage that starts
the time delay for Power on Reset Delay.
VRADJ.TH is the default threshold voltage of 1.31 V typ.
RADJ1 is the resistor connected from the 5 V output to the
RADJ pin.
RADJ2 is the resistor connected from the RADJ pin to
ground.
The reset delay circuit provides a delay (programmable by
external capacitor) on the RESET output lead.
The DELAY lead provides source current (typically 9 mA)
to the external DELAY capacitor at the following times:
1. During Power Up (once the regulation threshold
has been exceeded).
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NCV8512
trip point can be programmed externally using a resistor
divider to the input monitor (MON) (Figure 13). The typical
threshold is 1.20 V on the MON Pin.
2. After a reset event has occurred and the device is
back in regulation. The DELAY capacitor is
discharged when the regulation (RESET threshold)
has been violated. When the DELAY capacitor
discharges to 0.45 V, the RESET signal pulls low.
VBAT
FLAG/Monitor Function
MON
VCC
RFLG
NCV8512
RM1
An on−chip comparator is available to provide an early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the FLAG pin
will allow the microprocessor time to complete its present
task before shutting down. This function is performed by a
comparator referenced to the bandgap voltage. The actual
VOUT
VIN
I/O
FLAG
RM2
mP
COUT
RRST
RADJ
RESET
Delay
GND
RESET
Figure 13. FLAG/Monitor Function
APPLICATION NOTES
FLAG MONITOR
Figure 14 shows the FLAG Monitor waveforms taken
from the circuit depicted in Figure 13. As the output voltage
falls (VOUT), the Monitor threshold is crossed. This causes
the voltage on the FLAG output to go low sending a warning
signal to the microprocessor that a RESET signal may occur
in a short period of time. TWARNING is the time the
microprocessor has to complete the function it is currently
working on and get ready for the RESET shutdown signal.
Use the typical value for VDT = 1.8 V.
Use the typical value for Delay Charge Current = 9.0 mA.
tDELAY +
9.0 mA
+ 6.45 ms
STABILITY CONSIDERATIONS
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay,
load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturer’s data sheet usually provides this information.
The value for the output capacitor COUT shown in Figure 15
should work for most applications, but is not necessarily the
optimized solution.
VOUT
MON
FLAG Monitor
Ref. Voltage
RESET
FLAG
VIN
VOUT
CIN*
0.1 mF
TWARNING
Figure 14. FLAG Monitor Circuit Waveform
NCV8512
RRST
COUT**
10 mF
RESET
SETTING THE DELAY TIME
The delay time is controlled by the Reset Delay Low
Voltage, Delay Switching Threshold, and the Delay Charge
Current. The delay follows the equation:
tDELAY +
ƪ33 nF(1.8 * 0.04 V)ƫ
*CIN required if regulator is located far from the power supply filter.
**COUT required for stability. Capacitor must operate at minimum
temperature expected.
ƪCDELAY(VDT * Reset Delay Low Voltage)ƫ
Delay Charge Current
Figure 15. Test and Application Circuit Showing
Output Compensation
Example:
Using CDELAY = 33 nF.
Use the typical value for Delay Low Voltage = 0.04 V.
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NCV8512
CALCULATING POWER DISSIPATION IN A
SINGLE OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 16) is:
PD(max) + [VIN(max) * VOUT(min)] IOUT(max)
HEATSINKS
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
(1)
) VIN(max)IQ
where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current for the
application, and
IQ is the quiescent current the regulator consumes at
IOUT(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
T
RqJA + 150C * A
PD
RqJA + RqJC ) RqCS ) RqSA
(2)
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
IOUT
IIN
SMART
REGULATOR®
VIN
(3)
where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heatsink thermal resistance, and
RqSA = the heatsink−to−ambient thermal resistance.
RqJC appears in the package section of the data sheet. Like
RqJA, it too is a function of package type. RqCS and RqSA are
functions of the package type, heatsink and the interface
between them. These values appear in heatsink data sheets
of heat sink manufacturers.
Further mounting and cooling information is available in
the application note, AN1040/D, “Mounting Considerations
for
Power
Semiconductors”
located
in
the
ON Semiconductor web site.
VOUT
} Control
Features
IQ
Figure 16. Single Output Regulator with Key
Performance Parameters Labeled
ORDERING INFORMATION
Device
NCV8512PW50G
NCV8512PW50R2G
Output Voltage
Package
Shipping†
5.0 V
SOW−16 E Pad
(Pb−Free)
47 Units / Rail
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCV8512
PACKAGE DIMENSIONS
SOIC 16 LEAD WIDE BODY, EXPOSED PAD
PW SUFFIX
CASE 751AG−01
−U−
ISSUE A
A
M
P
0.25 (0.010)
M
W
M
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
6. 751R-01 OBSOLETE, NEW STANDARD 751R-02.
9
B
1
R x 45_
8
−W−
G
PIN 1 I.D.
14 PL
DETAIL E
TOP SIDE
C
F
−T−
0.10 (0.004) T
K
D 16 PL
0.25 (0.010)
T U
M
SEATING
PLANE
W
S
J
S
DETAIL E
H
EXPOSED PAD
1
SOLDERING FOOTPRINT*
8
0.350
L
16
DIM
A
B
C
D
F
G
H
J
K
L
M
P
R
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.136
0.144
0.010
0.012
0.000
0.004
0.186
0.194
0_
7_
0.395
0.415
0.010
0.029
Exposed
Pad
0.175
9
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
3.45
3.66
0.25
0.32
0.00
0.10
4.72
4.93
0_
7_
10.05
10.55
0.25
0.75
0.050
BACK SIDE
CL
0.200
0.188
CL
0.376
0.074
0.150
0.024
DIMENSIONS: INCHES
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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Phone: 81−3−5773−3850
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For additional information, please contact your local
Sales Representative
NCV8512/D
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