12V Synchronous Buck Power MOSFET Driver

NCP5355
12 V Synchronous Buck
Power MOSFET Driver
The NCP5355 is a dual MOSFET gate driver optimized to drive the
gates of both high− and low−side Power MOSFETs in a Synchronous
Buck converter. The NCP5355 is an excellent companion to
multiphase controllers that do not have integrated gate drivers, such as
ON Semiconductor’s NCP5314 or NCP5316. This architecture
provides the power supply designer greater flexibility by being able to
locate the gate drivers close to the MOSFETs.
Driving MOSFETs with a 12 V source as opposed to a 5.0 V can
significantly reduce conduction losses. Optimized internal, adaptive
nonoverlap circuitry further reduces switching losses by preventing
simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate MOSFET drain
voltages as high as 26 V. Both gate outputs can be driven low by
applying a low logic level to the Enable (EN) pin. An Undervoltage
Lockout function ensures that both driver outputs are low when the
supply voltage is low, and a Thermal Shutdown function provides the
IC with overtemperature protection.
The NCP5355 has the same pinout as the NCP5351 5.0 V
Gate Driver.
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MARKING
DIAGRAMS
8
SOIC−8
D SUFFIX
CASE 751
8
1
1
8
•
•
•
•
•
8.0 V − 14 V Gate Drive Capability
2.0 A Peak Drive Current
Rise and Fall Times < 15 ns Typical into 3300 pF
Propagation Delay from Inputs to Outputs < 30 ns
Adaptive Nonoverlap Time Optimized for Large Power MOSFETs
Floating Top Driver Accommodates Applications Up to 26 V
Undervoltage Lockout to Prevent Switching when the Input
Voltage is Low
Thermal Shutdown Protection Against Overtemperature
TG to DRN Pulldown Resistor Prevents HV Supply−Induced
Turn−On of Top MOSFET
BG to PGND Pulldown Resistor Prevents Transient Turn On of
Bottom MOSFET
Internal Bootstrap Diode Reduces Parts Count and Total
Solution Cost
Pb−Free Package is Available
SOIC−8 EP
D SUFFIX
CASE 751AC
8
1
5355
ALYW
1
Features
•
•
•
•
•
•
•
5355
ALYW
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
DRN
1
8
PGND
TG
BST
BG
VS
CO
EN
ORDERING INFORMATION
Package
Shipping†
NCP5355D
SOIC−8
98 Units/Rail
NCP5355DR2
SOIC−8
2500 / Tape & Reel
NCP5355DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP5355PDR2
SOIC−8 EP
2500 / Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
 Semiconductor Components Industries, LLC, 2004
December, 2004 − Rev. 7
1
Publication Order Number:
NCP5355/D
NCP5355
5V
VS
5 V Regulator
BST
5V
Overtemp.
Shutdown
5V
5V
5V
VS
TG
Level Shift
5V
Driver
−
+
100 k
DRN
5V
UVLO
8.0/7.0 V
30 k
Nonoverlap
30 ns
PGND
20 k
5V
5V
CO
20 k
Nonoverlap
30 ns
5V
5V
2.0 A
5V
30 k
VS
VS
5V
BG
Level Shift
Driver
EN
Figure 1. Block Diagram
PACKAGE PIN DESCRIPTION
Pin
Pin Symbol
Description
1
DRN
2
TG
Driver output to the high−side MOSFET gate.
3
BST
Bootstrap supply voltage input. In conjunction with an internal diode to VS, a 0.1 F to 1.0 F ceramic
capacitor connected between BST and DRN develops supply voltage for the high−side driver (TG).
4
CO
Logic level control input produces complementary output states − no inversion at TG; inversion at BG.
5
EN
Logic level enable input forces TG and BG low when EN is low. When EN is high (5.0 V), normal operation
ensues. No connect defaults EN high. Note: maximum high input is 5.0 V.
6
VS
Power supply input. A 0.1 F to 1.0 F ceramic capacitor should be connected from this pin to PGND.
7
BG
Driver output to the low−side (synchronous rectifier) MOSFET gate.
8
PGND
The switching node common to the high and low−side FETs. The high−side (TG) driver and supply (BST)
are referenced to this pin.
Ground.
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2
NCP5355
MAXIMUM RATINGS
Rating
Value
Unit
Internally Limited
°C
Package Thermal Resistance: SOIC−8
Junction−to−Case, RJC
Junction−to−Ambient, RJA
45
165
°C/W
°C/W
Package Thermal Resistance: SOIC−8 EP
Junction−to−Ambient, RJA (Note 1)
50
°C/W
Storage Temperature Range, TS
−65 to 150
°C
Lead Temperature Soldering: Reflow: (SMD styles only) (Note 2)
230 peak
°C
1
−
Operating Junction Temperature, TJ
JEDEC Moisture Sensitivity
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
1. Ratings applies when soldered to an appropriate thermal area on the PCB.
2. 60 seconds maximum above 183°C.
MAXIMUM RATINGS
Pin Symbol
Pin Name
VMAX
VMIN
ISOURCE
ISINK
VS
Main Supply Voltage Input
15 V
−0.3 V
NA
2.0 A Peak (< 100 s)
250 mA DC
BST
Bootstrap Supply Voltage
Input
30 V wrt/PGND
15 V wrt/DRN
−0.3 V wrt/DRN
NA
2.0 A Peak (< 100 s)
250 mA DC
DRN
Switching Node
(Bootstrap Supply Return)
26 V
−1.0 V DC
−5.0 V for 100 ns
−6.0 V for 20 ns
2.0 A Peak (< 100 s)
250 mA DC
NA
TG
High−Side Driver Output
(Top Gate)
30 V wrt/PGND
15 V wrt/DRN
−0.3 V wrt/DRN
2.0 A Peak (< 100 s)
250 mA DC
2.0 A Peak (< 100 s)
250 mA DC
BG
Low−Side Driver Output
(Bottom Gate)
15 V
−0.3 V
2.0 A Peak (< 100 s)
250 mA DC
2.0 A Peak (< 100 s)
250 mA DC
CO
TG and BG Control Input
5.5 V
−0.3 V
1.0 mA
1.0 mA
EN
Enable Input
5.5 V
−0.3 V
1.0 mA
1.0 mA
PGND
Ground
0V
0V
2.0 A Peak (< 100 s)
250 mA DC
NA
NOTE:
All voltages are with respect to PGND except where noted.
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3
NCP5355
ELECTRICAL CHARACTERISTICS (Note 3) (0°C < TJ < 125°C; 9.2 V < VS <13.2 V; 9.2 V < VBST < 26 V; VEN = Float;
CLOAD = 3.3 nF; unless otherwise noted.)
Test Conditions
Min
Typ
Max
Unit
VS Quiescent Current, Operating
VCO = 0 V or 4.5 V; No output switching
−
1.0
2.0
mA
VBST Quiescent Current, Operating
VCO = 0 V or 4.5 V; No output switching
−
3.8
5.0
mA
Start Threshold
VCO = 0 V
7.0
8.0
9.2
V
Stop Threshold
VCO = 0 V
6.0
7.0
8.0
V
Hysteresis
VCO = 0 V
0.70
1.00
1.60
V
High Threshold
−
2.0
−
−
V
Low Threshold
−
−
−
0.8
V
0 < VCO < 5.0 V
−
0
1.0
A
High Threshold
Both outputs respond to CO
2.0
−
−
V
Low Threshold
Both outputs are low independent of CO
−
−
0.8
V
0 < VEN < 5.0 V
−7.0
−3.0
+2.0
A
Overtemperature Trip Point
Note 4
150
170
−
°C
Hysteresis
Note 4
−
20
−
°C
Note 4
−
2.0
−
A
Output Resistance (Sourcing)
Duty Cycle < 2.0%, Pulse Width < 100 s,
TJ = 125°C, VBST − VDRN = 12 V, VTG = 10 V + VDRN
−
1.0
−
Output Resistance (Sinking)
Duty Cycle < 2.0%, Pulse Width < 100 s,
TJ = 125°C, VBST − VDRN = 12 V, VTG = 2.0 V + VDRN
−
1.0
−
Note 4
−
2.0
−
A
Output Resistance (Sourcing)
Duty Cycle < 2.0%, Pulse Width < 100 s,
TJ = 125°C, VS = 12 V, VBG = 10 V
−
1.1
−
Output Resistance (Sinking)
Duty Cycle < 2.0%, Pulse Width < 100 s,
TJ = 125°C, VS = 12 V, VBG = 2.0 V
−
1.0
−
ID = 100 mA
−
1.1
1.4
V
Parameter
DC OPERATING SPECIFICATIONS POWER SUPPLY
UNDERVOLTAGE LOCKOUT
CO INPUT CHARACTERISTICS
Input Bias Current
EN INPUT CHARACTERISTICS
Input Bias Current
THERMAL SHUTDOWN
HIGH−SIDE DRIVER
Peak Output Current
LOW−SIDE DRIVER
Peak Output Current
CHARGE PUMP DIODE
Forward Voltage Drop
3. All limits at temperature extremes are guaranteed by characterization using Standard Statistical Quality Control methods.
4. Guaranteed by design, not 100% tested in production.
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4
NCP5355
ELECTRICAL CHARACTERISTICS (Note 5) (0°C < TJ < 125°C; 9.2 V < VS <13.2 V; 9.2 V < VBST < 26 V; VEN = Float;
CLOAD = 3.3 nF; unless otherwise noted.)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
AC OPERATING SPECIFICATIONS HIGH−SIDE DRIVER
Rise Time
trTG
VBST − VDRN = 12 V, VS = 12 V (Note 6)
−
15
25
ns
Fall Time
tfTG
VBST − VDRN = 12 V, VS = 12 V (Note 6)
−
15
25
ns
Propagation Delay Time,
TG Going High (Nonoverlap
Time)
tpdhTG
VBST − VDRN = 12 V, VS = 12 V (Note 6)
15
30
55
ns
Propagation Delay Time,
TG Going Low
tpdlTG
VBST − VDRN = 12 V, VS = 12 V (Note 6)
−
45
60
ns
Rise Time
trBG
(Note 6)
−
10
20
ns
Fall Time
tfBG
(Note 6)
−
10
20
ns
Propagation Delay Time,
BG Going High (Nonoverlap
Time)
tpdhBG
(Note 6)
15
30
55
ns
Propagation Delay Time,
BG Going Low
tpdlBG
(Note 6)
−
35
55
ns
LOW−SIDE DRIVER
5. All limits at temperature extremes are guaranteed by characterization using Standard Statistical Quality Control methods.
6. AC specifications are guaranteed by characterization, not 100% tested in production.
VCO
tpdlTG
tpdlBG
tfTG
VTG−VDRN
trTG
tpdhTG
(Non−overlap)
VBG
trBG
tfBG
tpdhBG
(Non−overlap)
VDRN
5.0 V
Figure 2. Timing Diagram
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5
ATX 12 V
+
12 V
3.3 V
BST
TG
DRN
PGND BG
NCP5355
3
4
5
6
SGND Near
Socket
VFFB
Connection
26
27
28
29
30
25
23
22
21
20
19
6
VS
4
CO
5
EN
8
3
2
1
7
6
VS
4
CO
5
EN
8
3
2
1
7
6
VS
4
CO
5
EN
8
3
2
1
7
BST
TG
DRN
PGND BG
NCP5355
18
17
16
15
14
13
12
VCORE
ILIM 24
ROSC
VCC
GATE1
GATE2
GATE3
GATE4
GND
NCP5314
+
GND
SGND
VDRP
VFB
COMP
CS4N
CS4P
CS3N
CS3P
8
VID2
VID3
VID4
PWRLS
VFFB
SS
PWRGD
DRVON
9
PWRGD
7
VID1
VID0
VID5
ENABLE
CS2N
CS2P
CS1N
CS1P
2
11
3.3 V
1
10
VID2
VID3
VID4
32
VID5
VID0
VID1
31
ENABLE
3
2
1
7
NCP5355
6
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Figure 3. Application Diagram, 12 V to 1.4 V, 60 Amp, Four−Phase Converter
6
VS
4
CO
5
EN
8
BST
TG
DRN
PGND BG
NCP5355
NTC Near Inductor
BST
TG
DRN
PGND BG
NCP5355
NCP5355
APPLICATIONS INFORMATION
Enable Pin
Supply Capacitor Selection
The Enable pin allows logic level On/Off control of the
NCP5355. A Logic Level Low (< 0.8 V) disables the part by
forcing both TG and BG low. Bringing both gates low prevents
the output voltage from ringing below ground at turn−off. A
Logic Level High (> 2.0 V) enables the part by allowing CO to
control TG and BG.
If the Enable function is not being used, the Enable pin should
be left unconnected. This will Enable the part by default, as the
Enable pin will be internally pulled high by a 2.0A current.
The maximum high voltage level is 5.0 V. Voltages greater than
this may damage the part.
A 1.0 F ceramic capacitor (CVS in Figure 4) should be
located close to the Vs supply pins to provide peak current and
to reduce noise. A small 1.0 to 5.0 resistor (RVS in
Figure 4) may also be added in series with CVS to provide
additional filtering in noisy environments.
Undervoltage Lockout
is the sum of the Top MOSFETs total gate
charge,
VBST
is the maximum change in voltage across
the bootstrap capacitor and is typically
designed for a drop of less than a 1.0 V.
For example, a circuit using one Top MOSFET with a typical
QTtopFETs of 60 nC (at 12 V Vgs) and 1.0 V of droop would give
a minimum value for CBST of 60 nF.
Bootstrap Capacitor Selection
The size of the Top MOSFET bootstrap capacitor (CBST in
Figure 4 ) is determined from the following equation:
CBST QTtopFETs
VBST
where
QTtopFETs
Gates TG and BG are both held low until Vs reaches the
UVLO Start Threshold of 8.0 V during startup. Vs exceeding the
UVLO threshold allows CO to take control of both gates. If Vs
falls below the UVLO Stop Threshold of 7.0 V, both gates are
then forced low until Vs again exceeds the Start Threshold.
VIN = 12 V
DBST
(Optional)
CBST
1.0 RVS
2.2
4
CO
5
EN
6
VS
CO
BST
TG
DRN
PGND
BG
U1
NCP5355
CVS
1.0 3
2
1
8
7
Switch Node
Qtop
NTD60N03
RGU
2.2
VCORE = 1.40 V
CSN
4700 p
Qbottom1
NTD80N02
+
CIN
4.7 Qbottom2
NTD80N02
LOUT
COUT
RSN
2.2
Figure 4. Typical NCP5355 Application
86
85
84
Internal Diode
External Diode
83
82
Efficiency (%)
81
80
Internal Diode
External Diode
79
78
77
200 kHz, Series 2
400 kHz, Series 4
600 kHz, Series 8
External Diode
Internal Diode
76
75
74
73
10
15
20
25
IO (A)
Figure 5. Efficiency With and Without an Added External Bootstrap Diode, See Figure 4 for Test Circuit
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7
NCP5355
Internal or External Bootstrap Diode
Safe design practice requires limiting the SO8 device power
dissipation to around 700 mW. Higher frequency designs may
require limiting the supply voltage (Vs) to less than 12 V to
maintain this limit.
For convenience, a bootstrap diode is internally provided by
the NCP5355. This internal diode reduces system cost and
parts count.
However, this diode will have higher losses than a standard
small signal switching or Schottky diode. By using an external
Schottky diode (DBST in Figure 4) a small improvement in
efficiency can be achieved as illustrated by the graph in
Figure 5.
While the difference in efficiency is relatively small, this
difference represents heat loss in the driver and on average
driver temperature may be reduced by about 10°C if using an
external diode. If an external diode is used, it should be a
Schottky
or
switching
diode.
(For
example:
ON Semiconductor Part Number BAT54HT1 or BAS16HT1.)
Switch Node Overshoot and Ringing
Due to the high current sourcing capability of the
NCP5355, increased overshoot and ringing may be noticed
at the switch node (DRN pin). This can be reduced in several
ways.
One is by adding a low ESR 1.0 F−10 F ceramic
capacitor (CIN in Figure 4) from VIN to ground near each
Qtop. This capacitor should be located in such a manner as
to reduce the loop area of the switch node as shown in
Figure 6. A smaller loop area from CIN+ to Qtop to Qbottom
and back to CIN− will reduce the amount of ringing by
reducing the PCB inductance. If further reduction in
overshoot and ringing is desired, a Top MOSFET gate drive
resistor may be added (RGU in Figure 4) to slow the turn−on
of the Top MOSFET without increasing the turn−off time.
Adaptive Nonoverlap
The NCP5355 includes adaptive nonoverlap protection to
prevent top and bottom MOSFET cross conduction.
When CO goes low signaling TG to turn off the top
MOSFET, BG does not go high until the switch node
(DRN pin) has fallen below 5.0 V and a fixed amount of delay
(tpdhBG) has elapsed. This ensures that the top MOSFET is off
before the bottom MOSFET is turned on.
When CO goes high signaling BG turn off the Bottom
MOSFET, TG does not go high until BG has fallen below a
threshold of 5.0 V and a fixed amount of time has elapsed
(tpdhTG).
However, caution must be observed if too much gate
resistance and inductance is introduced into the path between
the IC and the gate of the low MOSFET. A condition can occur
where the NCP5355 will sense that BG has fallen below 5.0 V
while the gate end of the MOSFET still has not fallen low
enough to turn off the device. This parasitic gate impedance
between the driver and MOSFET can reduce the nonoverlap
time, and result in shoot−through currents.
Layout Guidelines
When designing any switching regulator, the layout is
very important for proper operation. Gate drivers experience
high di/dt during switching, and the inductance of the gate
drive traces need to be minimized. Gate drive traces should
be kept as short and wide (25 to 30 mils) as practical, and
should have a return path directly below the gate trace. The
use of a ground plane is a desirable way to return ground
signals. Component location is very important. The boost
and the Vs capacitor are the most critical, and need to be
placed as close as possible to the driver IC pins (CVS and
CBST in Figure 4) as shown in Figure 6. Higher frequency
designs will magnify any layout problems, and added
attention to these guidelines should be observed in designs
above 250 kHz.
Power Dissipation
Driver power dissipation may be approximated by the
following equation:
Ploss fSW Vs (1.5 QTtopFETs QTbottomFETs)
Vs Is
QTOP
CIN
where
fSW
Vs
QTtopFETs
is the switching frequency,
is the supply voltage,
is the sum of the Top MOSFETs total
gate charge,
QTbottomFETs is the sum of the Bottom MOSFETs total
gate charge
Is
is the supply quiescent current, typically
around 5.0 mA
The 1.5 factor is a result of the internal bootstrap diode
whose loss is equivalent to the charge lost in turning on the Top
MOSFET. If an external diode is used to improve efficiency,
the 1.5 factor is replaced with 1.0 as this loss will now occur
outside the package.
CVS
RVS
DBST
U1
RGU
QBOTTOM
CBST
Figure 6. Typical NCP5355 PCB Layout
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8
NCP5355
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AD
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
−Y−
G
C
N
X 45 DIM
A
B
C
D
G
H
J
K
M
N
S
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 8 0.010
0.020
0.228
0.244
NCP5355
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC−01
ISSUE O
2X
0.10 C A−B
D
D
A
8
EXPOSED
PAD
5
ÉÉÉ
ÉÉÉ
ÉÉÉ
E1
2X
0.10 C D
PIN ONE LOCATION
DETAIL A
F
5
8
G
E
2X
1
0.20 C
4
e
4
h
1
BOTTOM VIEW
b
0.25 C A−B D
8X
B
A
END VIEW
TOP VIEW
0.10 C
A2
8X
(b)
A
0.10 C
c
SEATING
PLANE
SIDE VIEW
ÇÇÇ
ÉÉÉ
ÉÉÉ
c1
DIM
A
A1
A2
b
b1
c
c1
D
E
E1
e
L
L1
F
G
h
MILLIMETERS
MIN
MAX
1.35
1.75
0.00
0.10
1.35
1.65
0.31
0.51
0.28
0.48
0.17
0.25
0.17
0.23
4.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
0.40
1.27
1.04 REF
2.24
3.20
1.55
2.51
0.25
0.50
0
8
b1
A1
C
A
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS (ANGLES
IN DEGREES).
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
SECTION A−A
H
GAUGE
PLANE
0.25
L
(L1)
DETAIL A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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10
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