Dual Bootstrapped 12 V MOSFET Driver

Dual Bootstrapped 12 V
MOSFET Driver with Output Disable
ADP3118
FEATURES
GENERAL DESCRIPTION
Optimized for low gate charge MOSFETs
All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable control turns off both MOSFETs to float
output per Intel VRM 10
Meets CPU VR requirement when used with
Analog Devices, Inc. Flex-Mode1 controller
The ADP3118 is a dual, high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, which are the two switches
in a nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 25 ns propagation delay and a 25 ns transition time. One of the drivers can
be bootstrapped and is designed to handle the high voltage slew
rate associated with floating high-side gate drivers. The ADP3118
includes overlapping drive protection to prevent shoot-through
current in the external MOSFETs.
APPLICATIONS
The OD pin shuts off both the high-side and the low-side
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.
Multiphase desktop CPU supplies
Single-supply synchronous buck converters
The ADP3118 is specified over the commercial temperature
range of 0°C to 85°C and is available in 8-lead SOIC and 8-lead
LFCSP packages.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
VIN 12V
VCC
ADP3118
D1
4
1
BST
CBST2
CBST1
IN 2
8
DRVH
DELAY
RBST
7
OD 3
DELAY
TO
INDUCTOR
SW
VCC
6
CMP
CONTROL
LOGIC
Q1
5
6
DRVL
Q2
PGND
05452-001
CMP
1V
RG
Figure 1.
1
Flex-Mode™ is protected by U.S. Patent 6683441.
©2008 SCILLC. All rights reserved.
January 2008 – Rev. 2
Publication Order Number:
ADP3118/D
ADP3118
TABLE OF CONTENTS
Features...............................................................................................1
Low-Side Driver ............................................................................ 9
Applications .......................................................................................1
High-Side Driver........................................................................... 9
General Description..........................................................................1
Overlap Protection Circuit .......................................................... 9
Simplified Functional Block Diagram............................................1
Application Information ................................................................10
Revision History................................................................................2
Supply Capacitor Selection........................................................10
Specifications .....................................................................................3
Bootstrap Circuit ........................................................................10
Absolute Maximum Ratings ............................................................4
MOSFET Selection .....................................................................10
ESD Caution ..................................................................................4
High-Side (Control) MOSFETs ................................................10
Pin Configuration and Function Descriptions .............................5
Low-Side (Synchronous) MOSFETs.........................................11
Timing Characteristics .....................................................................6
PC Board Layout Considerations .............................................11
Typical Performance Characteristics..............................................7
Outline Dimensions........................................................................13
Theory of Operation.........................................................................9
Ordering Guide ...........................................................................13
REVISION HISTORY
01/08 - Rev 2: Conversion to ON Semiconductor
9/07—Rev. 0 to Rev. A
Added LFCSP...................................................................... Universal
Updated Outline Dimensions........................................................13
Changes to Ordering Guide...........................................................13
4/05—Revision 0: Initial Version
Rev. 2 | Page 2 of 14 | www.onsemi.com
ADP3118
SPECIFICATIONS
VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted.1
Table 1.
Parameter
PWM INPUT
Input Voltage High
Input Voltage Low
Input Current
Hysteresis
OD INPUT
Input Voltage High
Input Voltage Low
Input Current
Hysteresis
Propagation Delay Times2
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
Propagation Delay Times2
SW Pull-Down Resistance
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
Propagation Delay Times2
Symbol
1
2
Min
Typ
Max
Unit
0.8
+1
V
V
μA
mV
2.0
−1
90
250
2.0
tpdlOD
See Figure 3
250
20
35
V
V
μA
mV
ns
tpdhOD
See Figure 3
40
55
ns
BST − SW = 12 V
BST − SW = 12 V
BST − SW = 0 V
BST − SW = 12 V, CLOAD = 3 nF, see Figure 4
BST − SW = 12 V, CLOAD = 3 nF, see Figure 4
BST − SW = 12 V, CLOAD = 3 nF, see Figure 4
BST − SW = 12 V, CLOAD = 3 nF, see Figure 4
SW to PGND
2.2
1.0
10
25
20
25
25
10
3.5
2.5
Ω
Ω
kΩ
ns
ns
ns
ns
kΩ
3.2
2.5
VCC = PGND
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
SW = 5 V
SW = PGND
2.0
1.0
10
20
16
12
30
190
150
−1
90
trDRVH
tfDRVH
tpdhDRVH
tpdlDRVH
trDRVL
tfDRVL
tpdhDRVL
tpdlDRVL
Timeout Delay
SUPPLY
Supply Voltage Range
Supply Current
UVLO Voltage
Hysteresis
Conditions
VCC
ISYS
110
95
0.8
+1
4.15
BST = 12 V, IN = 0 V
VCC rising
2
1.5
350
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low.
Rev. 2 | Page 3 of 14 | www.onsemi.com
40
30
40
35
35
30
35
45
13.2
5
3.0
Ω
Ω
kΩ
ns
ns
ns
ns
ns
ns
V
mA
V
mV
ADP3118
ABSOLUTE MAXIMUM RATINGS
Unless otherwise specified, all voltages are referenced to PGND.
Table 2.
Parameter
VCC
BST
BST to SW
SW
DC
<200 ns
DRVH
DC
<200 ns
DRVL
DC
<200 ns
IN, OD
θJA, SOIC
2-Layer Board
4-Layer Board
θJA, LFCSP_VD1
4-Layer Board
Operating Ambient Temperature
Range
Junction Temperature Range
Storage Temperature Range
Lead Temperature Range
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
1
Rating
−0.3 V to +15 V
−0.3 V to VCC + 15 V
−0.3 V to +15 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−5 V to +15 V
−10 V to +25 V
SW − 0.3 V to BST + 0.3 V
SW − 2 V to BST + 0.3 V
−0.3 V to VCC + 0.3 V
−2 V to VCC + 0.3 V
−0.3 V to 6.5 V
123°C/W
90°C/W
50°C/W
0°C to 85°C
0°C to 150°C
−65°C to +150°C
300°C
215°C
260°C
For LFCSP_VD, θJA is measured per JEDEC STD with the exposed pad
soldered to PCB.
Rev. 2 | Page 4 of 14 | www.onsemi.com
ADP3118
BST 1
IN 2
OD 3
ADP3118
8
DRVH
7
SW
6 PGND
TOP VIEW
VCC 4 (Not to Scale) 5 DRVL
05452-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. 8-Lead SOIC Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
BST
2
IN
3
OD
4
5
6
7
VCC
DRVL
PGND
SW
8
DRVH
Description
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched.
Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this
pin low turns on the low-side driver; pulling it high turns on the high-side driver.
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Input Supply. This pin should be bypassed to PGND with an ~1 μF ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating return
for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of the
lower MOSFET until the voltage is below ~1 V.
Buck Drive. Output drive for the upper (buck) MOSFET.
Rev. 2 | Page 5 of 14 | www.onsemi.com
ADP3118
TIMING CHARACTERISTICS
OD
tpdlOD
tpdhOD
05452-004
90%
DRVH
OR
DRVL
10%
Figure 3. Output Disable Timing Diagram
IN
tpdlDRVL
tfDRVL
tpdlDRVH
trDRVL
DRVL
tfDRVH
tpdhDRVH
DRVH – SW
trDRVH
VTH
VTH
1V
Figure 4. Timing Diagram—Timing Is Referenced to the 90% and 10% Points, Unless Otherwise Noted
Rev. 2 | Page 6 of 14 | www.onsemi.com
05452-005
tpdhDRVL
SW
ADP3118
TYPICAL PERFORMANCE CHARACTERISTICS
24
VCC = 12V
CLOAD = 3nF
IN
DRVH
FALL TIME (ns)
22
DRVL
20
18
DRVL
05452-006
14
05452-009
16
DRVH
0
25
50
75
100
125
JUNCTION TEMPERATURE (°C)
Figure 5. DRVH Rise and DRVL Fall Times
CLOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH
Figure 8. DRVH and DRVL Fall Times vs. Temperature
40
35
IN
TA = 25°C
VCC = 12V
DRVH
RISE TIME (ns)
30
DRVL
25
DRVL
20
15
5
2.0
05452-010
10
05452-007
DRVH
2.5
3.0
3.5
4.0
4.5
5.0
LOAD CAPACITANCE (nF)
Figure 6. DRVH Fall and DRVL Rise Times
CLOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH
Figure 9. DRVH and DRVL Rise Times vs. Load Capacitance
35
35
VCC = 12V
TA = 25°C
VCC = 12V
CLOAD = 3nF
30
FALL TIME (ns)
DRVH
25
DRVL
DRVH
25
DRVL
20
15
20
15
0
25
50
75
125
100
5
2.0
JUNCTION TEMPERATURE (°C)
05452-011
10
05452-008
RISE TIME (ns)
30
2.5
3.0
3.5
4.0
4.5
LOAD CAPACITANCE (nF)
Figure 7. DRVH and DRVL Rise Times vs. Temperature
Figure 10. DRVH and DRVL Fall Times vs. Load Capacitance
Rev. 2 | Page 7 of 14 | www.onsemi.com
5.0
ADP3118
12
60
TA = 25°C
CLOAD = 3nF
11
10
DRVL OUTPUT VOLTAGE (V)
SUPPLY CURRENT, ICC (mA)
TA= 25°C
VCC = 12V
CLOAD = 3nF
45
30
15
9
8
7
6
5
4
3
0
200
400
600
800
1000
1200
1400
05452-014
0
05452-012
2
1
0
0
1
Figure 11. Supply Current vs. Frequency
12
11
10
05452-013
SUPPLY CURRENT, ICC (mA)
VCC = 12V
CLOAD = 3nF
fIN = 250kHz
0
25
50
75
3
4
5
6
7
8
9
10
Figure 13. DRVL Output Voltage vs. Supply Voltage
13
9
2
VCC VOLTAGE (V)
FREQUENCY (kHz)
100
125
JUNCTION TEMPERATURE (°C)
Figure 12. Supply Current vs. Temperature
Rev. 2 | Page 8 of 14 | www.onsemi.com
11
12
ADP3118
THEORY OF OPERATION
The ADP3118 is a dual-MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side MOSFETs. Each
driver is capable of driving a 3 nF load at speeds up to 500 kHz.
A more detailed description of the ADP3118 and its features
follows (see Figure 1 for a block diagram).
LOW-SIDE DRIVER
The low-side driver is designed to drive a ground-referenced
N-channel MOSFET. The bias to the low-side driver is internally connected to the VCC supply and PGND.
When the driver is enabled, the driver’s output is 180° out of
phase with the PWM input. When the ADP3118 is disabled,
the low-side gate is held low.
HIGH-SIDE DRIVER
The high-side driver is designed to drive a floating N-channel
MOSFET. The bias voltage for the high-side driver is developed
by an external bootstrap supply circuit, which is connected
between the BST and SW pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, CBST1. CBST2 and RBST are included to reduce the
high-side gate drive voltage and to limit the switch node slew
rate (referred to as a Boot-Snap circuit, see the Application
Information section for more details). When the ADP3118 is
starting up, the SW pin is at ground, so the bootstrap capacitor
charges up to VCC through D1. When the PWM input goes
high, the high-side driver begins to turn on the high-side
MOSFET, Q1, by pulling charge out of CBST1 and CBST2. As Q1
turns on, the SW pin rises up to VIN, forcing the BST pin to VIN
+ VC (BST), which is enough gate-to-source voltage to hold Q1 on.
To complete the cycle, Q1 is switched off by pulling the gate
down to the voltage at the SW pin. When the low-side MOSFET,
Q2, turns on, the SW pin is pulled to ground. This allows the
bootstrap capacitor to charge up to VCC again.
The high-side driver’s output is in phase with the PWM input.
When the driver is disabled, the high-side gate is held low.
OVERLAP PROTECTION CIRCUIT
The overlap protection circuit prevents both of the main power
switches, Q1 and Q2, from being on at the same time. This is
done to prevent shoot-through currents from flowing through
both power switches and the associated losses that can occur
during their on/off transitions. The overlap protection circuit
accomplishes this by adaptively controlling the delay from the
Q1 turn-off to the Q2 turn-on, and by internally setting the
delay from the Q2 turn-off to the Q1 turn-on.
To prevent the overlap of the gate drives during the Q1 turn-off
and the Q2 turn-on, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 begins
to turn off (after propagation delay). Before Q2 can turn on,
the overlap protection circuit makes sure that SW has first
gone high and then waits for the voltage at the SW pin to fall
from VIN to 1 V. Once the voltage on the SW pin falls to 1 V,
Q2 begins turn-on. If the SW pin has not gone high first, the
Q2 turn-on is delayed by a fixed 150 ns. By waiting for the
voltage on the SW pin to reach 1 V or for the fixed delay time,
the overlap protection circuit ensures that Q1 is off before Q2
turns on, regardless of variations in temperature, supply voltage,
input pulse width, gate charge, and drive current. If SW does
not go below 1 V after 190 ns, DRVL turns on. This can occur
if the current flowing in the output inductor is negative and is
flowing through the high-side MOSFET body diode.
Rev. 2 | Page 9 of 14 | www.onsemi.com
ADP3118
APPLICATION INFORMATION
SUPPLY CAPACITOR SELECTION
For the supply input (VCC) of the ADP3118, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 4.7 μF, low ESR capacitor. Multilayer ceramic chip capacitors (MLCC) provide the
best combination of low ESR and small size. Keep the ceramic
capacitor as close as possible to the ADP3118.
BOOTSTRAP CIRCUIT
C BST1 + C BST2
=
VGATE
VCC − VD
IF(AVG) = QGATE × fMAX
(3)
where fMAX is the maximum switching frequency of the controller.
The peak surge current rating should be calculated using
The bootstrap circuit uses a charge storage capacitor (CBST)
and a diode, as shown in Figure 1. These components can be
selected after the high-side MOSFET is chosen. The bootstrap
capacitor must have a voltage rating that can handle twice the
maximum supply voltage. A minimum 50 V rating is recommended. The capacitor values are determined by:
Q
C BST1 + C BST2 = 10 × GATE
(1)
VGATE
C BST1
A small-signal diode can be used for the bootstrap diode due
to the ample gate drive voltage supplied by VCC. The bootstrap
diode must have a minimum 15 V rating to withstand the
maximum supply voltage. The average forward current can
be estimated by
(2)
I F ( PEAK ) =
VCC − V D
R BST
(4)
MOSFET SELECTION
When interfacing the ADP3118 to external MOSFETs, there
are a few considerations that the designer should be aware of.
These help to make a more robust design that minimizes
stresses on both the driver and the MOSFETs. These stresses
include exceeding the short-time duration voltage ratings on
the driver pins as well as the external MOSFET.
where:
QGATE is the total gate charge of the high-side MOSFET at VGATE.
VGATE is the desired gate drive voltage (usually in the range of 5 V
to 10 V, 7 V being typical).
VD is the voltage drop across D1.
It is also highly recommended to use a Boot-Snap circuit to
improve the interaction of the driver with the characteristics of
the MOSFETs. If a simple bootstrap arrangement is used, make
sure to include a proper snubber network on the SW node.
Rearranging Equation 1 and Equation 2 to solve for CBST1 yields
The high-side MOSFET is usually selected to be high speed to
minimize switching losses (see the ADP3186 or ADP3188 data
sheet for controller details). This usually implies a low gate resistance and low input capacitance/charge device. Yet, a significant
source lead inductance can also exist. This depends mainly on
the MOSFET package; it is best to contact the MOSFET vendor
for this information.
C BST1 = 10 ×
Q GATE
VCC − V D
CBST2 can then be found by rearranging Equation 1.
C BST2 = 10 ×
Q GATE
VGATE
− C BST1
For example, an NTD60N02 has a total gate charge of about
12 nC at VGATE = 7 V. Using VCC = 12 V and VD = 1 V, one finds
CBST1 = 12 nF and CBST2 = 6.8 nF. Good quality ceramic capacitors
should be used.
RBST is used for slew-rate limiting to minimize the ringing at the
switch node. It also provides peak current limiting through D1.
An RBST value of 1.5 Ω to 2.2 Ω is a good choice. The resistor
needs to be able to handle at least 250 mW due to the peak
currents that flow through it.
HIGH-SIDE (CONTROL) MOSFETS
The ADP3118 DRVH output impedance and the input resistance
of the MOSFETs determine the rate of charge delivery to the
gate’s internal capacitance. This determines the speed at which
the MOSFETs turn on and off. However, due to potentially large
currents flowing in the MOSFETs at the on and off times (this
current is usually larger at turn off due to ramping up of the output current in the output inductor), the source lead inductance
generates a significant voltage when the high-side MOSFETs
switch off. This creates a significant drain-source voltage spike
across the internal die of the MOSFETs and can lead to a catastrophic avalanche. The mechanisms involved in this avalanche
condition can be referenced in literature from the MOSFET
suppliers.
Rev. 2 | Page 10 of 14 | www.onsemi.com
ADP3118
I MAX = I DC ( per phase ) + (VCC − VOUT ) ×
D MAX
f MAX × L OUT
(5)
where:
DMAX is determined for the VR controller being used with the
driver. This current is divided as equally as possible between
MOSFETs if more than one is used (assume a worst-case
mismatch of 30% for design margin).
LOUT is the output inductor value.
When producing a design, there is no exact method for calculating the dV/dt due to the parasitic effects in the external
MOSFETs as well as the PCB. However, it can be measured
to determine if it is safe. If it appears that the dV/dt is too fast,
an optional gate resistor can be added between DRVH and the
high-side MOSFETs. This resistor slows down the dV/dt, but it
increases the switching losses in the high-side MOSFETs. The
ADP3118 has been optimally designed with an internal drive
impedance that works with most MOSFETs to switch them
efficiently yet minimizes dV/dt. However, some high speed
MOSFETs may require this external gate resistor depending
on the currents being switched in the MOSFET.
LOW-SIDE (SYNCHRONOUS) MOSFETS
The low-side MOSFETs are usually selected to have a low on
resistance to minimize conduction losses. This usually implies
a large input gate capacitance and gate charge. The first concern
is to make sure the power delivery from the ADP3118’s DRVL
does not exceed the thermal rating of the driver (see the ADP3186
or ADP3188 data sheet for controller details).
the proper switching time, so the state of the DRVL pin is
monitored to go below one sixth of VCC. A delay is then added.
Due to the Miller capacitance and internal delays of the lowside MOSFET gate, one must ensure that the Miller-to-input
capacitance ratio is low enough and that the low-side MOSFET
internal delays are not so large as to allow accidental turn on of
the low-side when the high-side turns on.
Contact sales for an updated list of recommended low-side
MOSFETs.
PC BOARD LAYOUT CONSIDERATIONS
Use the following general guidelines when designing printed
circuit boards.
•
Trace out the high current paths and use short, wide
(>20 mil) traces to make these connections.
•
Minimize trace inductance between DRVH and DRVL
outputs and MOSFET gates.
•
Connect the PGND pin of the ADP3118 as closely as
possible to the source of the lower MOSFET.
•
Locate the VCC bypass capacitor as close as possible to the
VCC and PGND pins.
•
Use vias to other layers when possible to maximize thermal
conduction away from the IC.
The circuit in Figure 15 shows how four drivers can be combined with the ADP3188 to form a total power conversion
solution for generating VCC (CORE) for an Intel® CPU that is VRD
10.x-compliant.
Figure 14 shows an example of the typical land patterns based
on the guidelines given previously. For more detailed layout
guidelines for a complete CPU voltage regulator subsystem,
refer to the Layout and Component Placement section of the
ADP3188 data sheet.
The next concern for the low-side MOSFETs is based on
preventing them from inadvertently being switched on when
the high-side MOSFET turns on. This occurs due to the draingate (Miller, also specified as Crss) capacitance of the MOSFET.
When the drain of the low-side MOSFET is switched to VCC by
the high-side turning on (at a rate of dV/dt), the internal gate of
the low-side MOSFET is pulled up by an amount roughly equal
to VCC × (Crss/Ciss). It is important to make sure this does not put
the MOSFET into conduction.
CBST1
CBST2
D1
Another consideration is the nonoverlap circuitry of the ADP3118,
which attempts to minimize the nonoverlap period. During the
state of the high-side turning off to low-side turning on, the SW
pin is monitored (as well as the conditions of SW prior to
switching) to adequately prevent overlap.
However, during the low-side turn off to high-side turn on,
the SW pin does not contain information for determining
RBST
CVCC
05452-015
The MOSFET vendor should provide a maximum voltage
slew rate at a drain current rating such that this can be designed
around. Once the designer has this specification, determine the
maximum current you expect to see in the MOSFET. This can
be done with the following equation:
Figure 14. External Component Placement Example
Rev. 2 | Page 11 of 14 | www.onsemi.com
Rev. 2 | Page 12 of 14 | www.onsemi.com
Figure 15. VRD 10-Compliant Power Supply Circuit
05452-016
ENABLE
POWER
GOOD
C211
1nF
FROM
CPU
VIN RTN
VIN
12V
C4
1μF
D1
1N4148
+
C2
RLDY
470kΩ
RT
137kΩ,
1%
22pF
CFB
R1
10Ω
PWM2 26
PWM3 25
PWM4 24
SW1 23
SW2 22
SW3 21
SW4 20
GND 19
VID2
VID1
VID0
VID5
FBRTN
FB
COMP
3
4
5
6
7
8
9
10 PWRGD
CSREF 16
13 RT
C23
1nF
14 RAMPADJ ILIMIT 15
CSSUM 17
12 DELAY
CSCOMP 18
PWM1 27
VID3
2
11 EN
VCC 28
VID4
U1
ADP3188
1
R2
357kΩ,
1%
RLIM
150kΩ,
1%
C22
1nF
CCS2
1.5nF
CCS1
560pF
RSW41
RSW21
RCS2
35.7kΩ 84.5kΩ
RCS1
RPH4
158kΩ, 1%
RSW31
RSW1
1
RPH2
RPH3 158kΩ,
RPH1
1% 158kΩ,
158kΩ,
1%
1%
NOTE:
1. FOR A DESCRIPTION OF OPTIONAL COMPONENTS, SEE THE ADP3188 THEORY OF OPERATION SECTION.
CLDY
39nF
CA
RB
RA
1.21kΩ 470pF 12.1kΩ
470pF
CB
+
+
C1
2700μF/16V/3.3A × 2
SANYO MV-WX SERIES
C3
100μF
L1
370nH
18A
C17
4.7μF
D5
1N4148
C13
4.7μF
D4
1N4148
C9
4.7μF
D3
1N4148
C5
4.7μF
D2
1N4148
DRVL 5
C12
12nF
VCC
R4
2.2Ω
4
C16
12nF
VCC
R5
2.2Ω
4
DRVL 5
VCC
C16
6.8nF
PGND
DRVL 5
IN
OD
VCC
3
4
6
SW 7
BST
2
DRVH 8
U5
ADP3118
C20
12nF
PGND 6
OD
R6
2.2Ω
SW 7
DRVH 8
IN
BST
1
4
3
2
1
DRVL 5
OD
3
C14
6.8nF
PGND 6
IN
2
U4
ADP3118
SW 7
BST
1
DRVH 8
C10
6.8nF
PGND 6
OD
3
U3
ADP3118
SW 7
IN
2
DRVH 8
BST
1
C6
6.8nF
C8
12nF
U2
ADP3118
R3
2.2Ω
Q15
NTD110N02
Q11
NTD110N02
Q7
NTD110N02
Q3
NTD110N02
Q16
NTD110N02
Q13
NTD60N02
C19
4.7μF
Q12
NTD110N02
Q9
NTD60N02
C15
4.7μF
Q8
NTD110N02
Q5
NTD60N02
C11
4.7μF
Q4
NTD110N02
Q1
NTD60N02
C7
4.7μF
L5
320nH/1.4mΩ
L4
320nH/1.4mΩ
L3
320nH/1.4mΩ
RTH1
100kΩ, 5%
NTC
C24
+
+
10μF × 18
MLCC IN
SOCKET
C31
560μF/4V × 8
L2
320nH/1.4mΩ SANYO SEPC SERIES
5mΩ EACH
VCC (CORE) RTN
VCC (CORE)
0.8375V – 1.6V
95A TDC, 119A PK
ADP3118
ADP3118
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497)
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
012407-A
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 16. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters (inches)
3.25
3.00 SQ
2.75
0.60 MAX
5
2.95
2.75 SQ
2.55
TOP
VIEW
PIN 1
INDICATOR
8
12° MAX
1
1.89
1.74
1.59
PIN 1
INDICATOR
0.05 MAX
0.01 NOM
0.30
0.23
0.18
0.20 REF
061507-B
SEATING
PLANE
0.50
0.40
0.30
0.70 MAX
0.65 TYP
1.60
1.45
1.30
EXPOSED
PAD
(BOTTOM VIEW)
4
0.90 MAX
0.85 NOM
0.50
BSC
0.60 MAX
Figure 17. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADP3118JRZ1
ADP3118JRZ-RL1
ADP3118JCPZ-RL1
1
Temperature
Range
0°C to 85°C
0°C to 85°C
0°C to 85°C
Package Description
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Lead Frame Chip Scale Package (LFCSP_VD)
Z = RoHS Compliant Part.
Rev. 2 | Page 13 of 14 | www.onsemi.com
Package
Option
R-8
R-8
CP-8-2
Ordering
Quantity
98
2,500
2,500
ADP3118
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
ON Semiconductor and
products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”
parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or
use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action
Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
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Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81-3-5773-3850
Rev. 2 | Page 14 of 14 | www.onsemi.com
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For additional information, please contact your local
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