Dual Bootstrapped 12V MOSFET Driver with Output Disable

NCP3418, NCP3418A
Dual Bootstrapped 12 V
MOSFET Driver with
Output Disable
The NCP3418 and NCP3418A are dual MOSFET gate drivers
optimized to drive the gates of both high--side and low--side power
MOSFETs in a synchronous buck converter. Each of the drivers is
capable of driving a 3000 pF load with a 25 ns propagation delay and a
20 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal,
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 30 V, with transient voltages as high as 35 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
The NCP3418A is identical to the NCP3418 except that there is no
internal charge pump diode.
The NCP3418 is pin--to--pin compatible with Analog Devices
ADP3418 with the following advantages:
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MARKING
DIAGRAMS
8
SO--8
D SUFFIX
CASE 751
8
1
341x
AYWW
G
1
8
SO--8 EP
PD SUFFIX
CASE 751AC
8
1
341x
ALYW
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Faster Rise and Fall Times
Internal Charge Pump Diode Reduces Cost and Parts Count
Thermal Shutdown for System Protection
Integrated OVP
Internal Pulldown Resistor Suppresses Transient Turn On of Either
MOSFET
Anti Cross--Conduction Protection Circuitry
Floating Top Driver Accommodates Boost Voltages of up to 30 V
One Input Signal Controls Both the Upper and Lower Gate Outputs
Output Disable Control Turns Off Both MOSFETs
Complies with VRM 10.x Specifications
Undervoltage Lockout
Thermally Enhanced Package Available
Pb--Free Packages are Available
341x
= Device Code
x = 8 or 8A
A
= Assembly Location
L
= Wafer Lot
Y
= Year
WW, W = Work Week
G
= Pb--Free Package
PIN CONNECTIONS
BST
1
8
DRVH
IN
OD
SW
PGND
VCC
DRVL
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
April, 2007 -- Rev. 13
1
Publication Order Number:
NCP3418/D
NCP3418, NCP3418A
ORDERING INFORMATION
Package
Shipping†
NCP3418D
SO--8
98 Units / Rail
NCP3418DR2
SO--8
2500 / Tape & Reel
NCP3418DR2G
SO--8
(Pb--Free)
2500 / Tape & Reel
NCP3418ADR2
SO--8
2500 / Tape & Reel
NCP3418ADR2G
SO--8
(Pb--Free)
2500 / Tape & Reel
NCP3418PDR2
SO--8 EP
2500 / Tape & Reel
NCP3418APDR2
SO--8 EP
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
V CC
4
Not present in
the NCP3418A
IN
1
BST
8
DRVH
7
SW
5
DRVL
6
PGND
2
100 k
-+
Nonoverlap
1.5 V
4V
-+
120 k
OD
3
Figure 1. NCP3418/A Block Diagram
PIN DESCRIPTION
Pin
Symbol
Description
1
BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this bootstrap voltage for the high--side MOSFET as it is switched. The recommended capacitor value is between
100 nF and 1.0 mF. An external diode will be needed with the NCP3418A.
2
IN
Logic--Level Input. This pin has primary control of the drive outputs.
3
OD
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
4
VCC
Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.
5
DRVL
Output drive for the lower MOSFET.
6
PGND
Power Ground. Should be closely connected to the source of the lower MOSFET.
7
SW
8
DRVH
Switch Node. Connect to the source of the upper MOSFET.
Output drive for the upper MOSFET.
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2
NCP3418, NCP3418A
MAXIMUM RATINGS
Rating
Value
Unit
Operating Ambient Temperature, TA
0 to 85
°C
Operating Junction Temperature, TJ (Note 1)
0 to 150
°C
Package Thermal Resistance: SO--8
Junction--to--Case, RθJC
Junction--to--Ambient, RθJA (2--Layer Board)
45
123
°C/W
°C/W
Package Thermal Resistance: SO--8 EP
Junction--to--Ambient, RθJA (Note 2)
50
°C/W
--65 to 150
°C
240 peak
260 peak
°C
1
1
1
3
--
Storage Temperature Range, TS
Lead Temperature Soldering (10 sec): Reflow (SMD styles only)
Standard (Note 3)
Lead Free (Note 4)
JEDEC Moisture Sensitivity Level
SO--8 (240 peak profile)
SO--8 (260 peak profile)
SO--8 EP (240 peak profile)
SO--8 EP (260 peak profile)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Internally limited by thermal shutdown, 150°C min.
2. Rating applies when soldered to an appropriate thermal area on the PCB.
3. 60 -- 180 seconds minimum above 183°C.
4. 60 -- 180 seconds minimum above 237°C.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
MAXIMUM RATINGS
Pin Symbol
Pin Name
VMAX
VMIN
VCC
Main Supply Voltage Input
15 V
--0.3 V
BST
Bootstrap Supply Voltage Input
30 V wrt/PGND
35 V ≤ 50 ns wrt/PGND, 15 V wrt/SW
--0.3 V wrt/SW
SW
Switching Node
(Bootstrap Supply Return)
30 V
--1.0 V DC
--10 V< 200 ns
DRVH
High--Side Driver Output
BST + 0.3 V
35 V ≤ 50 ns wrt/PGND, 15 V wrt/SW
--0.3 V wrt/SW
DRVL
Low--Side Driver Output
VCC + 0.3 V
--0.3 V DC
--2.0 V < 200 ns
IN
DRVH and DRVL Control Input
VCC + 0.3 V
--0.3 V
OD
Output Disable
VCC + 0.3 V
--0.3 V
PGND
Ground
0V
0V
NOTE:
All voltages are with respect to PGND except where noted.
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3
NCP3418, NCP3418A
NCP3418--SPECIFICATIONS (Note 5) (VCC = 12 V, TA = 0°C to +85°C, TJ = 0°C to +125°C unless otherwise noted.).
Conditions
Symbol
Min
Typ
Max
Unit
--
VCC
4.6
--
13.2
V
BST = 12 V, IN = 0 V
ISYS
--
2.0
6.0
mA
Input Voltage High
--
--
2.0
--
--
V
Input Voltage Low
--
--
--
--
0.8
V
Input Current
--
--
--1.0
--
+1.0
mA
See Figure 2
tpdlOD
tpdhOD
---
40
40
60
60
ns
ns
Input Voltage High
--
--
2.0
--
--
V
Input Voltage Low
--
--
--
--
0.8
V
Input Current
--
--
--1.0
--
+1.0
mA
--
1.8
3.0
Ω
Parameter
SUPPLY
Supply Voltage Range
Supply Current
OD INPUT
Propagation Delay Time (Note 6)
PWM INPUT
HIGH--SIDE DRIVER
Output Resistance,
Sourcing Current
VBST -- VSW = 12 V (Note 8)
Output Resistance,
Sinking Current
VBST -- VSW = 12 V (Note 8)
--
--
1.0
2.5
Ω
VBST -- VSW = 12 V, CLOAD = 3.0 nF,
See Figure 3
trDRVH
tfDRVH
---
18
10
25
15
ns
ns
VBST -- VSW = 12 V
tpdhDRVH
tpdlDRVH
---
30
25
60
45
ns
ns
Output Resistance,
Sourcing Current
--
VCC = 12 V
(Note 8)
--
1.8
3.0
Ω
Output Resistance,
Sinking Current
--
VCC -- VSW = 12 V
(Note 8)
--
1.0
2.5
Ω
trDRVL
tfDRVL
CLOAD = 3.0 nF,
See Figure 3
---
16
11
25
15
ns
ns
tpdhDRVL
tpdlDRVL
See Figure 3
---
30
20
60
30
ns
ns
--
--
3.9
4.3
4.6
V
(Note 8)
--
Over Temperature Protection
(Note 8)
--
Hysteresis
(Note 8)
Transition Times (Note 6)
Propagation Delay
(Notes 6 & 7)
--
LOW--SIDE DRIVER
Transition Times
Propagation Delay
UNDERVOLTAGE LOCKOUT
UVLO
Hysteresis
0.5
V
170
°C
20
°C
THERMAL SHUTDOWN
5.
6.
7.
8.
150
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
AC specifications are guaranteed by characterization, but not production tested.
For propagation delays, “tpdh’’ refers to the specified signal going high; “tpdl’’ refers to it going low.
GBD: Guaranteed by design; not tested in production. Specifications subject to change without notice.
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4
NCP3418, NCP3418A
OD
tpdlOD
tpdhOD
90%
DRVH
or
DRVL
10%
Figure 2. Output Disable Timing Diagram
IN
tpdlDRVL tfDRVL
DRVL
tpdlDRVH
90%
1.5 V
90%
10%
10%
tpdhDRVH
tfDRVH
trDRVH
90%
DRVH--SW
trDRVL
90%
10%
10%
tpdhDRVL
SW
4V
Figure 3. Nonoverlap Timing Diagram (timing is referenced to the 90% and 10% points unless otherwise noted)
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5
NCP3418, NCP3418A
APPLICATIONS INFORMATION
IN
IN
DRVH
DRVH
DRVL
DRVL
Figure 4. DRVH Rise and DRVL Fall Times
Figure 5. DRVH Fall and DRVL Rise Times
15
40
FALL TIME (ns)
trTG
20
trBG
10
0
1
2
4
3
trBG
5
0
5
trTG
10
1
2
3
Figure 6. Rise Time vs. Load Capacitance
Figure 7. Fall Time vs. Load Capacitance
60
50
40
ICC
30
20
TA = 25 °C
VCC = 12 V
Cload = 3.3 nF
10
0
0
4
LOAD CAPACITANCE (nF)
LOAD CAPACITANCE (nF)
SUPPLY CURRENT (mA)
RISE TIME (ns)
30
200
400
600
800
1000
1200
IN FREQUENCY (kHz)
Figure 8. VCC Supply Current vs. IN Frequency
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6
5
NCP3418, NCP3418A
APPLICATIONS INFORMATION
Theory of Operation
The NCP3418 and NCP3418A are single phase MOSFET
drivers optimized for driving two N--channel MOSFETs in
a synchronous buck converter topology. The NCP3418
features an internal diode, while the NCP3418A requires an
external BST diode for the floating top gate driver. A single
PWM input signal is all that is required to properly drive the
high--side and the low--side MOSFETs. Each driver is
capable of driving a 3.3 nF load at frequencies up to 500 kHz.
threshold, DRVL will go high after a propagation delay
(tpdhDRVL), turning the low--side MOSFET on. However, if
SW does not fall below 4.0 V in 300 ns, the safety timer
circuit will override the normal control scheme and drive
DRVL high. This will help insure that if the high--side
MOSFET fails to turn off it will not produce an over--voltage
at the output.
Similarly, to prevent cross conduction during the low--side
MOSFET’s turn--off and the high--side MOSFET’s turn--on,
the overlap circuit monitors the voltage at the gate of the
low--side MOSFET through the DRVL pin. When the PWM
signal goes high, DRVL will go low after a propagation delay
(tpdlDRVL), turning the low--side MOSFET off. However,
before the high--side MOSFET can turn on, the overlap
protection circuit waits for the voltage at DRVL to drop below
1.5 V. Once this has occurred, DRVH will go high after a
propagation delay (tpdhDRVH), turning the high--side
MOSFET on.
Low--Side Driver
The low--side driver is designed to drive a
ground--referenced low RDS(on) N--Channel MOSFET. The
voltage rail for the low--side driver is internally connected to
the VCC supply and PGND.
When the NCP3418 is enabled, the low--side driver’s
output is 180_ out of phase with the PWM input. When the
device is disabled, the low--side gate is held low.
High--Side Driver
Application Information
The high--side driver is designed to drive a floating low
RDS(on) N--channel MOSFET. The bias voltage for the high
side driver is developed by a bootstrap circuit referenced to
SW. The bootstrap capacitor should be connected between
the BST and SW pins.
The bootstrap circuit comprises an internal or external
diode, D1 (in which the anode is connected to VCC), and an
external bootstrap capacitor, CBST. When the NCP3418 is
starting up, the SW pin is at ground, so the bootstrap capacitor
will charge up to VCC through D1. When the PWM input goes
high, the high--side driver will begin to turn on the high--side
MOSFET by pulling charge out of CBST. As the high--side
MOSFET turns on, the SW pin will rise to VIN, forcing the
BST pin to VIN + VCC, which is enough gate--to--source
voltage to hold the MOSFET on. To complete the cycle, the
high--side MOSFET is switched off by pulling the gate down
to the voltage at the SW pin. When low--side MOSFET turns
on, the SW pin is held at ground. This allows the bootstrap
capacitor to charge up to VCC again.
The high--side driver’s output is in phase with the PWM input.
When the device is disabled, the high side gate is held low.
Supply Capacitor Selection
For the supply input (VCC) of the NCP3418, a local bypass
capacitor is recommended to reduce noise and supply peak
currents during operation. Use a 1.0 to 4.7 mF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors
provide the best combination of low ESR and small size.
Keep the ceramic capacitor as close as possible to the VCC
and PGND pins.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBST) and the internal (or an external) diode. Selection of
these components can be done after the high--side MOSFET
has been chosen.
The bootstrap capacitor must have a voltage rating that is
able to withstand twice the maximum supply voltage. A
minimum 50 V rating is recommended. The capacitance is
determined using the following equation:
CBST =
QGATE
ΔVBST
(eq. 1)
where QGATE is the total gate charge of the high--side
MOSFET, and ΔVBST is the voltage droop allowed on the
high--side MOSFET drive. For example, a NTD60N03 has
a total gate charge of about 30 nC. For an allowed droop of
300 mV, the required bootstrap capacitance is 100 nF. A
good quality ceramic capacitor should be used.
If an external Schottky diode will be used for bootstrap,
it must be rated to withstand the maximum supply voltage
plus any peak ringing voltages that may be present on SW.
The average forward current can be estimated by:
Safety Timer and Overlap Protection Circuit
The overlap protection circuit prevents both the high--side
MOSFET and the low--side MOSFET from being on at the
same time, and minimizes the associated off times. This will
reduce power losses in the switching elements. The overlap
protection circuit accomplishes this by controlling the delay
from turning off the high--side MOSFET to turning on the
low--side MOSFET.
To prevent cross conduction during the high--side
MOSFET’s turn--off and the low--side MOSFET’s turn--on,
the overlap circuit monitors the voltage at the SW pin. When
the PWM input signal goes low, DRVH will go low after a
propagation delay (tpdlDRVH), turning the high--side
MOSFET off. However, before the low--side MOSFET can
turn on, the overlap protection circuit waits for the voltage at
the SW pin to fall below 4.0 V. Once SW falls below the 4.0 V
IF(AVG) = QGATE × fMAX
(eq. 2)
where fMAX is the maximum switching frequency of the
controller. The peak surge current rating should be checked
in--circuit, since this is dependent on the source impedance
of the 12 V supply and the ESR of CBST.
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7
NCP3418, NCP3418A
PACKAGE DIMENSIONS
SOIC--8 NB
CASE 751--07
ISSUE AH
--X--
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751--01 THRU 751--06 ARE OBSOLETE. NEW
STANDARD IS 751--07.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
--Y--
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
--Z--
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm 
inches
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP3418, NCP3418A
PACKAGE DIMENSIONS
SOIC--8 EP
CASE 751AC--01
ISSUE B
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS (ANGLES
IN DEGREES).
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
2X
0.10 C A--B
D
8
DETAIL A
D
A
EXPOSED
PAD
5
E1
5
F
8
G
E
2X
0.10 C D
PIN ONE
LOCATION
h
2X
1
4
4
0.20 C
e
BOTTOM VIEW
b
0.25 C A--B D
8X
B
1
A
TOP VIEW
0.10 C
A2
8X
A
b1
GAUGE
PLANE
SEATING
PLANE
C
c
H
0.10 C
SIDE VIEW
A1
A
END VIEW
0.25
L
(L1)
DETAIL A
θ
(b)
DIM
A
A1
A2
b
b1
c
c1
D
E
E1
e
L
L1
F
G
h
θ
c1
MILLIMETERS
MIN
MAX
1.35
1.75
0.00
0.10
1.35
1.65
0.31
0.51
0.28
0.48
0.17
0.25
0.17
0.23
4.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
0.40
1.27
1.04 REF
2.24
3.20
1.55
2.51
0.25
0.50
0_
8_
SECTION A--A
SOLDERING FOOTPRINT*
2.72
0.107
1.52
0.060
7.0
0.275
Exposed
Pad
4.0
0.155
2.03
0.08
0.6
1.270
SCALE 6:1
0.024
0.050
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
mm 
inches
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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