Dual Bootstrapped MOSFET Driver

Dual Bootstrapped
MOSFET Driver
ADP3414
a
FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High Side Drive
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Pulse-by-Pulse Disable Control
FUNCTIONAL BLOCK DIAGRAM
VCC
BST
DRVH
IN
APPLICATIONS
Mobile Computing CPU Core Power Converters
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
OVERLAP
PROTECTION
CIRCUIT
SW
DRVL
ADP3414
GENERAL DESCRIPTION
PGND
The ADP3414 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs which are the two switches in a
nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propagation delay and a 30 ns transition time. One of the drivers can
be bootstrapped and is designed to handle the high voltage
slew rate associated with “floating” high side gate drivers.
The ADP3414 includes overlapping drive protection (ODP)
to prevent shoot-through current in the external MOSFETs.
The ADP3414 is specified over the commercial temperature
range of 0°C to 70°C and is available in an 8-lead SOIC package.
12V
7V
D1
VCC
ADP3414
BST
CBST
DRVH
IN
Q1
SW
DELAY
+1V
DRVL
Q2
1V
PGND
Figure 1. General Application Circuit
©2010 SCILLC. All rights reserved.
May 2010 - Rev. 3
Publication Order Number:
ADP3414/D
ADP3414–SPECIFICATIONS1(T = 08C to 708C, VCC = 7 V, BST = 4 V to 26 V, unless otherwise noted.)
A
Parameter
Symbol
SUPPLY
Supply Voltage Range
Quiescent Current
VCC
ICCQ
Conditions
1
7.5
2
V
mA
0.8
V
V
trDRVH
tfDRVH
tpdhDRVH
tpdlDRVH
3.0
2.0
1.25
1.0
36
20
65
21
5.0
3.5
2.5
2.5
47
30
86
32
Ω
Ω
Ω
Ω
ns
ns
ns
ns
trDRVL
tfDRVL
tpdhDRVL
tpdlDRVL
VCC = 5 V
VCC = 7 V
VCC = 5 V
VCC = 7 V
VCC = 7 V, CLOAD = 3 nF
VCC = 7 V, CLOAD = 3 nF
VCC = 7 V
VCC = 7 V
3.0
2.0
1.5
1.0
27
19
30
15
5.0
3.5
3.0
2.5
35
26
35
25
Ω
Ω
Ω
Ω
ns
ns
ns
ns
LOW SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Propagation Delay3, 4 (See Figure 2)
Unit
VBST – VSW = 5 V
VBST – VSW = 7 V
VBST – VSW = 5 V
VBST – VSW = 7 V
VBST – VSW = 7 V, CLOAD = 3 nF
VBST – VSW = 7 V, CLOAD = 3 nF
VBST – VSW = 7 V
VBST – VSW = 7 V
Output Resistance, Sinking Current
Transition Times3 (See Figure 2)
Max
2.3
HIGH SIDE DRIVER
Output Resistance, Sourcing Current
Propagation Delay3, 4 (See Figure 2)
Typ
4.15
PWM INPUT
Input Voltage High2
Input Voltage Low2
Transition Times3 (See Figure 2)
Min
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA).
3
AC specifications are guaranteed by characterization but not production tested.
4
For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.
Specifications subject to change without notice.
Rev. 3 | Page 2 of 9 | www.onsemi.com
–2–
REV. A
ADP3414
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V
IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature Range . . . . . . 0°C to 125°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Model
Temperature Package
Range
Description
ADP3414JR 0°C to 70°C
Package
Option
8-Lead Standard
Small Outline (SOIC)
SOIC-8
PIN CONFIGURATION
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.
BST
1
IN
2
NC
3
VCC
4
8
DRVH
ADP3414
7
SW
TOP VIEW
(Not To Scale)
6
PGND
5
DRVL
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
1
BST
2
3
4
5
6
7
IN
NC
VCC
DRVL
PGND
SW
8
DRVH
Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW Pins
holds this bootstrapped voltage for the high side MOSFET as it is switched. The capacitor should be
chosen between 100 nF and 1 mF.
TTL-level input signal that has primary control of the drive outputs.
No Connection
Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating
return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turnon of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the
high low transition delay is determined at this pin.
Buck Drive. Output drive for the upper (buck) MOSFET.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3414 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Rev. 3 | Page 3 of 9 | www.onsemi.com
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
ADP3414
IN
tpdlDRVL
tfDRVL
tpdlDRVH
trDRVL
DRVL
tfDRVH
tpdhDRVH
DRVH-SW
trDRVH
VTH
VTH
tpdhDRVL
SW
1V
Figure 2. Nonoverlap Timing Diagram (Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted)
Rev. 3 | Page 4 of 9 | www.onsemi.com
–4–
REV. A
Typical Performance Characteristics– ADP3414
50
T
T
TA = 258C
VCC = 5V
DRVH
5V/DIV
CLOAD = 3nF
TA = 258C
VCC = 5V
45
DRVH
5V/DIV
40
TIME – ns
R3
R3
DRVL
2V/DIV
IN
DRVL
5V/DIV
R2
R2
2V/DIV
20
TPC 2. DRVL Fall and DRVH Rise
Times
DRVL @ VCC = 7V
125
37
32
DRVH @ VCC = 5V
DRVL @ VCC = 7V
27
40
20
DRVH @ VCC = 7V
TIME – ns
DRVH @ VCC = 7V
TIME – ns
TIME – ns
25
50
75
100
JUNCTION TEMPERATURE – 8C
45
DRVL @ VCC = 5V
15
0
50
30
25
DRVL @ VCC = 7V
TPC 3. DRVH and DRVL Rise Times
vs. Temperature
55
35
DRVL @ VCC = 5V
35
25
40ns/DIV
40ns/DIV
TPC 1. DRVH Fall and DRVL Rise
Times
DRVH @ VCC = 7V
30
IN
2V/DIV
R1
R1
DRVH @ VCC = 5V
35
30
DRVL @ VCC = 5V
25
DRVH @ VCC = 5V
22
17
DRVH @ VCC = 5V
10
20
DRVH @ VCC = 7V
12
5
15
0
0
25
50
75
100
JUNCTION TEMPERATURE – 8C
DRVL @ VCC = 5V
10
1.0
125
TPC 4. DRVH and DRVL Fall Times
vs. Temperature
2.0
3.0
4.0
LOAD CAPACITANCE – nF
5.0
TPC 5. DRVH and DRVL Rise Times
vs. Load Capacitance
8.5
35
TA = 258C
CLOAD = 3nF
8.0
25
VCC = 7V
20
15
VCC = 5V
10
5
SUPPLY CURRENT – mA
30
SUPPLY CURRENT – mA
DRVL @ VCC = 7V
VCC = 7V
7.5
CLOAD = 3nF
fIN = 250kHz
7.0
6.5
6.0
VCC = 5V
5.5
0
5.0
0
200
400 600 800 1000 1200 1400
IN FREQUENCY – kHz
TPC 7. Supply Current vs.
Frequency
0
100
25
50
75
JUNCTION TEMPERATURE – 8C
TPC 8. Supply Current vs.
Temperature
Rev. 3 | Page 5 of 9 | www.onsemi.com
REV. A
–5–
125
7
1.0
1.5
2.0 2.5 3.0 3.5 4.0 4.5
LOAD CAPACITANCE – nF
5.0
TPC 6. DRVH and DRVL Fall Times
vs. Load Capacitance
ADP3414
THEORY OF OPERATION
To prevent the overlap of the gate drives during Q2’s turn OFF
and Q1’s turn ON, the overlap circuit provides a internal delay
that is set to 50 ns. When the PWM input signal goes high, Q2
will begin to turn OFF (after a propagation delay), but before
Q1 can turn ON, the overlap protection circuit waits for the
voltage at DRVL to drop to around 10% of VCC. Once the
voltage at DRVL has reached the 10% point, the overlap protection circuit will wait for a 20 ns typical propagation delay. Once
the delay period has expired, Q1 will begin turn ON.
The ADP3414 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high side and the low side FETs. Each driver
is capable of driving a 3 nF load.
A more detailed description of the ADP3414 and its features
follows. Refer to the Functional Block Diagram.
Low Side Driver
The low side driver is designed to drive low RDS(ON) N-channel
MOSFETs. The maximum output resistance for the driver is
3.5 Ω for sourcing and 2.5 Ω for sinking gate current. The low
output resistance allows the driver to have 20 ns rise and fall
times into a 3 nF load. The bias to the low side driver is internally connected to the VCC supply and PGND.
APPLICATION INFORMATION
Supply Capacitor Selection
For the supply input (VCC) of the ADP3414, a local bypass
capacitor is recommended to reduce the noise and to supply some
of the peak currents drawn. Use a 1 µF, low ESR capacitor.
Multilayer ceramic chip (MLCC) capacitors provide the best
combination of low ESR and small size and can be obtained from
the following vendors:
When the driver is enabled, the driver’s output is 180 degrees
out of phase with the PWM input. When the ADP3414 is disabled, the low side gate is held low.
High-Side Driver
The high side driver is designed to drive a floating low RDS(ON)
N-channel MOSFET. The maximum output resistance for the
driver is 3.5 Ω for sourcing and 2.5 Ω for sinking gate current. The low output resistance allows the driver to have 30 ns
rise and fall times into a 3 nF load. The bias voltage for the
high side driver is developed by an external bootstrap supply
circuit, which is connected between the BST and SW Pins.
Murata
GRM235Y5V106Z16
www.murata.com
TaiyoYuden
EMK325F106ZF
www.t-yuden.com
Tokin
C23Y5V1C106ZP
www.tokin.com
Keep the ceramic capacitor as close as possible to the ADP3414.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (CBST) and a
Schottky diode, as shown in Figure 1. Selection of these components can be done after the high side MOSFET has been chosen.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, CBST. When the ADP3414 is starting up, the SW Pin
is at ground, so the bootstrap capacitor will charge up to VCC
through D1. When the PWM input goes high, the high side
driver will begin to turn the high side MOSFET, Q1, ON by
pulling charge out of CBST. As Q1 turns ON, the SW Pin will
rise up to VIN, forcing the BST Pin to VIN + VC(BST), which is
enough gate to source voltage to hold Q1 ON. To complete the
cycle, Q1 is switched OFF by pulling the gate down to the voltage at the SW Pin. When the low side MOSFET, Q2, turns
ON, the SW Pin is pulled to ground. This allows the bootstrap
capacitor to charge up to VCC again.
The bootstrap capacitor must have a voltage rating that is able
to handle the maximum battery voltage plus 5 V. A minimum 50
V rating is recommended. The capacitance is determined
using the following equation:
CBST =
QGATE
∆VBST
where, QGATE is the total gate charge of the high side MOSFET,
and ∆VBST is the voltage droop allowed on the high side MOSFET
drive. For example, the IRF7811 has a total gate charge of about
20 nC. For an allowed droop of 200 mV, the required bootstrap capacitance is 100 nF. A good quality ceramic capacitor
should be used.
The high-side driver’s output is in phase with the PWM input.
When the driver is disabled, the high side gate is held low.
Overlap Protection Circuit
The overlap protection circuit (OPC) prevents both of the main
power switches, Q1 and Q2, from being ON at the same time.
This is done to prevent shoot-through currents from flowing
through both power switches and the associated losses that can
occur during their ON-OFF transitions. The overlap protection
circuit accomplishes this by adaptively controlling the delay from
Q1’s turn OFF to Q2’s turn ON and by internally setting the
delay from Q2’s turn OFF to Q1’s turn ON.
A Schottky diode is recommended for the bootstrap diode due
to its low forward drop, which maximizes the drive available for
the high side MOSFET. The bootstrap diode must have a minimum 40 V rating to withstand the maximum battery voltage
plus 5 V. The average forward current can be estimated by:
IF(AVG) ≈ QGATE × f MAX
where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be checked in-circuit,
since this is dependent on the source impedance of the 5 V
supply and the ESR of CBST.
To prevent the overlap of the gate drives during Q1’s turn OFF
and Q2’s turn ON, the overlap circuit monitors the voltage at the
SW Pin. When the PWM input signal goes low, Q1 will begin to
turn OFF (after a propagation delay), but before Q2 can turn ON,
the overlap protection circuit waits for the voltage at the SW Pin
to fall from VIN to 1 V. Once the voltage on the SW Pin has fallen
to 1 V, Q2 will begin turn ON. By waiting for the voltage on the
SW Pin to reach 1 V, the overlap protection circuit ensures that
Q1 is OFF before Q2 turns on, regardless of variations in temperature, supply voltage, gate charge, and drive current.
Rev. 3 | Page 6 of 9 | www.onsemi.com
–6–
REV. A
ADP3414
Printed Circuit Board Layout Considerations
Typical Application Circuits
Use the following general guidelines when designing printed
circuit boards:
The circuit in Figure 3 shows how two drivers can be combined with the ADP3160 to form a total power conversion
solution for VCC(CORE) generation in a high current Intel CPU
computer. Figure 4 gives a similar application circuit for a
45 A AMD processor.
1. Trace out the high current paths and use short, wide traces
to make these connections.
2. Connect the PGND pin of the ADP3414 as close as possible
to the source of the lower MOSFET.
3. The VCC bypass capacitor should be located as close as
possible to VCC and PGND Pins.
VIN
12V
270mF 3 4
OS–CON 16V
C12
C13
C14
R7
20V
C15
C23 C24
10mF 10mF
VINRTN
C26
4.7mF
R6
10V
C21
15nF
C4
4.7mF
R4
4mV
D1
MBR052LTI
R5
2.4kV
Z1
ZMM5236BCT
U2
ADP3414
Q5
2N3904
1 BST
2
IN
3 NC
U1
ADP3160
FROM
CPU
RA
34.0kV
COC
1.4nF
1 VID4
VCC 16
2 VID3
REF 15
3 VID2
CS– 14
4 VID1
PWM1 13
5 VID0
PWM2 12
6 COMP
RZ
1.1kV
4
SW 7
C22
1nF
Q2
FDB8030L
DRVL 5
1200mF 3 8
OS–CON 2.5V
11mV ESR (EACH)
C10
1mF
D2
MBR052LTI
CS+ 11
U3
ADP3414
GND 9
C1
150pF
1 BST
R1
1kV
IN
3 NC
4
VCC
DRVH 8
+
DRVL 5
Figure 3. 53.4 A Intel CPU Supply Circuit
Rev. 3 | Page 7 of 9 | www.onsemi.com
+
+
+
+
VCC (CORE)
1.1V – 1.85V
53.4A
+
+
C11 C16 C17 C18 C19 C20 C27 C28
Q3
FDB7030L
PGND 6
NC = NO CONNECT
–7–
+
SW 7
C6
1mF
REV. A
L1
600nH
PGND 6
C5
1mF
2
C2
100pF
VCC
Q1
FDB7030L
DRVH 8
7 FB PWRGND 10
8 CT
RB
11.5kV
C9
1mF
Q4
FDB8030L
L2
600nH
VCC (CORE)
RTN
ADP3414
VIN
5V
1000mF 3 6
RUBYCON ZA SERIES
C12
C13
C14
C15
C24
C25
R7
20V
VINRTN
R4
5mV
12V VCC
R6
10V
C21
15nF
C4
4.7mF
C29
10mF
D1
MBR052LTI
C26
4.7mF
12V
VCCRTN
R5
2.4kV
Z1
ZMM5236BCT
U2
ADP3414
Q5
2N3904
1 BST
2
IN
3 NC
U1
ADP3160
FROM
CPU
RA
6.98kV
COC
4.7nF
1 VID4
VCC 16
2 VID3
REF 15
3 VID2
CS– 14
4 VID1
PWM1 13
5 VID0
PWM2 12
6 COMP
RZ
750V
RB
14.0kV
4
PWRGD 10
8 CT
GND 9
C22
1nF
Q1
FDB7030L
DRVH 8
SW 7
L1
600nH
PGND 6
Q2
FDB7045L
DRVL 5
1000mF 3 8
RUBYCON ZA SERIES
24mV ESR (EACH)
C10
1mF
D2
MBR052LTI
U3
ADP3414
C1
150pF
1 BST
2
C2
100pF
VCC
C9
1mF
C5
1mF
CS+ 11
7 FB
C30
10mF
R1
1kV
IN
3 NC
4
VCC
DRVH 8
+
+
+
+
+
+
+
VCC (CORE)
1.1V – 1.85V
45A
+
C11 C16 C17 C18 C19 C20 C27 C28
Q3
FDB7030L
SW 7
VCC (CORE)
RTN
L2
600nH
PGND 6
DRVL 5
C6
1mF
Q4
FDB7045L
NC = NO CONNECT
Figure 4. 45 A Athlon Duron CPU Supply Circuit
Rev. 3 | Page 8 of 9 | www.onsemi.com
–8–
REV. A
ADP3414
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
1
4
6.20 (0.2440)
5.80 (0.2284)
PIN 1
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
SEATING
PLANE
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.33 (0.0130)
0.50 (0.0196)
3 458
0.25 (0.0099)
88
0.25 (0.0098) 08 1.27 (0.0500)
0.41 (0.0160)
0.19 (0.0075)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
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