NCP5358 Gate Driver for Desktop Power Systems QFN−16 CASE 485D 4x4 mm N5358 A L Y W G = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS GND Faster Rise and Fall Times Thermal Shutdown Protection Adaptive−Non−Overlap Circuit Floating Top Driver Accommodates Boost voltage of up to 30 V Output Disable Control Turn Off Both MOSFETs Complies with VR11.1 Specifications Under−Voltage Lock Out Power Saving Operation under Light Load Condition Thermally Enhanced Package Available These are Pb−Free Devices N5358 ALYWG G PWM2 • • • • • • • • • • MARKING DIAGRAM PWM1 Features http://onsemi.com EN The NCP5358 is a high performance two channel gate driver. It combines two single NCP5359 gate drivers together and provides an optimized solution for multi−phase application. Each channel gate driver has both high−side and low side power MOSFETs in a synchronous buck converter. Also, it can drive up to 3 nF load with a 25 ns propagation delay and 20 ns transition time. An adaptive non−overlap and power saving operation circuit has built in. It can provide a low switching loss and high efficiency solution in notebook and desktop systems. Thus, this controller has three protection functions, under voltage lockout (UVLO), over voltage protection (OVP) and thermal shutdown. The NCP5358 is available in 4x4 mm QFN16 package. SW2 VCC DRVH2 SW1 Typical Applications • Power Solutions for Desktop and Notebook system. DRVH1 BST2 BST1 VCCP DRVL2 PGND2 PGND1 DRVL1 (Top View) ORDERING INFORMATION Device Package Shipping† NCP5358MNTXG QFN−16 (Pb−Free) 4000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2008 December, 2008 − Rev. 0 1 Publication Order Number: NCP5358/D NCP5358 BST1 ChipEN DRVH comparator PWM >2V =1, else = 0 PWM1 DRVH1 Level Shift and Driver Falling Edge Delay 100K SW1 FPWM comparator 1V < PWM < 2V =1, else = 0 CH1 SW1 PGND1 100K Falling Edge Delay 1mV R S Q Q ChipEN VCCP DRVL1 Driver Pre−OV ChipEN EN VCC VCCP VCC GND Fault SW1 SW2 UVLO Pre −Over Voltage VCCP Fault Thermal Shutdown EN Pre−OV ChipEN BST2 DRVH2 PWM2 PGND2 CH2 SW 2 DRVL2 Figure 1. Internal Block Diagram and Typical Application http://onsemi.com 2 NCP5358 VCCP VBAT BST1 DRVH1 PWM1 SW1 EN PGND1 Vo DRVL1 VCC NCP5358 PGND1 VCCP GND VBAT VCCP BST2 DRVH2 PWM2 SW 2 DRVL2 Vo PGND2 PGND2 Figure 2. Typical Applications http://onsemi.com 3 NCP5358 PIN DESCRIPTION Pin NO. Symbol Descriptions 1 VCC Analog logic input power pin 2 SW 1 PWM 1 Switch Node pin 3 DRVH 1 PWM 1 High side gate drive output 4 BST1 5 DRVL 1 Upper MOSFET floating bootstrap supply pin PWM 1 Low side gate drive output 6 PGND 1 PWM 1 Ground pin 7 PGND 2 PWM 2 Ground pin 8 DRVL 2 PWM 2 Low side gate drive output 9 VCCP Connect to input power supply 10 V to 13.2 V 10 BST 2 Upper MOSFET floating bootstrap supply pin 11 DRVH 2 12 SW 2 PWM 2 Switch Node pin 13 GND Analog logic ground pin 14 PWM 2 PWM2 input pin When PWM voltage is higher than 2 V, DRVH will set to 1 and DRVL set to 0 When PWM voltage is lower than 1 V, DRVL set to 1 and DRVH set to 0 When 1 V < PWM < 2V and SW < 0, DRVL will set to 1 When 1 V < PWM < 2V and SW > 0, DRVL will set to 0 15 PWM 1 PWM1 input pin When PWM voltage is higher than 2 V, DRVH will set to 1 and DRVL set to 0 When PWM voltage is lower than 1 V, DRVL set to 1 and DRVH set to 0 When 1 V < PWM < 2 V and SW < 0, DRVL will set to 1 When 1 V < PWM < 2 V and SW > 0, DRVL will set to 0 16 EN PWM 2 High side gate drive output Both Channel Enable pin When OVP, TSD or UVLO has happened, the gate driver will pull the pin to low http://onsemi.com 4 NCP5358 MAXIMUM RATINGS Rating Symbol Value Unit RθJA 110 °C/W TJ 0 to + 150 °C Thermal Characteristics Plastic Package, Thermal Resistance, Junction to Air (1 in2 of 2 oz copper) Operating Junction Temperature Range Operating Ambient Temperature Range TA 0 to +85 °C Storage Temperature Range Tstg −55 to +150 °C Moisture Sensitivity Level MSL 1 − Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Pin Symbol Pin Name VMAX VMIN VCC Main Supply Voltage input 15 V −0.3 V VCCP Main Supply Voltage input 15 V −0.3 V BST1, BST2 Bootstrap Supply voltage 30 V wrt / GND 35 V ≤ 50 ns wrt / GND 15 wrt / SW −0.3 V SW1,SW2 Switching Node (Bootstrap Supply Return) 30 V −1 VDC −10 V (200 ns) DRVH1, DRVH2 High Side Driver output BST + 0.3 V 35 V ≤ 50 ns wrt / GND 15 wrt / SW −0.3 V −2 V (200 ns) DRVL1, DRVL2 Low Side Driver output Vcc + 0.3 V −0.3 V −2 V (200 ns) PWM1, PWM2 DRVH and DRVL Control Input 6V −0.3 V EN Enable Pin 6V −0.3 V GND Ground 0 0V 1. Latchup Current Maximum Rating: 100 mA per JEDEC standard: JESD78. 2. Moisture Sensitivity Level (MSL): 1&3 per IPC/JEDEC standard: J−STD−020A. 3. The maximum package power dissipation limit must not be exceeded. PD + NOTE: TJ(max) * TA RqJA This device is ESD sensitive. Use standard ESD precautions when handling. http://onsemi.com 5 NCP5358 ELECTRICAL CHARACTERISTICS (VCC = 12 V, TA = 0°C to 85°C, VEN = 5 V, unless other noted.) Symbol Characteristics Test Conditions Min Typ Max Units SUPPLY VOLTAGE VCC Operating Voltage VCC 10 − 13.2 V Power ON Reset Threshold VPOR − 3.2 − V SUPPLY CURRENT VCCP Quiescent Supply Current in Normal Operation IVCCP_NORM EN = 5 V, PWM1 = PWM2 = OSC, FSW = 100 K, duty cycle = 50%. CLOAD = 0 p 1.5 4 mA VCC Quiescent Supply Current in Normal Operation IVCC_NORM EN = 5 V, PWM1 = PWM2 = OSC, FSW = 100 K, duty cycle = 50%. CLOAD = 0 p 1.5 2.5 mA VCCP Standby Current IVCCP_SBC EN = GND; No switching − 0.1 0.5 mA VCC Standby Current IVCC_SBC EN = GND; No switching − 0.9 1.5 mA mA BST1 Quiescent Supply Current in Normal Operation IBST1_normal PWM1 = +5 V 1.0 1.5 IBST1_normal PWM1 = GND 1.0 1.5 BST2 Quiescent Supply Current in Normal Operation IBST2_normal PWM2 = +5 V 1.0 1.5 IBST2_normal PWM2 = GND 1.0 1.5 IBST1_SD PWM1 = +5 V 0.25 IBST1_SD PWM1 = GND 0.25 IBST2_SD PWM2 = +5 V 0.25 IBST2_SD PWM2 = GND 0.25 BST1 Standby Current BST2 Standby Current mA mA mA UNDER VOLTAGE LOCKOUT VCCP Start Threshold VCCPTH VCCP UVLO Hysteresis VCCPHYS VCC Start Threshold VCCTH VCC UVLO Hysteresis VCCHYS 8.2 8.7 9.5 1.0 8.2 8.7 V V 9.5 1.0 V V Output Overvoltage Trip Threshold at channel 1 Startup OVP1_SU Power Startup time, VCC > 9 V. (Without trimming) 1.8 2.0 V Output Overvoltage Trip Threshold at channel 2 Startup OVP2_SU Power Startup time, VCC > 9 V. (Without trimming) 1.8 2.0 V EN INPUT Input Voltage High VEN_HI 2.0 V Input Voltage Low VEN_LOW Hysteresis (Note 6) VEN_HYS Enable Pin Sink Current IEN_SINK Propagation Delay Time (Note 6) TpdhEN 20 60 ns TpdlEN 20 60 ns 1.5 1.6 V 1.0 500 VCC = 5.5 V V mV 5.0 mA PWM INPUT PWM Input Self Bias Voltage DRVH Comparator Rise Threshold DRVL Comparator Rise Threshold CH1 VPWM1 CH2 VPWM2 CH1 VTH_DRVH1 CH2 VTH_DRVH2 CH1 VTH_DRVL1 CH2 VTH_DRVL2 1.4 2.2 V 0.8 http://onsemi.com 6 V NCP5358 ELECTRICAL CHARACTERISTICS (VCC = 12 V, TA = 0°C to 85°C, VEN = 5 V, unless other noted.) Characteristics Symbol Test Conditions Min Typ Max Units PWM INPUT Input Current CH1 IPWM1 PWM1 = 0 V, EN = GND CH2 IPWM2 PWM2 = 0 V, EN = GND CH1 RH_TG1 VBST1 – VSW1 = 12 V CH2 RH_TG2 VBST2 – VSW2 = 12 V CH1 RH_TG1 VBST1 – VSW1 = 12 V CH2 RH_TG2 VBST2 – VSW2 = 12 V CH1 TrDRVH1 30 mA HIGH SIDE DRIVER Output Resistance, Sourcing Output Resistance, Sinking Transition Time (Note 6) CH2 Propagation Delay (Notes 5 & 6) CH1 CH2 2.0 3.5 Ohms 1.0 2.5 Ohms CLOAD = 3 nF, VBST1 – VSW1 = 12 V 16 25 ns TfDRVH1 CLOAD = 3 nF, VBST1 – VSW1 = 12 V 11 15 TrDRVH2 CLOAD = 3 nF, VBST2 – VSW2 = 12 V 16 25 TfDRVH2 CLOAD = 3 nF, VBST2 – VSW2 = 12 V 11 15 TpdhDRVH1 Driving High, CLOAD = 3 nF 10 40 TpdlDRVH1 Driving Low, CLOAD = 3 nF 10 40 TpdhDRVH2 Driving High, CLOAD = 3 nF 10 30 TpdlDRVH2 Driving Low, CLOAD = 3 nF 10 30 ns LOW SIDE DRIVER Output Resistance, Sourcing Output Resistance, Sinking Transition Time (Note 6) Ohms 1.0 2.5 Ohms CLOAD = 3 nF 16 25 ns TfDRVL1 CLOAD = 3 nF 11 15 TrDRVL2 CLOAD = 3 nF 16 25 TfDRVL2 CLOAD = 3 nF 11 15 SW = GND CH2 RH_BG2 SW = GND CH1 RL_BG1 SW = VCC CH2 RL_BG2 SW = VCC CH1 TrDRVL1 CH1 CH2 Negative Current Detector Threshold 3.5 RH_BG1 CH2 Propagation Delay (Notes 5 & 6) 2.0 CH1 TpdhDRVL1 Driving High, CLOAD = 3 nF 10 40 TpdlDRVL1 Driving Low, CLOAD = 3 nF 10 40 TpdhDRVL2 Driving High, CLOAD = 3 nF 10 30 TpdlDRVL2 Driving Low, CLOAD = 3 nF 10 30 CH1 VNCDT1 (Note 4) CH2 VNCDT2 (Note 4) Tsd (Note 6) Tsdhys (Note 6) −1.0 ns mV THERMAL SHUTDOWN Thermal Shutdown Thermal Shutdown Hysteresis 4. Design guaranteed 5. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. 6. Guaranteed by design; not tested in production http://onsemi.com 7 150 170 20 − °C °C NCP5358 Table 1. Decoder Truth Table: PWM 1 or PWM 2 Input ZCD DRVL DRVH X Low High Greater than 1.0 V, but less than 2.0 V High (current through MOSFET is greater than 0) High Low Greater than 1.0 V, but less than 2.0 V Low (current through MOSFET is less than 0) Low Low X High Low Greater than 2.0 V Less than 1.0 V Application Information IN tpdlDRVL tfDRVL 90% DRVL 2V 90% 10% 10% tpdhDRVH trDRVH tpdlDRVH 90% trDRVL tfDRVH 90% DRVH−SW 10% 2V 10% tpdhDRVL SW PWM DRVH−SW DRVL IL Figure 3. Timing Diagram http://onsemi.com 8 NCP5358 Power ON Reset The NCP5358 gate driver is a dual phase MOSFET driver, each phase designed for driving two N−channel MOSFETs in a synchronous buck converter topology. This driver is compatible with the Signal channel NCP5359 gate drive. This gate drives has a Bi−direction fault detection and multi−level PWM input feature. When the gate driver works with ON’s NCP539X controller, it can provide a difference output logic status through multi−level PWM input. For this new feature, higher efficiency can be provided. For the bi−direction fault detection function, it is used to provide a driver state information to other gate drivers and controller in a multi−phase buck converter. e.g over voltage protection (OVP) function at startup, thermal shutdown and under voltage lockout (UVLO). This feature can provide an additional protection function for the multi−phase system when the fault condition occurs in one channel. With this additional feature, converter overall system will be more reliable and safe. Power on reset feature is used to protect a gate driver avoid abnormal status driving the start up condition. When the initial soft start voltage VCC is higher than 3.2 V, the gate driver will monitor the switching node SW pin. If SW1 or SW2 pin high than 1.9 V, bottom gate will be force to high for discharge the output capacitor. The fault mode will be latch and EN pin will force both channel to be low, unless the driver is recycle. When input voltage is higher than 9 V, the gate driver will normal operation, top gate driver DRVH and bottom gate driver will follow the PWM signal decode to a status. Adaptive Non−overlap The non−overlap dead time control is used to avoid the shoot through damage the power MOSFETs. When the PWM signal pull high, DRVL will go low after a propagation delay, the controller will monitors the switching node (SW) pin voltage and the gate voltage of the MOSFET to know the status of the MOSFET. When the low side MOSFET status is off an internal timer will delay turn on of the high−side MOSFET. When the PWM pull low, gate DRVH will go low after the propagation delay (tpdDRVH). The time to turn off the high side MOSFET is depending on the total gate charge of the high−side MOSFET. A timer will be triggered once the high side MOSFET is turn off to delay the turn on the low−side MOSFET. Enable Pin The bi−direction enable pin is connected with an open drain MOSFET. This pin is controlled by internal or external signal. There are three conditions will be triggered: 1. The voltage at SW1 or SW2 pin is higher than preset voltage at power start up. 2. The controller hits the UVLO at VCC pin or VCCP pin. 3. The controller hits the thermal shutdown. When the internal fault has been detected, EN pin will be pull low. In this case, both channel drive output DRVH and DRVL will be forced low, until the fault mode remove then restart automatic. Layout Guidelines Layout is very important thing for design a DC−DC converter. Bootstrap capacitor and VCC capacitor are most critical items, it should be placed as close as to the driver IC. Another item is using a GND plane. Ground plane can provide a good return path for gate drives for reducing the ground noise. Therefore GND pin should be directly connected to the ground plane and close to the low−side MOSFET source pin in every channel. Also, the gate drive trace should be considered. The gate drives has a high di/dt when switching, therefore a minimized gate drives trace can reduce the di/dv, raise and fall time for reduce the switching loss. Under Voltage Lockout The DRVH1, DRVH2 and DRVL1, DRVL2 are held low until VCC or VCCP reaches 9 V during startup. The PWM signals will control the gate status when VCC threshold is exceeded. If VCC decreases to 3.2 V below the threshold, the output gate will be forced low until input voltage VCC rises above the startup threshold. http://onsemi.com 9 NCP5358 PACKAGE DIMENSIONS 16 PIN QFN CASE 485D−01 ISSUE O −X− A M −Y− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. N B 0.25 (0.010) T 0.25 (0.010) T R J C 0.08 (0.003) T −T− K SEATING PLANE E H G L 5 8 4 9 1 12 DIM A B C D E F G H J K L M N P R MILLIMETERS MIN MAX 4.00 BSC 4.00 BSC 0.80 1.00 0.23 0.35 2.75 2.85 2.75 2.85 0.65 BSC 1.38 1.43 0.20 REF 0.00 0.05 0.35 0.45 2.00 BSC 2.00 BSC 1.38 1.43 0.60 0.80 INCHES MIN MAX 0.157 BSC 0.157 BSC 0.031 0.039 0.009 0.014 0.108 0.112 0.108 0.112 0.026 BSC 0.054 0.056 0.008 REF 0.000 0.002 0.014 0.018 0.079 BSC 0.079 BSC 0.054 0.056 0.024 0.031 F 16 D 13 NOTE 3 0.10 (0.004) M P T X Y ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP5358/D