8-Channel EMI Filter with ESD Protection

CM1443-08CP
8-Channel EMI Filter Array
with ESD Protection
Features
• Eight Channels of EMI Filtering for Data Ports
• Pi−Style EMI Filters in a Capacitor−Resistor−Capacitor (C−R−C)
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Network
• ±15 kV ESD Protection on Each Channel
•
•
•
•
•
(IEC 61000−4−2 Level 4, Contact Discharge)
±30 kV ESD Protection on Each Channel (HBM)
Chip Scale Package (CSP) Features Extremely Low Lead Inductance
for Optimum Filter and ESD Performance
20−Bump; 0.4 mm Pitch, 3.160 x 1.053 mm Footprint
OptiGuardt Coating for Improved Reliability at Assembly
These Devices are Pb−Free and are RoHS Compliant
WLCSP20
CP SUFFIX
CASE 567BU
MARKING DIAGRAM
Applications
•
•
•
•
•
•
EMI Filtering and ESD Protection for Both Data and I/O Ports
Wireless Handsets
Handheld PCs / PDAs
MP3 Players
Notebooks
Desktop PCs
R = 100 W
8.5 pF
CS
8.5 pF
N438
= CM1443−08CP
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
BLOCK DIAGRAM
FILTERn*
(Pins A1−A8)
N438 MG
G
FILTERn*
(Pins C1−C8)
CS
GND
(Pins B1−B4)
Device
Package
Shipping†
CM1443−08CP
CSP−20
(Pb−Free)
3500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1 of 8 EMI/RFI + ESD Channels
*See Package/Pinout Diagrams for expanded pin information.
© Semiconductor Components Industries, LLC, 2011
March, 2011 − Rev. 3
1
Publication Order Number:
CM1443−08CP/D
CM1443−08CP
PACKAGE / PINOUT DIAGRAMS
Top View
(Bumps Down View)
Orientation
Marking
A
+
1
2
4
3
5
6
Bottom View
(Bumps Up View)
7
8
C1
C2
B
B1
C
A1 A2
A1
CM1443−08CP
C3
C4
C5
B2
A3
C6
C7
B3
A4
A5
C8
B4
A6
A7
A8
Orientation
Marking
Table 1. PIN DESCRIPTIONS
Pins
Name
A1
FILTER1
A2
Description
Pins
Name
Description
Filter Channel 1
C1
FILTER1
Filter Channel 1
FILTER2
Filter Channel 2
C2
FILTER2
Filter Channel 2
A3
FILTER3
Filter Channel 3
C3
FILTER3
Filter Channel 3
A4
FILTER4
Filter Channel 4
C4
FILTER4
Filter Channel 4
A5
FILTER5
Filter Channel 5
C5
FILTER5
Filter Channel 5
A6
FILTER6
Filter Channel 6
C6
FILTER6
Filter Channel 6
A7
FILTER7
Filter Channel 7
C7
FILTER7
Filter Channel 7
A8
FILTER8
Filter Channel 8
C8
FILTER8
Filter Channel 8
B1−B4
GND
Device Ground
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
–65 to +150
°C
DC Power per Resistor
100
mW
DC Package Power Rating
600
mW
Storage Temperature Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
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2
Rating
Units
–40 to +85
°C
CM1443−08CP
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter
Conditions
R
Resistance
CT
Total Capacitance
At 2.5 V DC
CS
Single Capacitor
At 2.5 V DC
TCR
Temperature Coefficient of Resistance
TCC
Temperature Coefficient of Capacitance
At 2.5 V DC
VDIODE
Diode Voltage (reverse bias)
IDIODE = 10 mA
ILEAK
Diode Leakage Current (reverse bias)
VDIODE = 3.3 V
VSIG
Signal Voltage
Positive Clamp
Negative Clamp
ILOAD = 10 mA
VESD
In−system ESD Withstand Voltage
a) Human Body Model, MIL−STD−883,
Method 3015
b) Contact Discharge per IEC 61000−4−2
Level 4
(Notes 2 and 4)
Clamping Voltage during ESD Discharge
MIL−STD−883 (Method 3015), 8 kV
Positive Transients
Negative Transients
(Notes 2, 3 and 4)
Cut−off Frequency
ZSOURCE = 50 W, ZLOAD = 50 W
R = 100 W, CS = 8.5 pF
VCL
fC
Min
Typ
Max
Units
80
100
120
W
14
17
21
pF
8.5
pF
1200
ppm/°C
−300
ppm/°C
5.5
5.6
−1.5
V
0.1
1.0
6.8
–0.8
9.0
−0.4
mA
V
kV
±30
±15
V
+10
–5
220
MHz
1. TA = 25°C unless otherwise specified.
2. ESD applied to input and output pins with respect to GND, one at a time.
3. Clamping voltage is measured at the opposite side of the EMI filter to the ESD pin. For example, if ESD is applied to Pin A1, then clamping
voltage is measured at Pin C1.
4. Unused pins are left open.
APPLICATION INFORMATION
Refer to Application Note “The Chip Scale Package”, for a detailed description of Chip Scale Packages offered by
ON Semiconductor.
PERFORMANCE INFORMATION
Figure 1. Resistance vs. Temperature (normalized to resistance at 255C)
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3
CM1443−08CP
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (TA = 255C, DC Bias = 0 V, 50 W Environment)
Figure 2. Insertion Loss vs. Frequency (A1−C1 to GND B1)
Figure 3. Insertion Loss vs. Frequency (A2−C2 to GND B1)
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4
CM1443−08CP
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (TA = 255C, DC Bias = 0 V, 50 W Environment)
Figure 4. Insertion Loss vs. Frequency (A3−C3 to GND B2)
Figure 5. Insertion Loss vs. Frequency (A4−C4 to GND B2)
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5
CM1443−08CP
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (TA = 255C, DC Bias = 0 V, 50 W Environment)
Figure 6. Insertion Loss vs. Frequency (A5−C5 to GND B3)
Figure 7. Insertion Loss vs. Frequency (A6−C6 to GND B3)
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6
CM1443−08CP
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (TA = 255C, DC Bias = 0 V, 50 W Environment)
Figure 8. Insertion Loss vs. Frequency (A7−C7 to GND B4)
Figure 9. Insertion Loss vs. Frequency (A8−C8 to GND B4)
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7
CM1443−08CP
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (TA = 255C, DC Bias = 0 V, 50 W Environment)
Figure 10. Comparison of Filter Response Curves for CM1443 vs. DC Bias
Figure 11. Filter Capacitance vs. Input Voltage over Temperature
(normalized to capacitance at 2.5 VDC and 255C)
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CM1443−08CP
PACKAGE DIMENSIONS
WLCSP20, 3.16x1.05
CASE 567BU−01
ISSUE O
PIN A1
REFERENCE
2X
0.05 C
2X
ÈÈ
ÈÈ
D
A
E
0.05 C
DIM
A
A1
A2
b
D
E
eD
eE
TOP VIEW
OptiGuard Option
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
B
ÉÉÉÉÉÉÉÉ
A2
MILLIMETERS
MIN
MAX
0.69
0.54
0.17
0.24
0.42 REF
0.24
0.29
3.16 BSC
1.05 BSC
0.400 BSC
0.347 BSC
A
0.05 C
NOTE 3
A1
C
SIDE VIEW
SEATING
PLANE
eD/2
20X
b
0.05 C A B
0.03 C
eD
eE
C
B
A
1 2 3
4 5 6
7 8 9
10 1112
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
PACKAGE
OUTLINE
A1
0.35
0.35
20X
0.40
PITCH
0.25
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
OptiGuardt is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
CM1443−08CP/D
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