4-In-1 PWM Buck and Tri-Linear Power Controller

NCP5209
4−In−1 PWM Buck and
Tri−Linear Power Controller
The NCP5209 4−In−1 PWM Buck and Tri−Linear Power Controller
is a complete ACPI compliant power solution for MCH and DDR
memory. This IC combines the high efficiency of a PWM controller
for the VDDQ supply with the simplicity of linear regulator for the
VTT termination voltage as well as the MCH core supply voltage.
This IC contains a synchronous PWM buck controller for driving
two external N−Ch FETs to form the DDR memory supply voltage
(VDDQ). The DDR memory termination regulator (VTT) is designed
to track at the half of reference voltage while sourcing and sinking
current. The two linear regulator controllers driving two external
N−Ch FETs are cascaded to produce the MCH core voltage (VMCH).
Protective features include, soft−start circuitry, undervoltage
monitoring of 5VDUAL, 5VATX and 12VATX, and thermal
shutdown. The device is housed in a thermal enhanced space−saving
QFN−20 package.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Synchronous PWM Buck Controller for VDDQ
Integrated Power FETs in VTT Regulator Source/Sink up to 2.0 A
Two Linear Regulator Drivers for VMCH
All External Power MOSFETs are N−Channel
Adjustable VDDQ and VMCH by External Dividers
VTT Tracks at Half of Reference Voltage or can be Adjusted
Externally
Fixed Switching Frequency of 250 kHz for DDQ Regulator in
Normal Mode
Doubled Switching Frequency of 500 kHz for DDQ Regulator in
Standby Mode to Optimize Inductor Current Ripple and Efficiency
Soft−Start Protection for all Regulators
Undervoltage Monitoring of Supply Voltages
Overcurrent Protection for DDQ and VTT Regulators
Fully Complies with ACPI Power Sequencing Specifications
Short Circuit Protection Prevents Damage to Power Supply Due to
Reverse DIMM Insertion
Thermal Shutdown
5x6 QFN−20 Package
Applications
• DDR I and DDR II Memory and MCH Power Supply
 Semiconductor Components Industries, LLC, 2004
June, 2004 − Rev. 1
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MARKING
DIAGRAM
20
NCP5209
AWLYYWW
1
QFN−20
MN SUFFIX
CASE 505AB
1
NCP5209 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
PIN CONNECTIONS
COMP_DDQ
FBDDQ
SW_DDQ
BG_DDQ
TG_DDQ
BOOT
SS
PGND
VTT
VDDQ
5VDUAL
OCDDQ
BUF_Cut
DRV_2P4
FB2P4
DRV_1P5
AGND
FBVTT
DDQ_REF
FB1P5
NOTE: Pin 21 is the thermal pad
on the bottom of the device.
ORDERING INFORMATION
Device
Package
Shipping†
NCP5209MNR2
6x5 mm
QFN−20
2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
Publication Order Number:
NCP5209/D
NCP5209
CL1
5VATX
BUF_Cut
RL1
BUF_Cut
BOOT
SCHOTTKY
CSS
VTT
1.25 V,
12VATX
13 V
Zener
5VDUAL
VTT
2 Apk
SCHOTTKY
OCDDQ
SS
5VDUAL
R3
COUT2
FBVTT
R4
TG_DDQ
M1
REF_SNS
L
DDQ_REF
AGND
NCP5209
M2
BG_DDQ
PGND
DRV_2P4
COMP_DDQ
2P4V
R5
FB2P4
CZ2
CZ1
COUT3
RZ1
R6
CP1
RZ2
R1
FBDDQ
DRV_1P5
M4
R2
1P5V
R7
FB1P5
VDDQ
1.5 V, 7 A
COUT4
R8
Figure 1. Application Diagram
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2
2.5 V, 20 A
COUT1
SW_DDQ
3.3VATX
M3
VDDQ
NCP5209
VREF1
VOLTAGE
and CURRENT
REFERENCE
CL1
RL1
5VATX
VREF2
_VREFQD
OCDDQ
THERMAL
SHUTDOWN
TSD
BOOT
12VATX
BUF_CUT
BOOT
BOOT
CONTROL
_BOOTGD
R10
VREF1
R11
+
LOGIC
S0
BOOT−
UVLO
Schottky
13 V
Zener
Schottky
S3
MCH
5VDUAL
−
5VDUAL
5VDUAL
R12
+
ILIM
5VDUAL−
UVLO
_5VDLGD
+
VREF1
R13
−
IREF
BOOT
−
TG_DDQ
M1
VDDQ
OCDDQ
L
R14
+
VREF1
−
R15
PGND
VDDQ
PWM
LOGIC
5VATX−
UVLO
_5VATXGD
SW_DDQ
BOOT
SS
CSS
M2
PGND
PGND
OSC
COUT1
RSWDDQ
BG_DDQ
S0
COMP_DDQ
S3
VREF1
MCH
AMP
+
+
A1
CZ2
CP1
CZ1
R1
RZ2
RZ1
−
−
FBDDQ
R2
DDQ_REF
5VDUAL
S0
R16
−
M2
VDDQ
+
VTT
Regulation
Control
VTT
R17
AGND
5VDUAL
VTT
R18
R3
−
R19
+
R4
AGND
AGND
PGND
VREF2
COUT2
M3
FBVTT
3.3VATX
5VDUAL
BOOT
DRV_2P4
+
M3
2P4V
−
R5
AGND
S0
VREF2
PGND
5VDUAL
FB2P4
BOOT
R6
COUT3
+
MCH
M4
−
DRV_IP5
R7
PGND
1P5V
AGND
FB1P5
R8
AGND
Figure 2. Internal Block Diagram
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3
COUT4
NCP5209
PIN DESCRIPTION
Pin
Symbol
Descriptions
1
COMP
VDDQ error amplifier compensation node.
2
FBDDQ
DDQ regulator feedback pin.
3
SS
4
PGND
Soft−start pin of DDQ.
Power ground.
5
VTT
6
VDDQ
VTT regulator output.
Power input for VTT linear regulator.
7
AGND
Analog ground connection and remote ground sense.
8
FBVTT
VTT linear regulator pin for closed loop regulation.
9
DDQ_REF
10
FB1P5
11
DRV_1P5
Reference voltage input of VTT regulator.
2nd linear regulator pin for closed loop regulation.
2nd linear regulator gate driver output for N−channel power FET.
12
FB2P4
13
DRV_2P4
1st linear regulator pin for closed loop regulation.
1st linear regulator gate driver output for N−channel power FET.
14
BUF_CUT
Active high control signal to activate S3 sleep state.
15
OCDDQ
Dual function I/O pin for overcurrent sensing as well as programming input of the high side FET of
DDQ regulator, which is also monitored by undervoltage lock out circuitry.
16
5VDUAL
5.0 V dual supply input, which is monitored by undervoltage lock out circuitry.
17
BOOT
18
TG_DDQ
Gate driver output for DDQ regulator high side N−channel power FET.
19
BG_DDQ
Gate driver output for DDQ regulator low side N−channel power FET.
20
SW_DDQ
DDQ regulator switch node and current limit sense input.
21
TH_PAD
Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane
under the IC.
Gate drivers input supply, which is monitored by undervoltage lock out circuitry, and a boost capacitor
is connected between SWDDQ and this pin.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
5VDUAL
−0.3, 6.0
V
Gate Drive (Pins 11, 13), BOOT (Pin 17) to AGND (Pin 7)
Vs
−0.3, 14
V
Gate Drive (Pins 18, 19) to AGND (Pin 7)
Vg
−0.3 DC,
−4.0 for 100 ns; 14
V
Input/Output Pins to AGND (Pin 7)
Pins 1−3, 5−6, 8−10, 12, 14−15, 20
VIO
−0.3, 6.0
V
PGND (Pin 4) to AGND (Pin 7)
VGND
−0.3, 0.3
V
Thermal Characteristics
QFN−20 Plastic Package
Thermal Resistance, Junction−to−Air
RJA
35
°C/W
Operating Junction Temperature Range
TJ
0 to +150
°C
Operating Ambient Temperature Range
TA
0 to +70
°C
Storage Temperature Range
Tstg
− 55 to +150
°C
Moisture Sensitivity Level
MSL
2.0
Power Supply Voltage (Pin 16) to AGND (Pin 7)
1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) 2.0 kV per JEDEC standard:
JESD22–A114. Machine Model (MM) 200 V per JEDEC standard: JESD22–A115. Except 11 and 13 pins, which are 150 V.
2. Latch–up Current Maximum Rating: 150 mA per JEDEC standard: JESD78.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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NCP5209
ELECTRICAL CHARACTERISTICS (5VDUAL = 5.0 V, BOOT = 12 V, 5VATX = 5.0 V, DDQ_REF = 2.5 V, TA = 0 to 70°C, L = 1.7 H,
COUT1 = 3770 F, COUT2 = 470 F, COUT3 = 680 F, COUT4 = 3300 F, CSS = 33 nF, RL1 = 50 k, R1 = 2.2 k, R2 = 2.0 k,
R3 = 0 , R4 = 1.0 k, R5 = 10 k, R6 = 5.0 k, R7 = 6.8 k, R8 = 7.5 k, RSWDDQ = 1.0 k, RZ1 = 20 k, RZ2 = 8.0 , CP1 = 10 nF,
CZ1 = 6.8 nF, CZ2 = 100 nF, for min/max values unless otherwise noted.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
5VDUAL Operating Voltage
V5VDUAL
(Note 3)
4.5
5.0
5.5
V
OCDDQ Operating Voltage
VOCDDQ
(Note 3)
−
5.0
5.5
V
VBOOT
(Note 3)
−
12
13.2
V
S0 Mode Supply Current from 5VDUAL
I5VDL_S0
BUF_CUT = LOW,
BOOT = 12 V, 5VATX = 5.0 V
−
−
8.0
mA
S3 Mode Supply Current from 5VDUAL
I5VDL_S3
BUF_CUT = HIGH, 5VATX = 0 V
−
−
5.0
mA
S5 Mode Supply Current from 5VDUAL
I5VDL_S5
BUF_CUT = LOW, 5VATX = 0 V
−
−
1.0
mA
S0 Mode Supply Current from BOOT
IBOOT_S0
BUF_CUT = LOW, BOOT = 12 V,
5VATX = 5.0 V
−
−
50
mA
S3 Mode Supply Current from BOOT
IBOOT_S3
BUF_CUT = HIGH,
5VATX = 0 V
−
−
25
mA
5VDUAL UVLO Upper Threshold
V5VDLUV+
−
−
−
4.4
V
5VDUAL UVLO Hysteresis
V5VDLhys
−
−
300
−
mV
BOOT UVLO Upper Threshold
VBOOTUV+
−
−
−
10.3
V
BOOT UVLO Hysteresis
VBOOThys
−
−
1.0
−
V
OCDDQ UVLO Upper Threshold
OCDDQUV+
−
−
−
1.5
V
OCDDQ UVLO Hysteresis
OCDDQhys
−
−
200
−
mV
Tsd
(Note 3)
−
145
−
°C
Tsdhys
(Note 3)
−
25
−
°C
VFBQ
TA = 25°C
TA = 0 to 70°C
1.178
1.166
1.190
1.202
1.214
V
IDDQfb
V(FBDDQ) = 1.3 V
−
−
1.0
A
Oscillator Frequency in S0 Mode
FDDQS0
−
217
250
283
kHz
Oscillator Frequency in S3 Mode
FDDQS3
−
434
500
566
kHz
SUPPLY VOLTAGE
BOOT Operating Voltage
SUPPLY CURRENT
UNDERVOLTAGE MONITOR
THERMAL SHUTDOWN
Thermal Shutdown
Thermal Shutdown Hysteresis
DDQ SWITCHING REGULATOR
FBDDQ Feedback Voltage,
Control Loop in Regulation
Feedback Input Current
Oscillator Ramp Amplitude
dVOSC
(Note 3)
−
1.3
−
Vp−p
OCDDQ Pin Current Sink
IOCDDQ
V(OCDDQ) = 3.0 V
28
40
52
A
Current Limit Blanking Time in S0 Mode
TDDQbk
(Note 3)
400
−
−
ns
Minimum Duty Cycle in S0 Mode
DS0min
(Note 3)
0
−
−
%
Maximum Duty Cycle in S0 Mode
DS0max
(Note 3)
−
−
100
%
Minimum Duty Cycle in S3 Mode
DS3min
(Note 3)
0
−
−
%
Maximum Duty Cycle in S3 Mode
DS3max
−
−
−
90
Iss1
V(SS) = 0 V
Soft−Start Pin Current for DDQ
3. Guarantee by design, not tested in production.
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5
2.0
%
A
NCP5209
ELECTRICAL CHARACTERISTICS (5VDUAL = 5.0 V, BOOT = 12 V, 5VATX = 5.0 V, DDQ_REF = 2.5 V, TA = 0 to 70°C, L =
1.7 H, COUT1 = 3770 F, COUT2 = 470 F, COUT3 = 680 F, COUT4 = 3300 F, CSS = 33 nF, RL1 = 50 k, R1 = 2.2 k, R2 = 2.0
k, R3 = 0 , R4 = 1.0 k, R5 = 10 k, R6 = 5.0 k, R7 = 6.8 k, R8 = 7.5 k, RSWDDQ = 1.0 k, RZ1 = 20 k, RZ2 = 8.0 , CP1 =
10 nF, CZ1 = 6.8 nF, CZ2 = 100 nF, for min/max values unless otherwise noted.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
DC Gain
GAINDDQ
(Note 4)
−
70
−
dB
Gain−Bandwidth Product
GBWDDQ
COMP PIN to GND = 220 nF, 1.0 in
Series (Note 4)
−
12
−
MHz
SRDDQ
COMP_DDQ = 10 pF
−
8.0
−
V/s
dVTTS0
IOUT= 0 to 2.0 A (Sink Current)
IOUT= 0 to –2.0 A (Source Current)
−30
−
30
mV
ILIMVTsrc
−
2.0
−
−
A
DDQ ERROR AMPLIFIER
Slew Rate
VTT ACTIVE TERMINATION REGULATOR
VTT Tracking REF_SNS/2 at S0 Mode
VTT Source Current Limit
VTT Sink Current Limit
ILIMVTsnk
−
2.0
−
−
A
RDDQ_REF
−
−
50
−
k
1st Regulator Feedback Voltage,
Control Loop in Regulation
VFB2P4
TA = 0°C to 70°C
0.784
0.800
0.816
V
1st Regulator Feedback Input Current
IFB2P4
−
−
−
1.0
A
1st Regulator DC Gain
GAIN2P4
(Note 4)
−
66
−
dB
2nd Regulator Feedback Voltage,
Control Loop in Regulation
VFB1P5
TA = 0°C to 70°C
0.784
0.800
0.816
V
2nd Regulator Feedback Input Current
IFB1P5
−
−
−
1.0
A
GAIN1P5
(Note 4)
−
66
−
dB
Tss2
−
−
1.5
−
ms
BUF_CUT Input Logic HIGH
Logic_H
−
2.0
−
−
V
BUF_CUT Input Logic LOW
Logic_L
−
−
−
0.8
V
ILogic
−
−
−
1.0
A
TGDDQ Gate Pull−HIGH Resistance
RH_TG
BOOT = 12 V, V(TGDDQ) = 11.9 V
−
3.0
−
TGDDQ Gate Pull−LOW Resistance
RL_TG
BOOT = 12 V, V(TGDDQ) = 0.1 V
−
2.5
−
BGDDQ Gate Pull−HIGH Resistance
RH_BG
BOOT = 12 V, V(BGDDQ) = 11.9 V
−
3.0
−
BGDDQ Gate Pull−LOW Resistance
RL_BG
BOOT = 12 V, V(BGDDQ) = 0.1 V
−
1.3
−
DRV_2P4 Gate Pull−HIGH Voltage
VH2P4
BOOT = 12 V
−
9.0
−
V
DRV_2P4 Gate Pull−LOW Voltage
VL2P4
BOOT = 12 V
−
0.8
−
V
DRV_2P4 Gate Source Current
IH2P4
BOOT = 12 V
−
10
−
mA
DRV_2P4 Gate Sink Current
IL2P4
BOOT = 12 V
−
10
−
mA
DRV_1P5 Gate Pull−HIGH Voltage
VH1P5
BOOT = 12 V
−
9.0
−
V
DRV_1P5 Gate Pull−LOW Voltage
VL1P5
BOOT = 12 V
−
0.8
−
V
DRV_1P5 Gate Source Current
IH1P5
BOOT = 12 V
−
10
−
mA
DRV_1P5 Gate Sink Current
IL1P5
BOOT = 12 V
−
10
−
mA
DDQ_REF Input Resistance
DUAL LINEAR REGULATOR CONTROLLER
2nd Regulator DC Gain
Internal Soft−Start Timing
CONTROL SECTION
BUF_CUT Input Current
GATE DRIVERS
4. Guarantee by design, not tested in production.
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NCP5209
TYPICAL OPERATING CHARACTERISTICS
550
SWITCHING FREQUENCY (kHz)
VFBQ, FEEDBACK VOLTAGE (V)
1.194
1.193
1.192
1.191
1.190
1.189
500
S3 Mode
450
400
350
S0 Mode
300
250
200
1.188
0
20
40
60
0
80
20
VFB1P5, 2ND REGULATOR FEEDBACK VOLTAGE (V)
0.8025
0.8020
0.8015
0.8010
0.8005
0.8000
0.7995
0.7990
0
20
40
40
60
80
TA, AMBIENT TEMPERATURE (°C)
0.8025
0.8020
0.8015
0.8010
0.8005
0.8000
0.7995
0
20
40
60
TA, AMBIENT TEMPERATURE (°C)
Figure 6. VFB1P5 2nd Regulator Feedback
Voltage vs. Ambient Temperature
−5.0
2 A Sourcing
Current with 10 ms
period and 2 ms
pulse width
−5.5
−6.0
−6.5
−7.0
−7.5
−8.0
−8.5
0
80
Figure 4. Oscillation Frequency in S0/S3
vs. Ambient Temperature
Figure 5. VFB2P4 1st Regulator Feedback
Voltage vs. Ambient Temperature
−9.0
60
TA, AMBIENT TEMPERATURE (°C)
Figure 3. VFBQ Feedback Voltage
vs. Ambient Temperature
VTT, SOURCE CURRENT LOAD REGULATION
(mVp−p)
VFB2P4, 1ST REGULATOR FEEDBACK VOLTAGE (V)
TA, AMBIENT TEMPERATURE (°C)
20
40
60
80
TA, AMBIENT TEMPERATURE (°C)
Figure 7. VTT Source Current Load Regulation
vs. Ambient Temperature
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7
80
NCP5209
0.015
21.0
VTT, OUTPUT VOLTAGE (VDDQ/2V)
VTT, SINK CURRENT LOAD REGULATION (mVp−p)
TYPICAL OPERATING CHARACTERISTICS
20.5
20.0
19.5
2 A Sourcing
Current with 10 ms
period and 2 ms
pulse width
19.0
18.5
18.0
0
20
40
60
80
0.010
0.005
0
Sourcing/Sin king
current with 10 ms
period and 2 ms
pulse width
−0.005
−0.010
−0.015
−0.020
−2.5
TA, AMBIENT TEMPERATURE (°C)
Figure 8. VTT Sink Current Load Regulation
vs. Ambient Temperature
−1.5
−0.5
0.5
1.5
IVTT, OUTPUT LOAD CURRENT (A)
2.5
Figure 9. VTT Output Voltage vs. Load Current
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NCP5209
TYPICAL OPERATING WAVEFORMS
288 mA applies
to V1P5
Channel 1: VDDQ output voltage, 1.0 V/div
Channel 2: VTT output voltage, 1.0 V/div
Channel 3: V1P5 output voltage, 1.0 V/div
Time base: 5.0 ms/div
Channel 1: BUF_CUT pin voltage, 5.0 V/div
Channel 2: VDDQ output voltage, AC−coupled, 50 mV/div
Channel 3: VTT output voltage, AC−coupled, 200 mV/div
Channel 4: V1P5 output voltage, 1.0 V/div
Time base: 10 ms/div
Figure 10. Power Up Sequence
Figure 11. S0−S3−S0 Transition
Channel 1: Current sourced out of VTT, 2.0 A/div
Channel 2: VDDQ output voltage, AC−coupled, 50 mV/div
Channel 3: VTT output voltage, AC−coupled, 20 mV/div
Channel 4: V1P5 output voltage, AC−coupled, 50 mV/div
Time base: 200 s/div
Channel 1: Current sunk into of VTT, 2.0 A/div
Channel 2: VDDQ output voltage, AC−coupled, 50 mV/div
Channel 3: VTT output voltage, AC−coupled, 20 mV/div
Channel 4: V1P5 output voltage, AC−coupled, 50 mV/div
Time base: 200 s/div
Figure 12. VTT Source Current Transient, 0A − 2A – 0A
Figure 13. VTT Sink Current Transient, 0A − 2A − 0A
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NCP5209
TYPICAL OPERATING WAVEFORMS
Channel 1: Current sourced into of VDDQ, 10 A/div
Channel 2: VDDQ output voltage, AC−coupled, 100 mV/div
Channel 3: VTT output voltage, AC−coupled, 100 mV/div
Channel 4: V1P5 output voltage, AC−coupled, 100 mV/div
Time base: 1.0 ms/div
Channel 1: Current sourced into of V1P5, 5.0 A/div
Channel 2: VDDQ output voltage, AC−coupled, 50 mV/div
Channel 3: VTT output voltage, AC−coupled, 100 mV/div
Channel 4: V1P5 output voltage, AC−coupled, 20 mV/div
Time base: 1.0 ms/div
Figure 15. V1P5 Source Current Transient,
0A – 7A – 0A
Figure 14. VDDQ Source Current Transient,
0A – 20A – 0A
Channel 1: Current sourced into of VDDQ, 2.0 A/div
Channel 2: VDDQ output voltage, AC−coupled, 10 mV/div
Time base: 1.0 ms/div
Figure 16. S3 Mode without 12VATX, 0A – 2A – 0A
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NCP5209
DETAILED OPERATION DESCRIPTIONS
General
diagram is shown in Figure 18. Table 1 summarizes the
operating states of all regulators and the conditions of output
pins.
The NCP5209 4−In−1 PWM Buck and Tri−Linear DDR
Power Controller contains a high efficiency PWM
controller, an integrated two−quadrant linear regulator and
two linear regulator controllers.
The VDDQ supply is generated by a PWM controller
driving two external N−Ch FETs. The VTT termination
voltage is tracked by an integrated linear regulator with
sourcing and sinking current capability which tracks at 1/2
VDDQ. The dual linear controllers driving two external
N−Ch FETs can either be cascaded to create the MCH core
voltage or work independently to produced two regulated
output voltages. All regulator outputs are adjustable.
The inclusion of soft−start, supply undervoltage monitors,
overcurrent protection and thermal shutdown, makes this
device a complete power solution for the MCH and DDR
memory system. This device is housed in thermal enhanced
space−saving QFN−20 package.
Internal Bandgap Voltage Reference
An internal bandgap reference is generated whenever
5VDUAL exceeds 2.7 V. Once this bandgap reference is in
regulation, an internal signal _VREFGD is asserted to wake
up the ACPI logic.
S5−To−S0 Mode Power Up Sequence
The ACPI control logic is enabled by the assertion of
VREFGD. Once the ACPI control is activated, the
power−up sequence starts by waking up the 5VDUAL
voltage monitor block and reference current generator first.
If the 5VDUAL is within the preset level, the BOOT and
OCDDQ undervoltage monitor blocks are enabled to detect
the presence of 12VATX and 5VATX supplies. When the
three supplies are in regulation and BUFCUT is LOW the
device enters S0 mode by activating the soft−start of DDQ
switching regulator.
Once the DDQ regulator is in regulation and the soft−start
interval is completed, the _INREGDDQ signal is asserted
HIGH to enable the VTT regulator as well as the dual linear
controllers.
ACPI Control Logic
The ACPI control logic powered by the 5VDUAL supply
input. External control is applied to the high impedance
CMOS input labeled BUF_CUT. This signal and three
internal undervoltage detectors are used to determine the
operating mode according to the state diagram in Figure 19.
The 5VDUAL supply must be come up before the other
supplies.
The UVLOs monitor the motherboard supplies
5VDUAL, 12VATX and 5VATX through 5VDUAL, BOOT
and OCDDQ pins respectively. Three control signals,
_5VDUALGD, _BOOTGD and _OCDDQGD, are asserted
when the supply voltages are in good condition.
The device is powered up initially in the S5 shutdown
mode to minimize the power consumption. When all three
supplies are good with BUF_CUT is LOW, the device enters
S0 normal operating mode.
Transition of BUF_CUT from LOW to HIGH in S0 mode
triggers the device into S3 sleep mode. In S3 mode, external
12VATX and 5VATX supplies collapse and only DDQ
regulator is working. Both BOOT_UVLO and
5VATX_UVLO work specially. Two control signals,
_BOOTGD and _OCDDQGD go low and the IC remains in
the S3 mode.
During S3 mode, the transition of BUF_CUT from HIGH
to LOW triggers the device back to S0 mode providing
12VATX and 5VATX are good. The IC can re−enter S5 mode
from S0 mode by removing one of the supplies. Transitions
from S3 to S5 or vice versa are not allowed. A timing
DDQ Switching Regulator
The DDQ regulator in S0 mode is a synchronous buck
controller that drives two external power N−Ch FETs to
supply up to 20 A. It employs the voltage mode fixed
frequency PWM control scheme with external
compensation switching at 250 kHz 13.2%. As shown in
Figure 2, the VDDQ output voltage is divided down and fed
back to the inverting input of an amplifier through FBDDQ
pin to close the loop at VDDQ = VFBQ × (1 + R1/R2). This
amplifier compares the feedback voltage with an internal
reference voltage VREF1 (= 1.190 V) to generate an error
signal for the PWM comparator. This error signal is further
compared with a fixed frequency RAMP waveform to
generate a PWM signal. This PWM signal drives the
external N−Ch FETs via the TG_DDQ and BG_DDQ pins.
External inductor L and capacitor COUT1 filter the output
voltage. When the NCP5209 leaves S5 mode, the VDDQ
output voltage ramps up at a rate controlled by the capacitor
at SS pin. When the regulation of VDDQ is regulating in S0
mode, a signal _INREGDDQ goes HIGH.
In S3 standby mode, the switching frequency is doubled
to reduce the conduction loss in the external N−Ch FETs.
Table 1. Mode, Operation and Output Pin Condition
Operating Conditions
S0
S3
S5
DDQ
Normal
Standby
OFF
VTT
Normal
H−Z
H−Z
Output Pin Conditions
Dual Linear
Normal
H−Z
H−Z
TGDDQ
Normal
Standby
Low
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BGDDQ
Normal
Standby
Low
DRV_2P4
Normal
Low
Low
DRV_1P5
Normal
Low
Low
NCP5209
Tolerance of VDDQ
Dual Linear Regulator Controllers
Both the tolerance of VFBDDQ and the ratio of external
resistor divider R1/R2 impact the precision of VDDQ. With
the control loop in regulation, VDDQ = VFBQ × (1 +
R1/R2). With a worst case (for all valid operating
conditions) VFBDDQ tolerance of 1.5%, a worst case
range of 2% for VDDQ can be assured if the ratio R1/R2
is specified as 1.100 1%.
The dual linear regulators are formed by two high−gain
controllers driving external N−Ch FETs. They are activated
after the DDQ regulator is in regulation in S0 mode. The
output voltage of each regulator is fed back through an
external resistor divider. The feedback voltage is compared
to an internal reference voltage VREF2 (= 0.800 V) to
achieve voltage regulation.
Both linear regulators use a common soft−start ramping
voltage set to 1.5 ms. Once they are activated, hiccup mode
is employed during the soft−start period to protect them
against short circuit or power failure conditions. In the
soft−start interval, the feedback voltages of both regulators
are compared with the soft−start ramping voltage. If either
one of feedback voltages is 100 mV below the SS ramping
voltage, a short circuit or power failure condition is detected,
causing both regulators to be reset and initiate the soft−start
sequence again, as depicted in Figure 17. This hiccup mode
feature is disabled once after both outputs are in regulation.
Fault Protection of VDDQ Regulator
In S0 mode, an external resistor (RL1) connecting the
5VATX supply to the OCDDQ pin sets the current limit for
the high−side switch. An internal 40 A current sink at the
OCDDQ pin establishes a voltage drop across this resistor.
The inductor node voltage is sensed at the SWDDQ pin
through a protective resistor (RSWDDQ). The voltage at
OCDDQ pin is compared to the voltage at SWDDQ pin
when the high−side FET is turned on after a fixed period of
blanking time thus avoiding false current limit triggering. If
the voltage at SW_DDQ is lower than that at OCDDQ, an
overcurrent condition occurs, during which, all regulators
are latched off to protect against overcurrent. The IC can be
powered up again only if any one of supply voltages
(5VDUAL, 12VATX or 5VATX) is recycled or the SS−pin
is discharged to ground externally.
Since the OCDDQ pin is also used for detecting 5VATX
power supply, the upper threshold of the 5VATX UVLO is
set to 1.25 V. Therefore, RL1 must be selected in such a way
that the voltage at the OCDDQ pin must be higher than this
threshold to avoid false triggering of UVLO.
In S3 mode, this overcurrent protection feature is
disabled.
3.3VATX
_INREGDDQ
DRV_1P5
V1P5
Feedback Compensation of VDDQ Regulator
The compensation network is shown in Figure 2.
V1P5 Loading
VTT Active Terminator
The VTT active terminator is a two quadrant linear
regulator with two internal N−Ch FETs to provide current
sink and source capability up to 2.0 A. It is activated only
when the VDDQ regulator is in regulation in S0 mode. It
draws power from VDDQ with the internal gate drive power
derived from 5VDUAL. While the VTT output is directly
connected to the FBVTT pin, the VTT voltage is designed
to automatically track at the half of the DDQ_REF voltage.
This VTT voltage can be adjusted by using an external
resistor divider in the feedback loop. This regulator is stable
with any value of output capacitor greater than 470 F, and
is insensitive to ESR ranging from 1.0 m to 400 m.
Figure 17. Hiccup Mode Soft−Start of Dual Linear
Regulators
These two linear regulators can be cascaded to generate
the 1.5 V MCH core voltage with 2.4 V as the intermediate
voltage. By using 3.3 VATX as the power supply of external
N−Ch FETs, up to 7.0 A can be delivered.
If only one linear regulator is used, it is recommended to
pull the feedback pin of the unused regulator to 5VDUAL to
reduce the internal power consumption as well as to avoid
soft−start issue.
Fault Protection of VTT Active Terminator
To provide protection for the internal FETs, a
bidirectional current limit set to 2.4 A is implemented. The
VTT current limit provides a soft−start function during
startup.
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NCP5209
Fault Protection of Dual Linear Regulator
Thermal Consideration
Internal soft−start is built−in to limit the in−rush current.
Assuming an ambient temperature of 50C, the maximum
allowed dissipated power of the QFN−20 package is 2.8 W,
which is enough to handle the internal power dissipation in
S0 mode. To take full advantage of the thermal capability
of this package, the exposed pad underneath must be
soldered directly onto a PCB metal substrate to allow
good thermal contact.
BOOT Pin Supply Voltage
In a typical application, a flying capacitor is connected
between the inductor LX node and the BOOT pin. In S0
mode, the 12VATX supply is tied to the BOOT pin through
a Schottky diode. A 13 V Zener diode must be put as close
to the BOOT pin as possible to clamp the boot strapping
voltage produced by the flying capacitor.
In S3 mode the 12VATX supply is collapsed. The BOOT
voltage is created by the Schottky diode between 5VDUAL
and BOOT pins and the flying capacitor. The BOOT_UVLO
works in the special case. The _BOOTGD goes low and the
IC remains in S3 mode.
Thermal Shutdown
When the junction temperature of the IC exceeds 145C,
the entire IC is shutdown. When the junction temperature
drops below 120C, the chip resumes normal operation.
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NCP5209
POWER UP AND POWER DOWN TIMING
5VSTBY
or
5VDUAL
12 V
5V
BUF_CUT
Switching Frequency
Doubles
DDQ−S0
VTT
Dual Lin
State
1
2
3
4
5
6
7
8
9
10
S0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
11 12 13 14
S3
15
S0
16 17
18
S5
5VSTBY or 5VSTB is ultimate chip enable. This supply has to be up first to ensure gates are in known state.
12 and 5.0 V supplies can ramp in either order.
DDQ ramps up with timing set by the SS pin.
MCH and VTT both ramp once DDQ SS is completed and DDQ is within 90% of regulated value.
S0 mode.
Prepare S3 Mode −− BUF_CUT goes HIGH.
VTT and MCH turn off.
12 V and 5.0 V ramp down.
Standard S3 mode.
12 V and 5.0 V ramp back to regulation.
BUF_CUT goes LOW.
DDQ switches back to 250 kHz.
MCH and VTT ramp up again.
S0 mode.
Prepare S5 mode −− 12VUVLO = H OR 5VUVLO = H.
DDQ, VTT and MCH turn off.
S5 mode.
Figure 18. Timing Diagram
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NCP5209
S5
BUF_CUT = 0 AND
_BOOTGD = 1 AND
_OCDDQGD = 1
BUF_CUT = 0 AND
(_BOOTGD = 0 OR
_OCDDQGD = 0)
S0
BUF_CUT = 1
BUF_CUT = 0 AND
_BOOTGD = 1 AND
_OCDDQGD = 1
S3
Note: 5VDUAL is assumed to be in good condition in any mode.
All possible state transitions are shown.
All unspecified inputs do not cause any state change.
Figure 19. State Transitions Diagram of NCP5209
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12VATX
5VDUAL
L1
1 H
TP1
R6
8
C9
100 nF
R5
2.2 k
VDDQ
+C11
4.7 F
C8
10 nF
C10
R7
6.8 nF 20 k
2
3
5
VDDQ
D1
BAT54HT1
D2
BAT54HT1
6
7
COMP_DDQ SW_DDQ
FBDDQ
BG_DDQ
SS
TG_DDQ
PGND
BOOT
VTT
5VDUAL
VDDQ
OCDDQ
AGND
SGND 8
FBVTT
VDDQ 9
DDQREF
C20
10
470 F
FB1P5
20
R2
4.7
19
18
17
4
Q1
40N03R
DPAK
1
3
R3
15 OCDDQ
14 BUF_CUT
BUF_CUT
13
DRV_2P4
12
FB2P4
11
C21
DRV_1P5
100 F
1k
R4
DPAK
4.7
1
TP3
VDDQ
C6
4.7 F
4
Q2
40N03R
AGND to
PGND
3
2.5
VDDQ
+C7
2200 F
+C3
2200 F
TP4
4
C12
4.7 F
+C13
470 F
L2
1.8 H
16 5VDUAL
VTT
1.25
VTT
C4
22 nF
+C5
470 F
ZENER
MMSZ13T1
Q4
40N03R
1
R15
50
3.3 V
C15
2200 F
3
TP7
R10
Vref = 800 mV
+C2
470 F
33 k
R1
51 k
2.4 V
4
1
Q5
40N03R
C16
4.7 F
+C17
470 F
3
Vref = 800 mV
TP6 5ATX
R9
TP8
R11
13 k
OCDDQ
51 k
R12
16 k
SGND
R13
16 k
C18
4.7 F
+C19
2200 F
+C6
2200 F
1.5
VMCH
TP9
SGND
GND
AGND to PGND
SGND
Figure 20. NCP5209 Typical Application Circuit
NCP5209
16
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SGND
TP5
4
C14
33 nF
SGND
+C1
3300 F
U1
1
+
TP2
NCP5209
Vref = 1.20 V
R8
2k
Filtered
5VDUAL
5VDUAL
NCP5209
Application Circuit
Switcher Power MOSFET Selection
Figure 20 shows the typical application circuit for
NCP5209. NCP5209 is specifically designed as a total
power solution for the MCH and DDR memory system. This
diagram contains NCP5209 for driving two external N−Ch
FETs to form the DDR memory supply voltage (VDDQ) and
two external N−Ch FETs to form the MCH regulator.
Power MOSFETs are chosen by balancing the cost with
the requirements for the current load of the memory system
and the efficiency of the converter provided. The selections
criteria can be based on drain−source voltage, drain current,
on−resistance RDS(on) and input gate capacitance. Low
RDS(on) and high drain current power MOSFETs are usually
preferred to achieve the high current requirement of the
DDR memory system, as well as the high efficiency of the
converter. The tradeoff is a corresponding increase in the
input gate capacitor of the power MOSFET.
Output Inductor Selection
The value of the output inductor is chosen by balancing
ripple current with transient response capability. A value of
1.7 H will yield about 3.0 A peak−to−peak ripple current
when converting from 5.0 V to 2.5 V at 250 KHz. It is
important that the rated inductor current is not exceeded
during full load, and that the saturation current is not less
than the expected peak current. Low ESR inductors may be
required to minimize DC losses and temperature rise.
PCB Layout Considerations
With careful PCB layout the NCP5209 can supply 20 A or
more of current. It is very important to use wide traces or
large copper shapes to carry current from the input node
through the MOSFET switches, inductor and the output
filters and load. Reducing the length of high current nodes
will reduce losses and reduce parasitic inductance. It is
usually best to locate the input capacitors the MOSFET
switches and the output inductor in close proximity to
reduce DC losses, parasitic inductance losses and radiated
EMI.
The sensitive voltage feedback and compensation
networks should be placed near the NCP5209 and away
from the switch nodes and other noisy circuit elements.
Placing compensation components near each other will
minimize the loop area and further reduce noise
susceptibility.
Input Capacitor Selection
Input capacitors for PWM power supplies are required to
provide a stable, low impedance source node for the buck
regulator to convert from. The usual practice is to use a
combination of electrolytic capacitors and multi−layer
ceramic capacitors to provide bulk capacitance and high
frequency noise suppression. It is important that the
capacitors are rated to handle the AC ripple current at the
input of the buck regulators, as well as the input voltage.
Output Capacitor Selection
Output capacitors are chosen by balancing the cost with
the requirements for low output ripple voltage and transient
voltage. Low ESR electrolytic capacitors can be effective at
reducing ripple voltage at 250 KHz. Low ESR ceramic
capacitors are most effective at reducing output voltage
excursions caused by fast load steps of system memory and
the memory controller.
12VATX
TP2
Optional Boost Voltage Configuration
The charge pump circuit in Figure 21 can be used instead
of boost voltage scheme of Figure 20. The advantage in
Figure 21 is the elimination of the requirement for the Zener
clamp. The tradeoff is slightly less boost voltage and a
corresponding increase in MOSFET conduction losses.
5VDUAL
TP2
D2
BAT54HT1
D1
C27
100 nF
NCP5209
SW_DDQ 20
BG_DDQ 19
TG_DDQ 18
BOOT 17
5VDUAL 16
15
OCDDQ
BUF_CUT 14
DRV_2P4 13
12
FB2P4
11
D1
BAT54HT1
BAT54HT1
5VDUAL
4
R2
4.7 1
Q2
3 NTD40N03
L
R3
1k
R4
4.7
C4
2.2 nF
TP5
VDDQ
1
4 DPAK
Q2
NTD40N03
3
C6
4.7 F
DRV_1P5
Figure 21. Charge Pump Circuit at Boot Pin
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+ C7
2200 F
+ C25
2200 F
R15 2.5 VDDQ
50
NCP5209
Table 2. Bill of Material of NCP5209 Application Circuit
Ref Design
Q1, Q2, Q3, Q4
D1, D2
U1
Zener
Description
Value
Qty
Part #
Manufacturer
Power MOSFET N−Channel
25 V, 12.6 m, 40 A
4
NTD40N03R
ON Semiconductor
Rectifier Schottky Diode
30 V
2
BAT54HT1
ON Semiconductor
Controller
4−In−1 PWM Buck &
Tri−Linear Power
Controller
1
NCP5209
ON Semiconductor
Zener Diode
13 V, 0.5 W
1
MMSZ13T1
ON Semiconductor
L1
Toroidal Choke
1.0 H, 25 A
1
T60−26(6T)
−
L2
Toroidal Choke
1.8 H, 25 A
1
T50−26B(6T)
−
C1
Aluminum Electrolytic Capacitor
3300 F, 6.3 V
1
EEUFJ0J332U
Panasonic
C5
Aluminum Electrolytic Capacitor
470 F, 35 V
1
EEUFC1V471
Panasonic
C21
Aluminum Electrolytic Capacitor
100 F, 50 V
1
EEUFC1H101
Panasonic
C15
Aluminum Electrolytic Capacitor
2200 F, 10 V
1
EEUFC1A222L
Panasonic
C17, C20
Aluminum Electrolytic Capacitor
470 F, 16 V
2
EEUFC1C471
Panasonic
C13, C2
Aluminum Electrolytic Capacitor
470 F, 10 V
2
EEUFC1A471
Panasonic
C7, C3, C19, C6
Aluminum Electrolytic Capacitor
2200 F, 6.3 V
4
EEUFC0J222SL
Panasonic
C11, C6, C16,
C18, C12
Ceramic Capacitor
4.7 F, 6.3 V
5
ECJHVB0J475M
Panasonic
C4
Ceramic Capacitor
22 nF, 25 V
1
ECJ1VB1E223K
Panasonic
C10
Ceramic Capacitor
6.8 nF, 50 V
1
ECJ1VB1H682K
Panasonic
C9
Ceramic Capacitor
100 nF, 16 V
1
ECJ1VB1C104K
Panasonic
C8
Ceramic Capacitor
10 nF, 50 V
1
ECJ1VB1H103K
Panasonic
C14
Ceramic Capacitor
33 nF, 25 V
1
ECJ1VB1E333K
Panasonic
R2, R4
Resistor
4.7 2
−
−
R3
Resistor
1.0 k
1
−
−
R7
Resistor
20 k
1
−
−
R6
Resistor
8.2 1
−
−
R8
Resistor
2.0 k
1
−
−
R5
Resistor
2.2 k
1
−
−
R10
Resistor
33 k
1
−
−
R13, R12
Resistor
16 k
2
−
−
R11
Resistor
13 k
1
−
−
R15
Resistor
50 1
−
−
R1, R9
Resistor
51 k
2
−
−
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NCP5209
PACKAGE DIMENSIONS
QFN−20, DUAL−SIDED, 6x5 mm
MN SUFFIX
CASE 505AB−01
ISSUE O
A
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINALS AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
PIN 1 LOCATION
E
2X
0.15 C
DIM
A
A1
A2
A3
b
D
D2
E
E2
e
K
L
2X
0.15 C
0.10 C
A2
A
0.08 C
A1
(A3)
C
SEATING
PLANE
D2
20 X
L
20 X
e
1
10
E2
K
20
11
20 X
b
0.10 C A B
0.05 C
NOTE 3
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MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.65
0.75
0.20 REF
0.23
0.28
6.00 BSC
3.98
4.28
5.00 BSC
2.98
3.28
0.50 BSC
0.20
−−−
0.50
0.60
NCP5209
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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LITERATURE FULFILLMENT:
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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Order Literature: http://www.onsemi.com/litorder
Japan: ON Semiconductor, Japan Customer Focus Center
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Phone: 81−3−5773−3850
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For additional information, please contact your
local Sales Representative.
NCP5209/D
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