1.2A Switching Regulator, and 5.0 V 100mA Linear Regulator with RESETbar

CS2001
1.2 A Switching Regulator,
and 5.0 V, 100 mA Linear
Regulator with RESET
The CS2001 is a smart power supply ASIC utilized in automotive
airbag systems. It contains a current−mode switching regulator with a
1.2 A on−chip switch and a 5.0 V, 100 mA linear regulator. The linear
output capacitor must be 3.3 μF or greater with an ESR in the range of
100 mΩ to 1.0 Ω. If the ESR of the cap is less than 100 mΩ, a series
resistor must be used. The switcher can be configured in either a boost
or flyback topology. The boost topology produces energy reserve the
resistor divider connected to the VFB pin. In the event of fault voltage
VER which is externally adjustable (25 V maximum) through
conditions that produce VFB either open or shorted, the switcher is
shut down.
Under normal operating conditions (VBAT > 8.0 V), the current
loading on the linear regulator is directed through VBAT. A low battery
or loss of battery condition switches the supply for the linear regulator
from VBAT to VER and shuts down the switcher using the ASIC’s
internal smart switch. This switchover feature minimizes the power
dissipation in both the linear and switcher output devices and saves the
cost of using a larger inductor.
The NERD (No Energy Reserve Detected) pin is a dual function
output. If VOUT is not in regulation, it provides a Power On Reset
function whose time interval is externally adjustable with the
capacitor. This interval can be seen on the RESETB pin, which allows
for clean power−up and power−down of the microprocessor. Once
VOUT is in regulation, the logic level of the NERD output (usually
low) indicates to the microprocessor whether or not the VER pin is
connected.
A switched−capacitor voltage tripler accepts input voltage VER and
produces output voltage VCHG (typically VER + 8.0 V). This voltage
is used in the system to drive high−side FETs.
This part is capable of withstanding a 50 V peak transient voltage.
The linear regulator will not shut down during this event.
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SO−20L
DWF SUFFIX
CASE 751D
20
1
MARKING DIAGRAM
20
CS2001
AWLYYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
VER
VBAT
VFB
GND1
GND2
GND3
GND4
VSW
SWSD
COMP
1
20
VOUT
RESETB
NERD
GND8
GND7
GND6
GND5
VCHG
IBIAS
CPUMP
Features
•
•
•
•
•
•
Linear Regulator 5.0 V ±2% @ 100 mA
Switching Regulator 1.2 A Peak Internal Switch
Voltage Tripler
Smart Functions
− Smartswitch
− RESET
− Energy Reserve Status
Protection
− Overtemperature
− Current Limit
− 50 V Peak Transient Capability
Internally Fused Leads in SO−20L Package
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 6
ORDERING INFORMATION
Device
1
Package
Shipping
CS2001YDWF20
SO−20L
37 Units/Rail
CS2001YDWFR20
SO−20L
1000 Tape & Reel
Publication Order Number:
CS2001/D
CS2001
Microprocessor
100 μF
68 μH
VOUT
RESETB
NERD
VER
VBAT
VFB
GND1
1.0 k
95.3 k
VSW
Reserve
Firing
Voltage
VIGN
1000 μF
1000 μF
ESR
GND2
GND7
CS2001
GND3
GND6
GND4
5.1 k
GND8
GND5
VCHG
SWSD
IBIAS
COMP
CPUMP
11 k
Tripler
Firing
Voltage
30.1 k
270 pF
1.0 μF
0.1 μF
1.0 μF
0.47 μF
10 μF
Figure 1. Application Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
VBAT
−0.5 to 25
V
VER
−0.5 to 25
V
VOUT
−0.5 to 7.0
V
Digital Input/Output Voltage
−0.5 to 7.0
V
50
V
−55 to 150
°C
Junction to Free Air Thermal Impedance
55
°C/W
ESD Susceptibility (Human Body Model)
4.0
kV
230 peak
°C
TA
−40 to 85
°C
TJ
−40 to 150
°C
Peak Transient Voltage (36 V Load Dump @ 14 V Battery Voltage)
Storage Temperature Range
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
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2
CS2001
ELECTRICAL CHARACTERISTICS (8.0 V ≤ VBAT ≤ 16 V, 8.0 V ≤ VER ≤ 25 V, 1.0 mA ≤ IV(OUT) ≤ 100 mA,
TTEST = −40°C to 125°C; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
4.9
4.9
−
−
5.1
5.1
V
V
Linear Regulator
Output Voltage
Output Driven from VBAT, VER = 25 V
Output Driven from VER, VBAT = 0 V
Regulator Bias Current (from VBAT)
IV(BAT) @ IV(OUT) = −100 mA,
SWSD = 4.0 V, VBAT = 16 V, VER = 25 V
T = −40°C
T = 25°C
T = 125°C
−
−
−
−
−
−
8.0
7.0
6.0
mA
mA
mA
IVER @ IV(OUT) = −100 mA,
SWSD = 4.0 V, VBAT = 0 V, VER = 25 V
T = −40°C
T = 25°C
T = 125°C
−
−
−
−
−
−
11
9.0
8.0
mA
mA
mA
Dropout Voltage VBAT − VOUT
VER = 25 V, IV(OUT) = −100 mA (Probe Only)
−
−
1.5
V
Dropout Voltage VER − VOUT
VBAT = 0 V, IV(OUT) = −100 mA
−
−
1.5
V
Smart Switch Threshold
VBAT to VER
VER = 25 V, IV(OUT) = −50 mA
6.5
−
8.0
V
Smart Switch Threshold Hysteresis
VER = 25 V, IV(OUT) = −50 mA
0.5
−
1.0
V
VOUT Output Noise
VBAT = 16 V, VER = 25 V, IV(OUT) = − 1.0 mA,
C = 10 μF, ESR = 0.5 Ω
−
−
0.05
V
Line Regulation
−
−
−
0.025
V
Load Regulation
−
−
−
0.025
V
Output Current Limit
−
120
−
−
mA
135
150
165
kHz
Regulator Bias Current (from VER)
Switching Regulator
VER = 25V, IV(OUT) = −1.0 mA
Switching Frequency
CPUMP 270 pF, RI(BIAS) = 30.1 kΩ
Pump Drive Current
ΔIV(BAT) for 0 A ≤ IV(SW) ≤ 1.2 A
−
−
50
mA
Switch Saturation Voltage
IV(SW) = 1.2 A
−
−
1.6
V
Output Current Limit
−
1.2
−
2.4
A
VFB Regulation
−
1.238
1.27
1.303
V
−
−
1.0
μA
VFB Input Current
VFB Above Short Low Detection Level
VFB Input Shorted Low Detection
Level
−
200
250
300
mV
CPUMP Short Detection Threshold
−
200
250
300
mV
Maximum Duty Cycle
−
80
−
95
%
−
−
100
μA
VSW Leakage Current
Voltage Tripler
IV(SW) @ VSW = 50 V, SWSD = VOUT
VBAT = 16 V, IV(OUT) = −1.0 mA, CCHG = 1.5 mF
Output Voltage Clamp
VCHG − VER
VER = 8.0 V, IV(CHG) = −30 μA
VER = 12 V, IV(CHG) = −90 μA
6.25
6.25
8.0
8.0
13
13
V
V
Initial Charge Time
CCHG = 0.15 μF, VER = 8.0 V,
VCHG = 14.25 V
−
−
30
ms
25
32.5
40
V
25
32.5
40
V
−
−
3.0
mA
Maximum Output Voltage Clamp
VCHG
Output Voltage Clamp VCHG
Short Circuit Path Current Limit VER
to VCHG
−
VER = 28 V, IV(CHG) = 0 μA
−
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3
CS2001
ELECTRICAL CHARACTERISTICS (continued) (8.0 V ≤ VBAT ≤ 16 V, 8.0 V ≤ VER ≤ 25 V, 1.0 mA ≤ IV(OUT) ≤ 100 mA,
TTEST = −40°C to 125°C; unless otherwise specified.)
Characteristic
RESETB OUTPUT
Test Conditions
Min
Typ
Max
Unit
VBAT = 0 V
High Threshold
VOUT Increasing
4.525
4.75
4.85
V
Low Threshold
VOUT Decreasing
4.5
4.65
4.825
V
25
100
200
mV
Hysteresis
−
Output Low Voltage
VOUT = 1.0 V, IRESETB = 100 μA
IRESETB = 1.0 mA, VOUT = 4.5 V
−
−
−
−
0.5
0.5
V
V
Pull−Up Resistor
RESETB = 1.0 V
25
50
100
kΩ
SWSD Input
VBAT = 16 V, VER = 25 V, IV(OUT) = −1.0 mA
High Threshold
−
−
−
0.7 × VOUT
V
Low Threshold
−
0.3 × VOUT
−
−
V
10
20
40
kΩ
1.5
−
6.5
V
Input Impedance
NERD OUTPUT
Referenced to Ground
VBAT = 16 V, IV(OUT) = −1.0 mA, CNERD = 0.47 mF
−
VER Detection Voltage
Output Low Voltage
INERD = 1.0 mA, VOUT = 4.5 V
−
−
0.5
V
Pull−Up Current
NERD = 0.5 V
30
40
50
μA
6.25
8.5
11
ms
Power On Delay
−
Clamping Voltage (Low)
VER Present
1.0
1.25
1.5
V
Clamping Voltage (High)
VER Not Present
3.5
3.75
4.0
V
−
−
−
−
−
−
5.0
5.0
4.0
mA
mA
mA
160
−
210
°C
General
VER Load Current
Thermal Shutdown
VER = 25 V, VBAT = 16 V, IV(OUT) = −100 mA
T = −40°C
T = 25°C
T = 125°C
(Guaranteed by Design)
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SO−20L
PIN SYMBOL
1
VER
Energy reserve input.
2
VBAT
Battery input.
3
VFB
Charge PUMP control voltage input.
4
GND1
Ground.
5
GND2
Ground.
6
GND3
Ground.
7
GND4
Ground.
8
VSW
Charge PUMP switch collector.
9
SWSD
Charge PUMP shutdown input.
10
COMP
Charge PUMP compensation pin.
11
CPUMP
Charge PUMP timing cap input.
12
IBIAS
Reference current resistor pin.
FUNCTION
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4
CS2001
PACKAGE PIN DESCRIPTION (continued)
PACKAGE PIN #
SO−20L
PIN SYMBOL
13
VCHG
Switched cap voltage tripler output.
14
GND5
Ground.
15
GND6
Ground.
16
GND7
Ground.
17
GND8
Ground.
18
NERD
No energy reserve detected output.
19
RESETB
20
VOUT
VER
FUNCTION
Reset output.
Linear regulator output.
VREF V /C
FB PUMP
Short
0.25 V −
Detect
+
VFB
VCC Switcher
Error Amp
VCC
−
+
COMP
+
−
Preregulator
Base
Logic
Drive
Current VCC
Sense Amp
+
−
VCC
VREF
Bandgap 1.25 V
Reference
VBAT
VREF
Over
Temperature
NERD
VSW
1.2 A
GND
Switcher
VCC Shutdown
Comp
− 0.5 × V
CC
+
Oscillator
CPUMP
VCHG
Switcher
V
Comp REF
VREF
IBIAS
Voltage
Tripler
VREF Low
Battery
−
Detect
7.25 V +
Linear
Error Amp
VREF
Logic
VREF
+
−
SWSD
No Battery
Drive
100 mA
Current
Limit
VCC
VCC
RESETB
Reset
Figure 2. Block Diagram
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5
VOUT
VER
Detect
CS2001
CIRCUIT DESCRIPTION
Figure 3 is an oscilloscope waveform showing the
charge pump collector voltage, collector current and the
charge pump timing capacitor during normal operation
with IVER = 30mA.
Figure 4 is an oscilloscope waveform showing the voltage
tripler output and the energy reserve input during power up.
Figure 4. Startup with RV(CHG) = 510 k
Figure 3. Typical Operation with IVER = 30 mA
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6
CS2001
PACKAGE DIMENSIONS
SOIC−20 WB
DWF SUFFIX
CASE 751D−05
ISSUE G
A
20
q
X 45 _
E
h
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
C
T
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
PACKAGE THERMAL DATA
Parameter
SO−20L
Unit
RΘJC
Typical
9
°C/W
RΘJA
Typical
55
°C/W
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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CS2001/D
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