NCP3102C Wide Input Voltage Synchronous Buck Converter The NCP3102C is a high efficiency, 10 A DC--DC buck converter designed to operate from a 5 V to 12 V supply. The device is capable of producing an output voltage as low as 0.8 V. The NCP3102C can continuously output 10 A through MOSFET switches driven by an internally set 275 kHz oscillator. The 40--pin device provides an optimal level of integration to reduce size and cost of the power supply. The NCP3102C also incorporates an externally compensated transconductance error amplifier and a capacitor programmable soft--start function. Protection features include programmable short circuit protection and input under voltage lockout (UVLO). The NCP3102C is available in a 40--pin QFN package. http://onsemi.com MARKING DIAGRAM QFN40, 6x6 CASE 485AK 1 40 A WL YY WW G Features NCP3102C AWLYYWWG Split Power Rail 2.7 V to 18 V on PWRVCC 275 kHz Internal Oscillator Greater Than 90% Max Efficiency Boost Pin Operates to 35 V Voltage Mode PWM Control 0.8 V ±1% Internal Reference Voltage Adjustable Output Voltage Capacitor Programmable Soft--Start 85% Max Duty Cycle Input Undervoltage Lockout Resistor Programmable Current Limit These are Pb--Free Devices = Assembly Location = Wafer Lot = Year = Work Week = Pb--Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 24 of this data sheet. Applications Servers / Networking DSP and FPGA Power Supply DC--DC Regulator Modules D1 100 CBST CIN CVCC BG COMP/DIS RSET CP FC AGND (EP) 95 LO 90 CO R1 PWRGND (EP) FB AGND R2 CC EFFICIENCY (%) CPHS BST PWRVCC PWRPHS PWRVCC PWRPHS EP (EP) VCC PWRGND 75 70 65 60 55 0 1 2 3 4 5 6 IOUT (A) 7 8 9 10 Figure 2. Efficiency Figure 1. Typical Application Diagram February, 2011 -- Rev. 0 VIN = 12 V 80 50 Semiconductor Components Industries, LLC, 2011 VIN = 5.0 V 85 1 Publication Order Number: NCP3102C/D NCP3102C VCC 13 FB BST 24 TGOUT 21 TGIN 25 PWRVCC 26--34 POR UVLO -+ 16 Vref FAULT -+ R 0.8 V Q PWM OUT + -- S CLOCK PWRPHS 1--4 36--40 2V CPHS COMP DIS 22 RAMP VCC 17 OSC -+ FAULT FAULT OSC LATCH 400 mV 50 mV --550 mV VOCTH CPHS -+ 2V VOCTH SET 10 mA -+ 14,15,19,20,23 AGND Figure 3. Detailed Block Diagram http://onsemi.com 2 35 BG 5--12 PWRGND 40 39 38 37 36 35 34 33 32 31 PWRPHS PWRPHS PWRPHS PWRPHS PWRPHS BG PWRVCC PWRVCC PWRVCC PWRVCC NCP3102C PWRGND PWRPHS PWRVCC AGND 30 29 28 27 26 25 24 23 22 21 PWRVCC PWRVCC PWRVCC PWRVCC PWRVCC TGIN BST AGND CPHS TGOUT PWRGND PWRGND VCC AGND AGND FB COMP NC AGND AGND 11 12 13 14 15 16 17 18 19 20 PWRPHS 1 PWRPHS 2 PWRPHS 3 PWRPHS 4 PWRGND 5 PWRGND 6 PWRGND 7 PWRGND 8 PWRGND 9 PWRGND 10 Figure 4. Pin Connections Table 1. PIN FUNCTION DESCRIPTION Pin No Symbol Description 1--4, 36--40 PWRPHS Power phase node (PWRPHS). Drain of the low side power MOSFET. 5--12 PWRGND Power ground. High current return for the low--side power MOSFET. Connect PWRGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. 13 VCC 14,15,19,20,23 AGND 16 FB The inverting input pin to the error amplifier. Use this pin in conjunction with the COMP pin to compensate the voltage--control feedback loop. Connect this pin to the output resistor divider (if used) or directly to output voltage. 17 COMP/DIS Compensation or disable pin. The output of the error amplifier (EA) and the non--inverting input of the PWM comparator. Use this pin in conjunction with the FB pin to compensate the voltage--control feedback loop. The compensation capacitor also acts as a soft start capacitor. Pull the pin below 400 mV to disable controller. 18 NC 21 TGOUT 22 CPHS 24 BST Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin and the CPHS pin. 25 TGIN High side MOSFET gate. 26--34 PWRVCC 35 BG Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF capacitor to GND. Ensure that this decoupling capacitor is placed near the IC. IC ground reference. All control circuits are referenced to these pins. Not Connected. The pin can be connected to AGND or not connected. High side MOSFET driver output. The controller phase sensing for short circuit protection. Input supply pin for the high side MOSFET. Connect VCCPWR to the VCC pin or power separately for split rail application.. The current limit set pin and low side MOSFET gate drive. http://onsemi.com 3 NCP3102C Table 2. ABSOLUTE MAXIMUM RATINGS Symbol Min Max Unit Main Supply Voltage Control Input Pin Name VCC --0.3 15 V Main Supply Voltage Power Input PWRVCC --0.3 30 V VBST --0.3 35 V VBST_spike --5.0 40 V Bootstrap Pin Voltage vs VPWRPHS VBST --VPWRPHS --0.3 15 V High Side Switch Max DC Current I PHS 0 7.5 A VPWRPHS --0.7 30 V VPWRPHSSP --5 40 V VCPHS --0.7 30 V VCPHSTR --5 40 V VBG --0.3 VCC < VBG < 15 V VBGSP --2.0 VCC < VBGSP < 15 V VTG --0.3 30 V Bootstrap Supply Voltage vs Ground Bootstrap Supply Voltage vs Ground (spikes < = 50 ns) VPWRPHS Pin Voltage VPWRPHS Pin Voltage (spikes < 50 ns) CPHASE Pin Voltage CPHASE Pin Voltage (spikes < 50 ns) Current Limit Set and Bottom Gate Current Limit Set and Bottom Gate (spikes < 200 ns) Top Gate vs Ground Top Gate vs Phase Top Gate vs Phase (spikes < 200 ns) FB Pin Voltage COMP/DISABLE Rating VTG --0.3 VCC < VTG < 15 V VTGSP --2.0 VCC < VTGSP < 15 V VFB --0.3 VCC < VFB < 6.0 V VCOMP/DIS --0.3 VCC < VCOMP/DIS < 6.0 V Symbol Symbol Unit Thermal Resistance, Junction--to--Ambient (Note 2) RθJA 35 C/W Thermal Resistance, Junction--to--Case (Note 2) at 85C RθJC 5 C/W Continuous Power Distribution (TA = +85C) PD 1.8 W Storage Temperature Range Tstg --55 to 150 C Junction Operating Temperature TJ --40 to 150 C Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb--Free (Note 1) RF 260 peak C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: These devices have limited built--in ESD protection. The devices should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the device. 1. 60--180 seconds minimum above 237C 2. Based on 110 * 100 mm double layer PCB with 35 mm thick copper plating. http://onsemi.com 4 NCP3102C Table 3. ELECTRICAL CHARACTERISTICS (--40C < TJ < 125C; VCC =12 V, BST -- PHS = 12 V, BST = 12 V, PHS = 24 V, for min/max values unless otherwise noted). Characteristic Power Power Channel Conditions Min Typ Max Unit PWRVCC -- GND 2.7 18 V Input Voltage Range VCC -- GND 4.5 13.2 V Boost Voltage Range VBST -- GND 4.5 26.5 V SUPPLY CURRENT Quiescent Supply Current VFB = 0.85 V VCOMP = 0.4 V, No Switching, VCC = 13.2 V 4.1 mA Quiescent Supply Current VFB = 0.85 V VCOMP = 0.4 V No Switching, VCC = 5.0 V 3.2 mA VCC Supply Current VFB = VCOMP = 1 V, Switching, VCC = 13.2 V 9.2 16 mA VCC Supply Current VFB = VCOMP = 1 V, Switching, VCC = 5 V 8.5 12 mA Boost Quiescent Current VFB = 0.85 V, No Switching, VCC = 13.2 V 63 Shutdown Supply Current VFB = 1 V, VCOMP= 0 V, No Switching, VCC = 13.2 V -- 4.1 -- mA VCC Rising Edge 3.8 -- 4.3 V -- -- 364 -- mV BST Rising -- 3.82 -- V -- 3.71 -- V mA UNDER VOLTAGE LOCKOUT VCC UVLO Threshold VCC UVLO Hysteresis BST UVLO Threshold Rising BST UVLO Threshold Falling SWITCHING REGULATOR VFB Feedback Voltage, Control Loop in Regulation 0C < TJ < 70C, 4.5 V < VCC < 13.2 V --40C < TJ < 125C, 4.5 < VCC < 13.2 V 0.792 0.788 0.800 0.800 0.808 0.812 V Oscillator Frequency 0C < TJ < 70C, 4.5 V < VCC < 13.2 V --40C < TJ < 125C, 4.5 < VCC < 13.2 V 250 233 275 275 300 317 kHz 0.8 1.1 1.4 V -- 8.5 -- % Ramp--Amplitude Voltage Minimum Duty Cycle Maximum Duty Cycle 85 % TG Falling to BG Rising Delay VCC = 12 V, TG < 2.0 V, BG > 2.0 V 46 ns BG Falling to TG Rising Delay VCC = 12 V, BG < 2.0 V, TG > 2.0 V 41 ns PWM COMPENSATION Transconductance Open Loop DC Gain Output Source Current Output Sink Current 3.2 -- 3.6 mS Guaranteed by design 55 70 -- DB VFB < 0.8 V VFB > 0.8 V 80 80 140 131 193 193 mA -- 0.160 1.0 mA 0.37 0.4 .43 V ms Input Bias Current ENABLE Enable Threshold (Falling) SOFT--START Delay to Soft--Start 1 -- 5 SS Source Current VFB < 0.8 V -- 10.6 -- mA Switch Over Threshold VFB = 0.8 V -- 100 -- % of Vref Sourced from BG Pin before Soft--Start -- 10 -- mA RBG = 5 kΩ -- 50 -- mV OC Switch--Over Threshold -- 700 -- mV Fixed OC Threshold -- 99 -- mV OVER--CURRENT PROTECTION OCSET Current Source OC Threshold PWM OUTPUT STAGE High--Side Switch On--Resistance VCC = 12 V ID = 1 A -- 8 -- mΩ Low--Side Switch On--Resistance VCC = 12 V ID = 1 A -- 8 -- mΩ http://onsemi.com 5 NCP3102C TYPICAL OPERATING CHARACTERISTICS ICC, SUPPLY CURRENT SWITCHING (mA) 285 FSW, FREQUENCY (kHz) 284 283 282 281 280 12 V 279 278 5V 277 276 275 --40 --20 0 20 40 60 80 100 120 12 V 30 25 20 15 5V 10 5 0 --40 --20 0 20 40 60 80 100 120 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 5. Frequency (FSW) vs. Temperature Figure 6. Switching Current vs. Temperature 0.807 4.1 UVLO Rising 12 V 0.803 5V 0.801 0.799 0.797 --40 --20 0 20 40 60 80 100 4 UVLO RISING/FALLING (V) 0.805 3.9 3.8 UVLO Falling 3.7 3.6 3.5 --40 120 --20 0 20 40 60 80 100 120 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 7. Reference Voltage (Vref) vs. Temperature Figure 8. UVLO Threshold vs. Temperature 16 SOFT--START CURRENT (mA) Vref, REFERENCE VOLTAGE (mV) 35 14 12 VCC = 12 V 10 8 VCC = 5 V 6 4 2 0 --40 --20 0 20 40 60 80 100 120 TJ, JUNCTION TEMPERATURE (C) Figure 9. Soft--Start Sourcing vs. Temperature http://onsemi.com 6 NCP3102C TYPICAL OPERATING CHARACTERISTICS 10 9 Vin = 12 V LOW--SIDE RDS(on) (mΩ) ICC, SUPPLY CURRENT SWITCHING (mA) 10 8 7 6 Vin = 5 V 5 4 3 2 9 8.5 8 7.5 1 0 --40 --20 0 20 40 60 80 100 7 120 25 0 50 75 100 TJ, JUNCTION TEMPERATURE (C) Figure 10. ICC vs. Temperature Figure 11. I--Limit vs. Temperature 125 ICC, CONTROL CIRCUITRY CURRENT DRAW (mA) 13 3.55 3.50 VCC = 5 V 3.45 3.40 3.35 VCC = 12 V 3.30 3.25 3.20 --40 --20 0 20 40 60 80 100 12 11 10 ICC High Duty Ratio 8 7 6 5 4 120 ICC Low Duty Ratio 9 5 6 7 8 9 10 11 12 13 VIN, INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (C) Figure 13. Maximum Duty Cycle vs. Input Voltage Figure 12. Transconductance vs. Temperature 799.0 87 5V 86 12 V 85 84 83 --40 --20 0 20 40 60 80 100 VOLTAGE REFERENCE (mV) 88 DUTY CYCLE (%) --25 TJ, JUNCTION TEMPERATURE (C) 3.60 TRANSCONDUCTANCE (mS) 9.5 798.8 798.6 798.4 798.2 798.0 4 120 5 6 7 8 9 10 11 12 13 JUNCTION TEMPERATURE (C) VIN, INPUT VOLTAGE (V) Figure 14. Controller Current vs. Input Voltage Figure 15. Reference Voltage vs. Input Voltage http://onsemi.com 7 NCP3102C TYPICAL OPERATING CHARACTERISTICS 6 12 V DUTY CYCLE (%) 5 5V 4 3 2 1 0 --40 --20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) Figure 16. Minimum Duty Cycle vs. Temperature http://onsemi.com 8 120 NCP3102C DETAILED OPERATING DESCRIPTION General Although BST is rated at 13.2 V with reference to PHS, it can also tolerate 26.5 V with respect to GND. NCP3102C is a high efficiency integrated wide input voltage 10 A synchronous PWM buck converter designed to operate from a 4.5 V to 13.2 V supply. The output voltage of the converter can be precisely regulated down to 800 mV +1.0% when the VFB pin is tied to the output voltage. The switching frequency is internally set to 275 kHz. A high gain Operational Transconductance Error Amplifier (OTEA) is used for feedback and stabilizing the loop. External Enable/Disable Once the input voltage has exceeded the boost and UVLO threshold at 3.82 V and VCC threshold at 4 V, the COMP pin starts to rise. The PWRPHS node is tri--stated until the COMP voltage exceeds 830 mV. Once the 830 mV threshold is exceeded, the part starts to switch and is considered enabled. When the COMP pin voltage is pulled below the 400 mV threshold, it disables the PWM logic, the top MOSFET is driven off, and the bottom MOSFET is driven on as shown in Figure 18. In the disabled mode, the OTA output source current is reduced to 10 mA. When disabling the NCP3102C using the COMP / Disable pin, an open collector or open drain drive should be used as shown in Figure 19. Input Voltage The NCP3102C can be used in many applications by using the VCC and PWRVCC pins together or separately. The PWRVCC pin provides voltage to the switching MOSFETS. The VCC pin provides voltage to the control circuitry and driver stage. If the VCC and the PWRVCC pin are not tied together, the input voltage of the PWRVCC pin can accept 2.7 V to 18 V. If the VCC and PWRVCC pins are tied together the input voltage range is 4.5 V to 13.2 V. Duty Cycle and Maximum Pulse Width Limits 0.83 V In steady state DC operation, the duty cycle will stabilize at an operating point defined by the ratio of the input to the output voltage. The NCP3102C can achieve an 82% duty ratio. The part has a built in off--time which ensures that the bootstrap supply is charged every cycle. The NCP3102C is capable of a 100 ns pulse width (minimum) and allows a 12 V to 0.8 V conversion at 275 kHz. The duty cycle limit and the corresponding output voltage are shown below in graphical format in Figure 17. The green area represents the safe operating area for the lowest maximum operational duty cycle for 4.5 V and 13.2 V. COMP BG TG Figure 18. Enable/Disable Driver State Diagram 2N7002E Gate Signal Enable Disable Base Signal Enable INPUT VOLTAGE (V) 12. 5 MMBT3904 COMP Disable COMP 11. 5 Figure 19. Recommended Disable Circuits 10. 5 9. 5 Power Sequencing 8. 5 Power sequencing can be achieved with NCP3102C using two general purpose bipolar junction transistors or MOSFETs. An example of the power sequencing circuit using the external components is shown in Figure 20. Dmax = 0.82 7. 5 Dmax = 0.88 6. 5 5. 5 4. 5 3. 5 4. 5 5. 5 6. 5 7. 5 8. 5 9. 5 VSW 10. 5 11. 5 OUTPUT VOLTAGE (V) NCP3102C FB1 Figure 17. Maximum Input to Output Voltage COMP 1.0V VIN VSW NCP3102C FB1 COMP Input voltage range (VCC and BST) The input voltage range for both VCC and BST is 4.5 V to 13.2 V with reference to GND and PHS, respectively. Figure 20. Power Sequencing http://onsemi.com 9 3.3V NCP3102C Normal Shutdown Behavior 4.3 V Normal shutdown occurs when the IC stops switching because the input supply reaches UVLO threshold. In this case, switching stops, the internal soft start, SS, is discharged, and all gate pins are driven low. The switch node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage. VCC 0.9 V COMP VFB External Soft--Start BG The NCP3102C features an external soft start function, which reduces inrush current and overshoot of the output voltage. Soft start is achieved by using the internal current source of 10 mA (typ), which charges the external integrator capacitor of the transconductance amplifier. Figures 21 and 22 are typical soft start sequences. The sequence begins once VCC surpasses its UVLO threshold. During Soft Start as the Comp Pin rises through 400 mV, the PWM logic and gate drives are enabled. When the feedback voltage crosses 800 mV, the EOTA will be given control to switch to its higher regulation mode with the ability to source and sink 130 mA. In the event of an over current during the soft start, the overcurrent logic will override the soft start sequence and will shut down the PWM logic and both the high side and low side gates of the switching MOSFETS. TG 500mV BG Comparator DAC Voltage 50mV BG Comparator Output Vout UVLO Current Normal Operation POR Trip Set COMP Delay Delay UVLO Figure 22. Soft--Start Sequence UVLO Under Voltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VCC is too low to support the internal rails and power the converter. For the NCP3102C, the UVLO is set to ensure that the IC will start up when VCC reaches 4.0 V and shutdown when VCC drops below 3.6 V. The UVLO feature permits smooth operation from a varying 5.0 V input source. 0.83V 0.4V 3.4 V 0.4V Vcomp Enable Current Limit Protection In case of a short circuit or overload, the low--side (LS) FET will conduct large currents. The low--side RDS(on) sense is implemented to protect from over current by comparing the voltage at the phase node to AGND just prior to the low side MOSFET turnoff to an internally generated fixed voltage. If the differential phase node voltage is lower than OC trip voltage, an overcurrent condition occurs and a counter is initiated. If seven consecutive over current trips are counted, the PWM logic and both HS--FET and LS--FET are latch off. The converter will be latched off until input power drops below the UVLO threshold. The operation of key nodes are displayed in Figure 23 for both normal operation and during over current conditions. 0.8V Vfb SS 120uA 10uA 10uA Isource/ sink --10uA Start up Normal Figure 21. Soft--Start Implementation http://onsemi.com 10 NCP3102C as soon as BG voltage reaches 700 mV, enabling the 96 mV fixed threshold and ending the OC setting period. The current trip threshold tolerance is ±25 mV. The accuracy is best at the highest set point (550 mV). The accuracy will decrease as the set point decreases. LS Gate Drive 2V BG Comparator 2V HS Gate Drive Drivers The NCP3102C drives the internal high and low side switching MOSFETS with 1 A gate drivers. The gate drivers also include adaptive non--overlap circuitry. The non--overlap circuitry increases efficiency which minimizes power dissipation by minimizing the low--side MOSFET body diode conduction time. A block diagram of the non--overlap and gate drive circuitry used is shown in Figure 25. Switch Node Comparator 2V Switch Node SCP Trip Voltage C Phase SCP Comparator/ BST Latch Output UVLO FAULT Figure 23. Switching and Current Limit Timing TG Overcurrent Threshold Setting The NCP3102C overcurrent threshold can be set from 50 mV to 450 mV by adding a resistor (RSET) between BG and GND. During a short period of time following VCC rising above the UVLO threshold, an internal 10 mA current (IOCSET) is sourced from the BG pin, creating a voltage drop across RSET. The voltage drop is compared against a stepped internal voltage ramp. Once the internal stepped voltage reaches the RSET voltage, the value is stored internally until power is cycled. The overall time length for the OC setting procedure is approximately 3 ms. When connecting an RSET resistor between BG and GND, the programmed threshold will be: I OCth = I OCSET * R SET R DS(on) → 12.5 A = 10 mA * 10 kΩ 8 mΩ + -- 2V + -- 2V PHASE VCC BG PWM OUT GND UVLO FAULT (eq. 1) Figure 24. Block Diagram IOCSET = Sourced current IOCTH = Current trip threshold RDS(on) = On resistance of the low side MOSFET RSET = Current set resistor The RSET values range from 5 kΩ to 45 kΩ. If RSET is not connected or the RSET value is too high, the device switches the OCP threshold to a fixed 96 mV value (12 A) typical at 12 V. The internal safety clamp on BG is triggered Careful selection and layout of external components is required to realize the full benefit of the onboard drivers. The capacitors between VCC and GND and between BST and CPHS must be placed as close as possible to the IC. A ground plane should be placed on the closest layer for return currents to GND in order to reduce loop area and inductance in the gate drive circuit. http://onsemi.com 11 NCP3102C APPLICATION SECTION Design Procedure current in the inductor should be between 10% and 40%. When using ceramic output capacitors, the ripple current can be greater because the ESR of the output capacitor is small, thus a user might select a higher ripple current. However, when using electrolytic capacitors, a lower ripple current will result in lower output ripple due to the higher ESR of electrolytic capacitors. The ratio of ripple current to maximum output current is given in Equation 5. When starting the design of a buck regulator, it is important to collect as much information as possible about the behavior of the input and output before starting the design. ON Semiconductor has a Microsoft Excel based design tool available online under the design tools section of the NCP3102C product page. The tool allows you to capture your design point and optimize the performance of your regulator based on your design criteria. ra = Example Value Input voltage (VCC) 10.8 V to 13.2 V Output voltage (VOUT) 3.3 V Input ripple voltage (VCCRIPPLE) 300 mV Output ripple voltage (VOUTRIPPLE) 40 mV L OUT = Output current rating (IOUT) 10 A Operating frequency (FSW) 275 kHz D= 27.5% = D FSW T TOFF TON VHSD VCC VLSD VOUT T ON T V CC − V HSD + V LSD T OFF ≈D= V OUT V CC * (1 − D ) → (eq. 6) 3.3 V 10 A * 26% * 275 kHz * (1 − 27.5%) = Duty ratio = Switching frequency = Output current = Output inductance = Ripple current ratio 8 (eq. 3) T I OUT * ra * F SW 9 (eq. 2) (1 − D ) = V OUT + V LSD D FSW IOUT LOUT ra INDUCTANCE (mH) D= V OUT 3.35 mH = The buck converter generates input voltage VCC pulses that are LC filtered to produce a lower DC output voltage VOUT. The output voltage can be changed by modifying the on time relative to the switching period T or switching frequency. The ratio of high side switch on time to the switching period is called duty ratio D. Duty ratio can also be calculated using VOUT, VCC, Low Side Switch Voltage Drop VLSD, and High Side Switch Voltage Drop VHSD. 1 F SW = T (eq. 5) ΔI = Ripple current IOUT = Output current ra = Ripple current ratio Using the ripple current rule of thumb, the user can establish acceptable values of inductance for a design using Equation 6. Table 4. DESIGN PARAMETERS Design Parameter ΔI I OUT → (eq. 4) 3.3 V 7 6 5 13V 4 3 5V 2 12 V 3.3 mH 7V 1 = Duty cycle = Switching frequency = Switching period = High side switch off time = High side switch on time = High side switch voltage drop = Input voltage = Low side switch voltage drop = Output voltage 0 10 13 16 19 22 25 28 31 34 37 40 RIPPLE CURRENT RATIO (%) Figure 25. Inductance vs. Current Ripple Ratio When selecting an inductor, the designer must not exceed the current rating of the part. To keep within the bounds of the part’s maximum rating, a calculation of the RMS current and peak current are required. Inductor Selection When selecting an inductor, the designer may employ a rule of thumb for the design where the percentage of ripple http://onsemi.com 12 NCP3102C I RMS = I OUT * 1 + ra12 → 10.03 A = 10 A * IOUT IRMS ra IPP = Peak--to--peak current of the inductor LOUT = Output inductance VOUT = Output voltage From Equation 10 the ripple current increases as LOUT decreases, emphasizing the trade--off between dynamic response and ripple current. The power dissipation of an inductor falls into two categories: copper and core losses. Copper losses can be further categorized into DC losses and AC losses. A good first order approximation of the inductor losses can be made using the DC resistance as shown below: 2 (eq. 7) 26% 2 1+ 12 = Output current = Inductor RMS current = Ripple current ratio I PK = I OUT * 1 + 26% ra → 11.3 A = 10 A * 1 + 2 2 (eq. 8) LP CU_DC = I RMS 2 * DCR → 171 mW = 10.03 2 * 1.69 mΩ IOUT = Output current IPK = Inductor peak current ra = Ripple current ratio A standard inductor should be found so the inductor will be rounded to 3.3 mH. The inductor should support an RMS current of 10.03 A and a peak current of 11.3 A. The final selection of an output inductor has both mechanical and electrical considerations. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by Equation 9. SlewRate LOUT = V CC − V OUT L OUT → 2.64 A∕ms = (eq. 11) IRMS = Inductor RMS current DCR = Inductor DC resistance LPCU_DC = Inductor DC power dissipation The core losses and AC copper losses will depend on the geometry of the selected core, core material, and wire used. Most vendors will provide the appropriate information to make accurate calculations of the power dissipation, at which point the total inductor losses can be captured by the equation below: LP tot = LP CU_DC + LP CU_AC + LP Core → 352 mW = 171 mW + 19 mW + 162 mW LPCU_DC LPCU_AC LPCore 12 V − 3.3 V 3.3 mH The important factors to consider when selecting an output capacitor are DC voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements. The output capacitor must be rated to handle the ripple current at full load with proper derating. The RMS ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies, but a multiplier is usually given for higher frequency operation. The RMS current for the output capacitor can be calculated below: LOUT = Output inductance VCC = Input voltage VOUT = Output voltage Equation 9 implies that larger inductor values limit the regulator’s ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. Reduced inductance to increase slew rates results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator’s maximum achievable slew rate and decrease the necessary capacitance at the expense of higher ripple current. The peak--to--peak ripple current is given by the following equation: V OUT1 − D L OUT * F SW 2.64 A = D FSW = Inductor DC power dissipation = Inductor AC power dissipation = Inductor core power dissipation Output Capacitor Selection (eq. 9) I PP = (eq. 12) CO RMS = I OUT ra 12 → 0.75 A = 10 A 26% 12 (eq. 13) CoRMS = Output capacitor RMS current IOUT = Output current ra = Ripple current ratio The maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the Equivalent Series Inductance (ESL), and Equivalent Series Resistance (ESR). The main component of the ripple voltage is usually due to the ESR of the output capacitor and the capacitance selected, which can be calculated as shown in Equation 14: → (eq. 10) 3.3 V1 − 27.5% 3.3 mH * 275 kHz = Duty ratio = Switching frequency http://onsemi.com 13 NCP3102C V ESR_C = I OUT * ra CO ESR + 8*F 32.4 mV = 10 * 26% 12 mΩ + 1 SW * C OUT A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is given by the following equation: (eq. 14) 1 8 * 275 kHz * 1000 mF ΔV OUT--DIS = CoESR = Output capacitor ESR COUT = Output capacitance FSW = Switching frequency IOUT = Output current ra = Ripple current ratio The ESL of capacitors depends on the technology chosen, but tends to range from 1 nH to 20 nH, where ceramic capacitors have the lowest inductance and electrolytic capacitors have the highest. The calculated contributing voltage ripple from ESL is shown for the switch on and switch off below: V ESLON = 7.8 mV = ESL * I PP * F SW D → 4.9 mV = 2.96 mV = 1 − D → (eq. 15) (eq. 16) 3 nH * 2.64 A * 275 kHz 1 − 27.5% D = Duty ratio ESL = Capacitor inductance FSW = Switching frequency Ipp = Peak--to--peak current The output capacitor is a basic component for fast response of the power supply. For the first few microseconds of a load transient, the output capacitor supplies current to the load. Once the regulator recognizes a load transient, it adjusts the duty ratio, but the current slope is limited by the inductor value. During a load step transient, the output voltage initially drops due to the current variation inside the capacitor and the ESR (neglecting the effect of the ESL). The user must also consider the resistance added due to PCB traces and any connections to the load. The additional resistance must be added to the ESR of the output capacitor. CoESR ITRAN ΔVOUT_ESR → (eq. 18) 5 A 2 × 3.3 mH 2 * 82% * 820 mF × 12 V − 3.3 V = = = = = = = Table 5. TRANSIENT RESPONSE VERSUS OUTPUT CAPACITANCE (50% to 100% Load Step) COUT OS--CON (mF) Drop (mV) Recovery Time (ms) 100 226 504 150 182 424 220 170 264 270 149 233 560 112 180 680 100 180 820 96 180 ΔV OUT--ESR = I TRAN × CO ESR + RCON → 71 mV = 5 A × 12 mΩ + 2.2 mΩ × LOUT Output capacitance Maximum duty ratio Output transient current Output inductor value Input voltage Output voltage Voltage deviation of VOUT due to the effects of capacitor discharge In a typical converter design, the ESR of the output capacitor bank dominates the transient response. Please note that ΔVOUT_DIS and ΔVOUT_ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL). Table 5 shows values of voltage drop and recovery time of the NCP3102C demo board with the configuration shown in Figure 26. The transient response was measured for the load current step from 5 A to 10 A (50% to 100% load). Input capacitors are 2 x 47 mF ceramic and 5 x 270 mF OS--CON, output capacitors are 2 x 100 mF ceramic and OS--CON as mentioned in Table 5. Typical transient response waveforms are shown in Figure 26. More information about OS--CON capacitors is available at http://www.edc.sanyo.com. 27.5% ESL * I PP * F SW 2 2 * D MAX * C OUT × V CC − V OUT COUT DMAX ITRAN LOUT VCC VOUT ΔVOUT_DIS 3 nH * 2.64 A * 275 kHz V ESLOFF = I TRAN (eq. 17) = Output capacitor Equivalent Series Resistance = Output transient current = Voltage deviation of VOUT due to the effects of ESR http://onsemi.com 14 1000 71 180 2X680 60 284 2X820 40 284 NCP3102C losses. The switching losses of the low side MOSFET will not be calculated as it switches into nearly zero voltage and the losses are insignificant. However, the body diode in the low--side MOSFET will suffer diode losses during the non--overlap time of the gate drivers. Starting with the high--side MOSFET, the power dissipation can be approximated from: P D_HS = P COND + P SW_TOT (eq. 21) PCOND = Conduction losses PD_HS = Power losses in the high side MOSFET PSW_TOT = Total switching losses The first term in Equation 21 is the conduction loss of the high--side MOSFET while it is on. P COND = I RMS_HS Input Capacitor Selection The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, therefore must have a low ESR to minimize losses. The RMS value of the input ripple current is: I RMS_HS = I OUT ⋅ (eq. 19) D = Duty ratio IINRMS = Input capacitance RMS current IOUT = Load current The equation reaches its maximum value with D = 0.5. Loss in the input capacitors can be calculated with the following equation: 199.8 mW = 10 mΩ × 4.47 A D⋅ 1+ ra 2 12 P SW_TOT = P SW + P DS + P RR (eq. 23) (eq. 24) PDS = High side MOSFET drain to source losses PRR = High side MOSFET reverse recovery losses PSW = High side MOSFET switching losses PSW_TOT = High side MOSFET total switching losses The first term for total switching losses from Equation 24 are the losses associated with turning the high--side MOSFET on and off and the corresponding overlap in drain voltage and current. 2 2 (eq. 22) D = Duty ratio ra = Ripple current ratio IOUT = Output current IRMS_HS = High side MOSFET RMS current The second term from Equation 21 is the total switching loss and can be approximated from the following equations. IIN RMS = I OUT × D × 1 − D → P CIN = CIN ESR × IIN RMS ⋅ R DS(on)_HS IRMS_HS = RMS current in the high side MOSFET RDS(ON)_HS = On resistance of the high side MOSFET PCOND = Conduction power losses Using the ra term from Equation 5, IRMS becomes: Figure 26. Typical Waveform of Transient Response 4.47 A = 10 A 27.5% × 1 − 27.5% 2 (eq. 20) CINESR = Input capacitance Equivalent Series Resistance IINRMS = Input capacitance RMS current PCIN = Power loss in the input capacitor Due to large di/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum capacitor must be used, it must be surge protected, otherwise capacitor failure could occur. P SW = P TON + P TOFF = Power MOSFET Dissipation Power dissipation, package size, and the thermal environment drive power supply design. Once the dissipation is known, the thermal impedance can be calculated to prevent the specified maximum junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The high--side MOSFET will display both switching and conduction FSW IOUT PSW PTON PTOFF tFALL tRISE VCC http://onsemi.com 15 1 ⋅ I OUT ⋅ V IN ⋅ F SW ⋅ t RISE + t FALL 2 (eq. 25) = Switching frequency = Load current = High side MOSFET switching losses = Turn on power losses = Turn off power losses = MOSFET fall time = MOSFET rise time = Input voltage NCP3102C When calculating the rise time and fall time of the high side MOSFET it is important to know the charge characteristic shown in Figure 27. FSW = Switching frequency PRR = High side MOSFET reverse recovery losses QRR = Reverse recovery charge VCC = Input voltage The low--side MOSFET turns on into small negative voltages so switching losses are negligible. The low--side MOSFET’s power dissipation only consists of conduction loss due to RDS(on) and body diode loss during non--overlap periods. P D_LS = P COND + P BODY PBODY = Low side MOSFET body diode losses PCOND = Low side MOSFET conduction losses PD_LS = Low side MOSFET losses Conduction loss in the low--side MOSFET is described as follows: Vth Q GD I G1 IG1 Q GD VBST − VTH∕RHSPU + RG Q GD I G2 = Q GD VBST − VTH∕RHSPD + RG (eq. 26) (eq. 32) P BODY = V FD ⋅ I OUT ⋅ F SW ⋅ NOL LH + NOL HL (eq. 33) FSW IOUT NOLHL (eq. 27) NOLLH PBODY VFD 1 − D ⋅ 1 + ra 2 12 = Switching frequency = Load current = Dead time between the high--side MOSFET turning off and the low--side MOSFET turning on, typically 46 ns = Dead time between the low--side MOSFET turning off and the high--side MOSFET turning on, typically 42 ns = Low--side MOSFET body diode losses = Body diode forward voltage drop Control Dissipation The control portion of the IC power dissipation is determined by the formula below: P C = I CC * V CC (eq. 28) (eq. 34) ICC = Control circuitry current draw PC = Control power dissipation VCC = Input voltage Once the IC power dissipations are determined, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient temperature. The formula for calculating the junction temperature with the package in free air is: COSS = MOSFET output capacitance at 0 V = Switching frequency FSW PDS = MOSFET drain to source charge losses VCC = Input voltage Finally, the loss due to the reverse recovery time of the body diode in the low--side MOSFET is shown as follows: P RR = Q RR ⋅ V IN ⋅ F SW D = Duty ratio IOUT = Load current IRMS_LS = RMS current in the low side ra = Ripple current ratio The body diode losses can be approximated as: = Output current from the low--side gate drive QGD = MOSFET gate to drain gate charge RG = MOSFET gate resistance RHSPD = Drive pull down resistance tFALL = MOSFET fall time VBST = Boost voltage VTH = MOSFET gate threshold voltage Next, the MOSFET output capacitance losses are caused by both the high--side and low--side MOSFETs, but are dissipated only in the high--side MOSFET. 1 ⋅ C OSS ⋅ V IN 2 ⋅ F SW 2 (eq. 31) ⋅ R DS(on)_LS I RMS_LS = I OUT ⋅ IG2 P DS = 2 IRMS_LS = RMS current in the low side RDS(ON)_LS = Low--side MOSFET on resistance PCOND = High side MOSFET conduction losses = Output current from the high--side gate drive = MOSFET gate to drain gate charge = Drive pull up resistance = MOSFET gate resistance = MOSFET rise time = Boost voltage = MOSFET gate threshold voltage QGD RHSPU RG tRISE VBST VTH t FALL = = P COND = I RMS_LS Figure 27. High Side MOSFET Gate--to--Source and Drain--to--Source Voltage vs. Total Charge t RISE = (eq. 30) (eq. 29) http://onsemi.com 16 NCP3102C T J = T A + P D ⋅ R θJC FSW = Switching frequency FESR = Output capacitor ESR zero frequency If the criteria is not met, the compensation network may not provide stability, and the output power stage must be modified. Figure 28 shows a pseudo Type III transconductance error amplifier. (eq. 35) PD RθJC = Power dissipation of the IC = Thermal resistance junction--to--case of the regulator package TA = Ambient temperature TJ = Junction temperature As with any power design, proper laboratory testing should be performed to ensure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e., worst case MOSFET RDS(on)). ZIN CF IEA Compensation Network 2.77 kHz = 1 2π * L OUT * C OUT CC The compensation network consists of the internal error amplifier and the impedance networks ZIN (R1, R2, RF, and CF) and external ZFB (RC, CC, and CP). The compensation network has to provide a closed loop transfer function with the highest 0 dB crossing frequency to have fast response and the highest gain in DC conditions to minimize the load regulation issues. A stable control loop has a gain crossing with --20 dB/decade slope and a phase margin greater than 45. Include worst--case component variations when determining phase margin. To start the design, a resistor value should be chosen for R2 from which all other components can be chosen. A good starting value is 10 kΩ. The NCP3102C allows the output of the DC--DC regulator to be adjusted down to 0.8 V via an external resistor divider network. The regulator will maintain 0.8 V at the feedback pin. Thus, if a resistor divider circuit was placed across the feedback pin to VOUT, the regulator will regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 V at the FB pin. (eq. 36) = Output capacitor = Double pole inductor and capacitor frequency LOUT = Output inductor value The ESR of the output capacitor creates a “zero” at the frequency a shown in Equation 37: 16.2 kHz = 1 2π * 12 mΩ * 820 mF (eq. 37) → COESR = Output capacitor ESR COUT = Output capacitor FLC = Output capacitor ESR frequency The two equations above define the bode plot that the power stage has created or open loop response of the system. The next step is to close the loop by considering the feedback values. The closed loop crossover frequency should be greater then the FLC and less than 1/5 of the switching frequency, which would place the maximum crossover frequency at 55 kHz. Further, the calculated FESR frequency should meet the following: F ESR =< F SW 5 R2 Figure 28. Pseudo Type III Transconductance Error Amplifier 2π * 3.3 mH * 1000 mF 1 → 2π * CO ESR * C OUT Gm VREF → 1 CP RC COUT FLC F ESR = RF ZFB To create a stable power supply, the compensation network around the transconductance amplifier must be used in conjunction with the PWM generator and the power stage. Since the power stage design criteria is set by the application, the compensation network must correct the overall output to ensure stability. The output inductor and capacitor of the power stage form a double pole at the frequency shown in Equation 36: F LC = R1 (eq. 38) Figure 29. Feedback Resistor Divider http://onsemi.com 17 NCP3102C The relationship between the resistor divider network above and the output voltage is shown in Equation 39: R2 = R1 ⋅ V REF The compensation components for the Pseudo Type III Transconductance Error Amplifier can be calculated using the method described below. The method serves to provide a good starting place for compensation of a power supply. The values can be adjusted in real time using the compensation tool comp calc, available for download at ON Semiconductor’s website. The poles of the compensation network are calculated as follows if RF is reduced to zero. The first pole is set at the ESR zero. (eq. 39) V OUT − V REF R1 = Top resistor divider R2 = Bottom resistor divider VOUT = Output voltage VREF = Regulator reference voltage The most frequently used output voltages and their associated standard R1 and R2 values are listed in Table 6. F P1 = Table 6. OUTPUT VOLTAGE SETTINGS 1 2π ⋅ R C ⋅ C P (eq. 40) The second pole is set at zero crossover frequency. VO (V) R1 (kΩ) R2 (kΩ) 0.8 1.0 Open 1.0 2.55 10 1.1 3.83 10.2 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.6 10 5.0 52.3 10 F P2 = 1 2π ⋅ R ⋅R 1 2 R +R 1 2 ⋅ CF (eq. 41) The first zero should be set at the LC pole frequency. F z1 = 1 2π ⋅ R C ⋅ C C (eq. 42) The second zero is determined automatically by FP2. F z2 = http://onsemi.com 18 1 2π ⋅ R 1 ⋅ C F (eq. 43) NCP3102C In practical design, the feed through resistor should be at 2X the value of R2 to minimize error from high frequency feed through noise. Using the 2X assumption, RF will be set to 20 kΩ and the feed through capacitor can be calculated as shown below: CF = R1 + R2 2π * R 1 * R F + R 2 * R F + R 2 * R 1 * f cross → 214 pF = (eq. 44) 31.6 kΩ + 10 kΩ 2 * π * 31.6 kΩ * 20 kΩ + 10 kΩ * 20 kΩ + 10 kΩ * 31.6 kΩ * 27 kHz CF = Feed through capacitor fcross = Crossover frequency R1 = Top resistor divider R2 = Bottom resistor divider RF = Feed through resistor The crossover of the overall feedback occurs at FPO: F PO = R1 + RF 16.12 kHz = CF fcross FLC FPO R1 R2 RF VCC Vramp * V ramp 2π * C 2R + R * R + R * R * R + R F LC * V IN 1 2 1 1 F F F F 2 31.6 kΩ + 20 kΩ (eq. 45) * 1.1 V 2π * 214 pF 31.6 kΩ + 20 kΩ * 10 kΩ + 31.6 kΩ * 20 kΩ20 kΩ + 31.6 kΩ 2.77 kHz * 12 V 2 2 = Feed through capacitor = Crossover frequency = Frequency of the output inductor and capacitor = Pole frequency = Top of resistor divider = Bottom of resistor divider = Feed through resistor = Input voltage = Peak--to--peak voltage of the ramp http://onsemi.com 19 NCP3102C The cross over combined compensation network can be used to calculate the transconductance output compensation network as follows: CC = R2 1 * * gm → F PO R 2 * R 1 60.1 nF = CC FPO gm R1 R2 1 t SS = 10 kΩ 16.12 kHz 10 kΩ + 31.6 kΩ CP CC D ISS tSS Vramp * 3.4 mS = Compensation capacitor = Pole frequency = Transconductance of amplifier = Top of resistor divider = Bottom of resistor divider RC = 2 2 + f cross * CO ESR * C OUT 10 mA = Compensation pole capacitor = Compensation capacitor = Duty ratio = Soft--start current = Soft--start interval = Peak--to--peak voltage of the ramp → 900 mV 1 2 * 2.77 kHz * 60.1 nF * 2 2 + 27 kHz * 12 mΩ * 1000 mF Vcomp = Compensation capacitance = Output capacitor ESR = Output capacitance = Crossover frequency = Output inductor and capacitor frequency = Compensation resistor C P = C OUT * CO ESR RC * 2 * π 656 pF = 1000 mF * COESR COUT CP RC (eq. 50) 0.656 nF + 60.1 nF * 27.5% * 1.1 V (eq. 47) 2.91 kΩ = CC COESR COUT fcross FLC RC → V 1 2 * F LC * C C * I SS 1.837 ms = (eq. 46) * CP + CC * D * Vramp Vout Figure 30. Soft Start Ramp The delay from the charging of the compensation network to the bottom of the ramp is considered tssdelay. The total delay time is the addition of the current set delay and tssdelay, which in this case is 3.2 ms and 5.04 ms respectively, for a total of 8.24 ms. → 12 mΩ (eq. 48) 2.91 kΩ * 2 * π Calculating Input Inrush Current = Output capacitor ESR = Output capacitor = Compensation pole capacitor = Compensation resistor The input inrush current has two distinct stages: input charging and output charging. The input charging of a buck stage is usually not controlled, and is limited only by the input RC network and the output impedance of the upstream power stage. If the upstream power stage is a perfect voltage source, then the input charge inrush current can be depicted as shown in Figure 31 and calculated as: Calculating Soft--Start Time To calculate the soft start delay and soft start time, the following equations can be used. CP + CC * 83 V 5.04 ms = I SS 0.656 nF + 60.1 nF * 0.83 V IPK CURRENT t SSdelay = (eq. 49) 10 mA CP = Compensation pole capacitor CC = Compensation capacitor ISS = Soft start current The time the output voltage takes to increase from 0 V to a regulated output voltage is tss as shown in Equation 50: TIME Figure 31. Input Charge Inrush Current http://onsemi.com 20 NCP3102C I ICinrush_PK = 120 A = I ICin_RMS = V IN CINESR * V IN I CLR_RMS = CIN ESR (eq. 51) 12 0.1 191 mA = 0.316 * 5 * CIN ESR * C IN ROUT VOUT ICLR_RMS ICR_PK t DELAY_TOTAL (eq. 52) 16.97 A = 12 V 0.01 Ω * 0.316 * 1 1 * V OUT 3 R OUT * 3.3 V 3 10 Ω 3 10 Ω 8.24 ms Output Voltage Output Current (eq. 53) tss Figure 33. Resistive Load Current COUT = Total converter output capacitance CLOAD = Total load capacitance D = Duty ratio of the load ICL = Applied load at the output IOCinrush_RMS = RMS inrush current during start--up tSS = Soft start interval VOUT = Output voltage From the above equation, it is clear that the inrush current is dependant on the type of load that is connected to the output. Two types of load are considered in Figure 32: a resistive load and a stepped current load. Alternatively, if the output has an under voltage lockout, turns on at a defined voltage level, and draws a consistent current, then the RMS connected load current is: I CLKI = 835 mA = IOUT VOUT VOUT_TO Load NCP3102C (eq. 54) 3.3V + I CL * D Inrush Current 3.3 V 5 * 0.01 Ω * 330 mF t SS D R OUT = Output resistance = Output voltage = RMS resistor current = Peak resistor current COUT + CLOAD * VOUT * V OUT 330 mA = CIN = Input capacitor CINESR = Input capacitor ESR tDELAY_TOTAL = Total delay interval = Input voltage VCC Once the tDELAY_TOTAL has expired, the buck converter starts to switch and a second inrush current can be calculated: I OCinrush_RMS = I CR_PK = OR Figure 32. Load Connected to the Output Stage If the load is resistive in nature, the output current will increase with soft start linearly which can be quantified in Equation 54. http://onsemi.com 21 V OUT − V OUT_TO V OUT 3.3 V − 1.0 V 3.3 V * I OUT (eq. 55) *1A = Output current = Output voltage = Output voltage load turn on NCP3102C Layout Considerations 3.3V 1.0V When designing a high frequency switching converter, layout is very important. Using a good layout can solve many problems associated with these types of power supplies as transients occur. External compensation components (R1, C9) are needed for converter stability. They should be placed close to the NCP3102C. The feedback trace is recommended to be kept as far from the inductor and noisy power traces as possible. The resistor divider and feedback acceleration circuit (R2, R3, R6, C13) are recommended to be placed near output feedback (Pin 16, NCP3102C). Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. The interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located together as close as possible using ground plane construction or single point grounding. The inductor and output capacitors should be located together as close as possible to the NCP3102C. Output Voltage Output Current t tss Figure 34. Voltage Enable Load Current If the inrush current is higher than the steady state input current during max load, then an input fuse should be rated accordingly using I2t methodology. http://onsemi.com 22 23 + http://onsemi.com PWRVCC AGND FB AGND PWRGND PWRGND PWRGND VCC TGOUT AGND CPHS AGND BST TGIN Figure 35. Schematic Diagram of NCP3102C Evaluation Board 120 C10 R1 732 33n C9 11 12 13 14 15 16 17 18 19 20 COMP 220n NCP3102C PWRPHS NC C11 10 9 8 PWRPHS 7 6 5 4 3 2 1 BG 2R2 47m OCPSET RSN 40 39 38 37 36 35 34 33 32 31 R6 PWRVCC IN IN 47m 270m C2 D3 21 22 23 24 25 26 27 28 29 30 OR R7 10R L1 CSN C12 3R3 2n2 220n RBOOST BAT54T1 CBOOST D1 470 3.3 mH PHASE R3 510 1.6k R2 1 3 2 22n C13 R8 200 R8 20R C8 + C16 100m 100m 0.82m C5 Q3 Q2 CLO3 RLO9 CLO2 RLO8 CLO1 RLO7 3 2 1 3 2 1 3 2 1 + 3 2 1 X1 OUT OUT RLO10 R5 C4 + C15 D2 2xMBRS140T3 RLO1 RLO2 RLO4 RLO6 Q1 NCP3102C NCP3102C ORDERING INFORMATION Device NCP3102CMNTXG Temperature Grade Package Shipping† For --40C to +125C QFN40 (Pb--Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 24 NCP3102C PACKAGE DIMENSIONS QFN40 6x6, 0.5P CASE 485AK--01 ISSUE A A B D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. PIN ONE LOCATION E 2X 0.15 C 2X TOP VIEW 0.15 C (A3) 0.10 C A 0.08 C SIDE VIEW A1 C NOTE 4 SEATING PLANE D3 40X G3 D5 G2 L 11 G2 21 10 11 21 10 E4 E3 E2 1 30 40 e G3 31 40X e/2 b 0.10 C A B 0.05 C BOTTOM VIEW 30 1 G2 40 31 K D2 AUXILIARY BOTTOM VIEW NOTE 3 D4 G3 SOLDERING FOOTPRINT* 6.30 0.72 1.86 0.72 2.62 0.92 1 0.72 1.58 1.96 6.30 2.31 0.92 0.50 PITCH 40X 0.30 40X 1.01 0.58 0.92 3.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 25 DIM A A1 A3 b D D2 D3 D4 D5 E E2 E3 E4 e G2 G3 K L MILLIMETERS MIN MAX 0.80 1.00 -----0.05 0.20 REF 0.18 0.30 6.00 BSC 2.45 2.65 3.10 3.30 1.70 1.90 0.85 1.05 6.00 BSC 1.80 2.00 1.43 1.63 2.15 2.35 0.50 BSC 2.10 2.30 2.30 2.50 0.20 -----0.30 0.50 NCP3102C Microsoft Excel is a registered trademark of Microsoft Corporation. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303--675--2175 or 800--344--3860 Toll Free USA/Canada Fax: 303--675--2176 or 800--344--3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800--282--9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81--3--5773--3850 http://onsemi.com 26 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP3102C/D