2.1 MHz Low Voltage Dual Output Buck Converter

NCV896530
2.1 MHz Low Voltage Dual
Output Buck Converter
The NCV896530 dual step−down dc−dc converter is a monolithic
integrated circuit dedicated to automotive driver information systems
from a downstream voltage rail.
Both channels are externally adjustable from 0.9 V to 3.3 V and can
source totally up to 1600 mA. Converters are running at 2.1 MHz
switching frequency above the sensitive AM band and operate 180°
out of phase to reduce large amounts of current demand on the rail.
Synchronous rectification offers improved system efficiency.
The NCV896530 provides additional features expected in
automotive power systems such as integrated soft−start, hiccup mode
current limit and thermal shutdown protection. The device can also be
synchronized to an external clock signal in the range of 2.1 MHz.
The NCV896530 is available in a space saving, 3 x 3 mm 10−pin
DFN package.
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MARKING DIAGRAM
DFN10
CASE 485C
A
L
Y
W
G
Features
•
•
•
•
•
•
•
•
•
•
Synchronous Rectification for Higher Efficiency
2.1 MHz Switching Frequency, 180° Out−of−Phase
Sources up to 1600 mA Total and 1 A Per Channel
Adjustable Output Voltage from 0.9 V to 3.3 V
2.7 V to 5.5 V Input Voltage Range
Thermal Limit and Short Circuit Protection
Auto Synchronizes with an External Clock
Wettable Flanks – DFN
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This is a Pb−Free Device
NCV89
6530
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
(Note: Microdot may be in either location)
PIN CONNECTIONS
FB1
1
10
FB2
EN1
2
9
EN2
SYNC
3
8
POR
VIN
4
7
GND
SW1
5
6
SW2
(Top View)
Typical Applications
•
•
•
•
ORDERING INFORMATION
Audio
Infotainment
Vision System
Instrumentation
ÎÎ
ÎÎ
ÏÏ
ÏÏ
ÎÎ
ÎÎ
ÏÏ
ÎÎ
4 VIN
7 GND
OFF ON
2.1MHz
2 EN1
3 SYNC
OFF ON
9 EN2
ÏÏ
ÏÏ
ÎÎ
ÎÎ
ÏÏ
ÏÏ
ÎÎ
ÏÏ
VOUT1
Shipping†
NCV896530MWTXG
DFN10
(Pb−Free)
3000 / Tape &
Reel
10 mF
FB1 1
POR
POR 8
2.2 mH
SW2 6
FB2 10
Package
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
2.2 mH
SW1 5
11
Device
VOUT2
10 mF
Figure 1. NCV896530 Typical Application
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 3
1
Publication Order Number:
NCV896530/D
NCV896530
BLOCK DIAGRAM
EA1
FB1
EA2
UVLO
1
VREF
Thermal
shutdown
EN 1
Oscillator
EA1
AVIN
VIN
4
SW 1
EA2
EN2
8
POR
7
GND
6
SW 2
VIN
Ramp generator
AVIN
PVIN Q1
0°
Q2
9
LOGIC
CONTROL
Voltage
reference
SYNC
3
FB 2
VIN
2
LOGIC
CONTROL
SYNC
10
VREF
PWM
PWM
CONTROL
CONTROL
5
ILIMIT
Q3
PVIN
180°
SYNC
ILIMIT
Figure 2. Simplified Block Diagram
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2
Q4
NCV896530
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Type
1
FB1
Analog Input
Feedback voltage from the output 1. This is the input to the error amplifier.
Description
2
EN1
Digital Input
Enable for converter 1. This pin is active HIGH (equal or lower Analog Input voltage)
and is turned off by logic LOW.
Do not let this pin float.
3
SYNC
Digital Input
Oscillator Synchronization. This pin can be synchronized to an external clock in the
range of 2.1 MHz.
If not used, the pin must to be connected to ground.
4
VIN
Analog / Power
Input
Power supply input for the PFET power stage, analog and digital blocks. The pin must
be decoupled to ground by a 10 mF ceramic capacitor.
5
SW1
Analog Output
Connection from power MOSFETs of output 1 to the Inductor.
6
SW2
Analog Output
Connection from power MOSFETs of output 2 to the Inductor.
7
GND
Analog Ground
This pin is the GROUND reference for the analog section of the IC. The pin must be
connected to the system ground.
8
POR
Digital Output
9
EN2
Digital Input
Enable for converter 2. This pin is active HIGH (equal or lower Analog Input voltage)
and is turned off by logic LOW.
Do not let this pin float.
10
FB2
Analog Input
Feedback voltage from the output 2. This is the input to the error amplifier.
11
Exposed Pad
Power Ground
Power On Reset. This is an open drain output. This output is shutting down when one
of the output voltages are less than 90% (typ) of their nominal values. A pull−up resistor around 500 kW should be connected between POR and VIN, VOUT1 or VOUT2
depending on the supplied device.
This pin is the GROUND reference for the NFET power stage of the IC. The pin must
be connected to the system ground and to both input and output capacitors.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Minimum Voltage All Pins
Vmin
−0.3
V
Maximum Voltage All Pins
Vmax
6.0
V
Maximum Voltage ENx, SYNC, FBx, , SWx, POR
Vmax
VIN+0.3
V
Thermal Resistance Junction−to−Ambient (3x3 DFN) (Note 1)
RqJA
40
°C/W
Storage Temperature Range
Tstg
−55 to 150
°C
Junction Operating Temperature
TJ
−40 to 150
°C
2.0
200
kV
V
3
per IPC
ESD Withstand Voltage
Human Body Model
Machine Model
Vesd
Moisture Sensitivity Level
MSL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Mounted on 1 sq. in. of a 4−layer PCB with 1 oz. copper thickness.
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3
NCV896530
ELECTRICAL CHARACTERISTICS (2.7 V < VIN < 5.5 V, Min and Max values are valid for the temperature range −40°C ≤ TJ ≤
+150°C unless noted otherwise, and are guaranteed by test design or statistical correlation, Typical values are referenced to TA = +25°C)
Rating
Conditions
Symbol
Min
Typ
Max
Unit
SYNC = GND, VFB = 0 V
EN1 = EN2 = 2 V, No Switching
IQ
−
2.0
3.0
mA
EN1 = EN2 = 0 V
ISTBMAX
−
4.0
10
mA
INPUT VOLTAGE
Quiescent Current
Standby Current
Under Voltage Lockout
VIN falling
VUVLO
2.2
2.4
2.6
V
VUVLOH
−
100
150
mV
Logic high
VIHSYNC
1.2
−
−
V
Logic Low
VILSYNC
VSYNC = 5 V
IILSYNC
2
External Synchronization
FSYNC
1.8
SYNC Pulse Duty Ratio
TSYNC
Under Voltage Hysteresis
SYNC
SYNC Threshold Voltage
SYNC Pin Bias Current
0.4
50
mA
2.7
MHz
50
%
EN1, EN2
V
ENx Threshold Voltage
Logic high
VIHENx
Logic Low
VILENx
ENx Pin Bias Current
VENx = 5 V
IILENx
2
50
mA
1.2
−
−
0.4
POWER ON RESET
Power On Reset Threshold
VOUT falling
Power On Reset Hysteresis
Sink Current
VPOR = 0.4 V
VPORT
87%
93%
V
VPORH
−
3%
V
ISIPOR
2
−
mA
OUTPUT PERFORMANCES
Feedback Voltage Threshold
FB1, FB2
VFB
Feedback Voltage Accuracy
TA = 25C
ΔVOUT
Soft−Start Time
Switching Frequency
0.6
−
V
±1
−
%
−40°C < TA < 125°C
ΔVOUT
−2
−
+2
Time from EN to 90% of output voltage
tSTART
400
−
1000
ms
EN1 = EN2 = 1, VIN = 5 V
FSW
1.8
2.1
2.6
MHz
D
−
−
100
%
Duty Cycle
POWER SWITCHES
High−Side MOSFET On−resistance
IRDS(on) = 600 mA, VIN = 5 V, TA = 25°C
RONHS
−
500
820
mW
Low−Side MOSFET On−resistance
IRDS(on) = 600 mA, VIN = 5 V, TA = 25°C
RONLS
−
450
820
mW
High−Side MOSFET Leakage Current
VIN = 5 V, VLX = 0 V, VENx = 0 V
ILEAKHS
−
5
mA
Low−Side MOSFET Leakage Current
VLX = 5 V, VENx = 0 V
ILEAKLS
−
5
mA
TONMIN
−
80
ns
Minimum On Time
PROTECTION
Current Limit
IPK
1.4
Thermal Shutdown Threshold
TSD
150
Thermal Shutdown Hysteresis
TSDH
5
Hiccup Time
Peak inductor current
% of Soft−Start Time
thcp,dly
170
60
2.0
A
190
°C
20
°C
%
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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4
NCV896530
TYPICAL CHARACTERISTICS CURVES
12
ISYNC, SYNC PULLDOWN CURRENT
(mA)
TJ = 25°C,
EN1 = EN2 = 1
2.35
2.3
2.25
2.2
2.5
3
3.5
4
4.5
5
5.5
10
8
6
4
2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
VIN, INPUT VOLTAGE (V)
VSYNC, SYNC VOLTAGE (V)
Figure 4. Sync Pulldown Current vs. Sync
Voltage
12
5
14
TJ = 25°C
10
8
6
4
2
0
1
2
3
4
5
TJ = 25°C
12
10
8
6
4
2
0
2.5
0
6
3
3.5
4
4.5
5
VENX, ENABLE VOLTAGE (V)
VIN, INPUT VOLTAGE (V)
Figure 5. Enable Pulldown Current vs. Enable
Voltage
Figure 6. Standby Current vs. Input Voltage
2.00
VREF, REFERENCE VOLTAGE (mV)
600.0
1.95
IPK, CURRENT LIMIT (A)
TJ = 25°C
Figure 3. Switching Frequency vs. Input
Voltage
ISTBMAX, STANDBY CURRENT (mA)
IENX, ENABLE PULLDOWN CURRENT (mA)
FSW, SWITCHING FREQUENCY (MHz)
2.4
1.90
1.85
1.80
1.75
1.70
1.65
1.60
−40
10
60
599.5
599.0
598.5
598.0
597.5
597.0
596.5
596.0
−40
110
10
60
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Current Limit vs. Temperature
Figure 8. Reference Voltage vs. Temperature
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5
5.5
NCV896530
TYPICAL CHARACTERISTICS CURVES
14
VENX = 5 V
ISYNC, SYNC PULLDOWN CURRENT
(mA)
12.0
11.0
10
10.5
10.0
9.5
9.0
8.5
8.0
−40
VSYNC = 5 V
12
−20
0
20
40
60
80
100
120
140
8
6
4
2
0
−50
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Enable Pulldown Current vs.
Temperature
Figure 10. Sync Pulldown Current vs.
Temperature
2.30
FSW, SWITCHING FREQUENCY
(MHz)
IENX, ENABLE PULLDOWN
CURRENT (mA)
11.5
2.25
2.20
2.15
2.10
2.05
2.00
−40
VIN = 5 V,
EN1 = EN2 = 1
10
60
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Switching Frequency vs.
Temperature
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6
150
NCV896530
DC/DC OPERATION DESCRIPTION
PWM Operating Mode
When an over current event is detected the NCV896530
disables the outputs and attempts to re−enable the outputs
after the hiccup time. The part remains off for the hiccup
time and then goes through the power on reset procedure. If
the excessive load has been removed then the output stage
re−enables and operates normally; however, if the excessive
load is still present the cycle begins again. Internal heat
dissipation is kept to a minimum as current will only flow
during the reset time of the protection circuitry. The hiccup
mode is continuous until the excessive load is removed.
The output voltage of the device is regulated by
modulating the on−time pulse width of the main switch Q1
at a fixed 2.1 MHz frequency (Figure 12).
The switching of the PMOS Q1 is controlled by a flip−flop
driven by the internal oscillator and a comparator that
compares the error signal from an error amplifier with the
sum of the sensed current signal and compensation ramp.
The driver switches ON and OFF the upper side transistor
(Q1) and switches the lower side transistor in either ON state
or in current source mode.
At the beginning of each cycle, the main switch Q1 is
turned ON by the rising edge of the internal oscillator clock.
The inductor current ramps up until the sum of the current
sense signal and compensation ramp becomes higher than
the error amplifier’s voltage. Once this has occurred, the
PWM comparator resets the flip−flop, Q1 is turned OFF
while the synchronous switch Q2 is turned in its current
source mode. Q2 replaces the external Schottky diode to
reduce the conduction loss and improve the efficiency. To
avoid overall power loss, a certain amount of dead time is
introduced to ensure Q1 is completely turned OFF before Q2
is being turned ON.
Low Dropout Operation
The NCV896530 offers a low input−to−output voltage
difference. The NCV896530 can operate at 100% duty cycle
on both channels.
In this mode the PMOS (Q1) remains completely ON. The
minimum input voltage to maintain regulation can be
calculated as:
ǒ
V IN(min) + V OUT(max) ) I OUT
ǒRDS(on) ) RINDUCTOR)ǓǓ
(eq. 1)
VOUT: Output Voltage
IOUT: Max Output Current
RDS(ON): P−Channel Switch RDS(on)
RINDUCTOR: Inductor Resistance (DCR)
VOUT
Power On Reset
The Power On Reset (POR) is pulled low when one of the
converter is out of 90% of the regulation. When both outputs
are in the range of regulation. If only one channel is active,
POR stays low. When the inactive regulator becomes
enabled, POR is kept low until the output reaches its voltage
range. A pull−up resistor is needed to this open drain output.
The resistor may be connected to VIN or to an output voltage
of one regulator if the device supplied can not accept VIN on
the IO. POR is low when NCV896530 is off. Leave the POR
pin unconnected when not used.
ILX
VLX
Figure 12. PWM Switching Waveforms
Frequency Synchronization
(VIN = 3.6 V, VOUT = 1.2 V, IOUT = 600 mA, Temp = 25°C)
The NCV896530 can be synchronized with an external
clock signal by using the SYNC pin (1.8 MHz − 2.4 MHz).
During synchronization, the outputs are in phase.
Soft−Start
The NCV896530 uses soft start to limit the inrush current
when the device is initially powered up or enabled. Soft start
is implemented by gradually increasing the reference
voltage until it reaches the full reference voltage. During
startup, a pulsed current source charges the internal soft start
capacitor to provide gradually increasing reference voltage.
When the voltage across the capacitor ramps up to the
nominal reference voltage, the pulsed current source will be
switched off and the reference voltage will switch to the
regular reference voltage.
Thermal Shutdown
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. If the junction
temperature exceeds TSD, the device shuts down. In this
mode all power transistors and control circuits are turned
off. The device restarts in soft start after the temperature
drops below 130°C min. This feature is provided to prevent
catastrophic failures from accidental device overheating.
Over Current Hiccup Protection
When the current through the inductor exceeds the current
limit the NCV896530 enters over current hiccup mode.
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7
NCV896530
effect on the control loop. If more than 100 mF is used on an
output small signal analysis should be done to make sure that
sufficient phase margin is maintained. The maximum
allowable due to soft start current limit is given by the
following equation:
Switching Frequency
When switcher 2 is enabled and switcher 1 is disabled, the
switching frequency is approximately 120 kHz higher than
when switcher 1 is enabled and switcher 2 is either enabled
or disabled.
Conversion Ratio
C max +
The minimum conversion ratio is dictated by switching
frequency and the minimum on time. The minimum
achievable output is:
V OUT + 0.2
I OUT,startup t start
V OUT
Cmax: Maximum output capacitance (F)
IOUT,startup: Output current during soft start (A)
tstart: Soft-start time (s)
Vout: Regulated output voltage (V)
V IN
Maximum Output Capacitance
The maximum output capacitance is determined by the
amount the capacitor can be charged during soft start and the
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8
(eq. 2)
NCV896530
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 485C
ISSUE C
D
PIN 1
REFERENCE
EDGE OF PACKAGE
A
B
L1
ÇÇÇ
ÇÇÇ
ÇÇÇ
E
DETAIL A
Bottom View
(Optional)
0.15 C
2X
EXPOSED Cu
TOP VIEW
MOLD CMPD
0.15 C
2X
(A3)
DETAIL B
0.10 C
A1
ÉÉÉ
ÉÉÉ
A
10X
SIDE VIEW
A1
D2
C
DETAIL A
SOLDERING FOOTPRINT*
e
L
1
A3
DETAIL B
Side View
(Optional)
SEATING
PLANE
0.08 C
10X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND
MATERIAL ALONG SIDE EDGE. MOLD
FLASHING MAY NOT EXCEED 30 MICRONS
ONTO BOTTOM SURFACE OF TERMINAL b.
6. DETAILS A AND B SHOW OPTIONAL VIEWS
FOR END OF TERMINAL LEAD AT EDGE OF
PACKAGE.
7. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
5
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
2.40
2.60
3.00 BSC
1.70
1.90
0.50 BSC
0.19 TYP
0.35
0.45
0.00
0.03
2.6016
E2
10X
K
10
10X
0.10 C A B
0.05 C
1.8508
2.1746
6
3.3048
b
BOTTOM VIEW
NOTE 3
10X
0.5651
10X
0.5000 PITCH
0.3008
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Email: [email protected]
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For additional information, please contact your local
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NCV896530/D
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