2-phase Stepping Motor Driver

Ordering number : ENA2252A
STK682-010-E
Thick Film Hybrid IC
2-phase Stepping Motor Driver
http://onsemi.com
Overview
The STK682-010-E is a hybrid IC for use as a Bipolar, 2-phase stepping motor driver with PWM current control.
Function
 Output on-resistance (High side 0.3 Ω, Low side 0.25 Ω, Total 0.55 Ω ; Ta = 25C, IO = 2.5A)
 VMmax=36V(DC), Iopmax=3.0A
 2, 1-2, W1-2, 2W1-2, 4W1-2, 8W1-2, 16W1-2, 32W1-2 phase excitation are selectable
 With built-in automatic half current maintenance energizing function
 Over current protection circuit
 Thermal shutdown circuit
 Input pull down resistance
 With reset pin and enable pin
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
VMmax
36.0
V
Peak output current
Iopmax
3.0
A
Logic input voltage
VINmax
6.0
V
VREF input voltage
VREFmax
6.0
V
Operating substrate temperature
Tc
20 to +105
C
Storage temperature
Tstg
40 to +125
C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of this data sheet.
Semiconductor Components Industries, LLC, 2013
December, 2013
D1813HK 018-13-0030/D1113HK No.A2252-1/20
STK682-010-E
Recommended Operating Conditions at Tc = 25C
Parameter
Symbol
Supply voltage range
VM
Logic input voltage range
VCC input voltage range
VIN
VCC
VREF
Io1
Io2
Io3
VREF input voltage range
Output current1
Output current2
Output current3
Conditions
1-2 Phase-ex, Tc  90C
1-2 Phase-ex, Tc=105C
2 Phase-ex, Tc=105C
Ratings
Unit
9.0 to 32.0
V
0 to 5.0
0 to 5.0
0 to 3.0
3.0
2.5
1.8
V
V
V
A
A
A
Electrical Characteristics at Tc  25C, VCC = 5V
Parameter
Symbol
Conditions
min
Ratings
typ
70
max
100
3.3
4.6
mA
180
210
C
Unit
Standby mode current drain
IMstn
Current drain
IM
VCC=”L”
VCC=”H”, ENABLE="H"
No Load
Thermal shutdown temperature
TSD
Design guarantee
Thermal hysteresis width
∆TSD
Design guarantee
IinL1
VIN=0.8V
3
8
15
μA
IinH1
VCC
VIN=5V
30
50
70
μA
15pin=5V
51
83
115
μA
Vinh
Pins 2,3,16,17,18,19
2.0
Logic input low-level voltage
Vinl
Pins 2,3,16,17,18,19
FDT pin high-level voltage
Vfdth
Pin 6
3.5
FDT pin middle-level voltage
Vfdtm
Pin 6
1.1
FDT pin low-level voltage
Vfdtl
Pin 6
Chopping frequency
Fch
C1=100pF
Chopping frequency
Iosc1
10
μA
Chopping oscillator circuit
Vtup1
1
V
threshold voltage
Vtdown1
0.5
V
VREF pin input voltage
Iref
VREF=1.5V, CLK=10kHz
DOWN output residual voltage
VolDO
Idown=1mA, CLK=Low
Hold current switching frequency
Falert
Blanking time
Tb1
Logic pin input current
VCC pin input current
Logic input high-level voltage
150
C
40
V
0.8
58
μA
V
V
83
3.1
V
0.8
V
108
kHz
0.5
μA
40
mV
1.6
Hz
1
μs
Output block
Output on-resistance
Ronu
Rond
IO=2.0A, high-side ON resistance
IO=2.0A, low-side ON resistance
0.30
0.25
0.42
0.35
Ω
Ω
Output leakage current
Ioleak
VM=36V
50
μA
Diode forward voltage
VD
ID=2.0A
1.1
1.4
V
Current setting reference voltage
VRF
VREF=1.5V, Current ratio 100%
300
mV
256
μs
Output short-circuit protection block
Timer latch time
Tscp
No.A2252-2/20
STK682-010-E
Package Dimensions
unit : mm
SIP19 29.2x14.4
CASE 127CF
ISSUE O
1
19
No.A2252-3/20
STK682-010-E
Block diagram
OUT1A
NFA
VM
12
1
3
9
OUT1B OUT2A
OUT2B
11
8
7
NFB
VREG2
14
VREG1
Output pre stage
PGNDB
Output pre stage
PGNDA
Output pre stage
Output pre stage
Regulator 2
1.2k
Regulator 1
Output control logic
VREF
5
DOWN
Current select
circuit
Current select
circuit
Oscillator
Decay Mode
setting circuit
OSC2
1
10
GND
PGND
16
15
VCC
17 18
3
2
19
6
M2 M3 CW/CCW CLK ENABLE FDT
M1
4
OSC1
Application Circuit Example
CW/CCW
2
CLK
3
14
VM
VM=24V
7
OUT2B
STK682-010-E
VREF
5V
5
9
OUT1B
R1
VCC
15
M1
16
M2
17
M3
18
ENABLE
19
11
13
OUT2A
OUT1A
6
FDT
OSC1
GND
4
1
8
NFB
R2
C1
RFB
10
PGND
C3
12
C2
NFA
RFA
GND
No.A2252-4/20
STK682-010-E
Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Pin symbol
GND
CW/CCW
CLK
OSC1
VREF
FDT
OUT2B
NFB
OUT1B
PGND
OUT2A
NFA
OUT1A
VM
VCC
M1
M2
M3
ENABLE
Pin Functions
Circuit GND
Forward / Reverse signal input
Clock pulse signal input
Chopping frequency setting capacitor connection
Constant-current control reference voltage input
Decay mode select voltage input
B phase OUTB output
B phase current sense resistance connection
B phase OUTA output
Power GND
A phase OUTB output
A phase current sense resistance connection
A phase OUTA output
Motor supply connection
Chip enable input
Excitation-mode switching pin
Output enable signal input
No.A2252-5/20
STK682-010-E
Equivalent circuit diagram
Pin No.
3
2
19
18
17
16
15
Pin type
CLK
CW/CCW
ENABLE
M3
M2
M1
Equivalent Circuit Diagram
VCC
Internal reset
Input pin
13
10
14
12
11
9
8
7
OUT1A
PGND
VM
NFA
OUT2A
OUT1B
NFB
OUT2B
5
VREF
4
OSC1
6
FDT
No.A2252-6/20
STK682-010-E
Description of functions
(1) Excitation setting method
Set the excitation setting as shown in the following table by setting M1 pin, M2 pin and M3 pin
Input signal
Initial position
M3
M2
M1
MODE (Excitation)
A phase
current
B phase current
L
L
L
2 Phase
100%
100%
L
L
H
1-2 Phase
100%
0%
L
H
L
W1-2 Phase
100%
0%
L
H
H
2W1-2 Phase
100%
0%
H
L
L
4W1-2 Phase
100%
0%
H
L
H
8W1-2 Phase
100%
0%
H
H
L
16W1-2 Phase
100%
0%
H
H
H
32W1-2 Phase
100%
0%
The initial position is also the default state at start-up and excitation position at counter-reset in each excitation
mode
(2) Output current setting
Output current is set as shown below by the VREF pin (applied voltage) and a resistance value between
NFA (B) pin and GND.
IOUT = (VREF / 5) / NFA (B) resistance
* The setting value above is a 100% output current in each excitation mode.
(Example) When VREF=1.5V and NFA (B) resistance is 0.3 Ω, the setting current is shown below.
IOUT = (1.5 V / 5) / 0.3 Ω = 1.0 A
(3) Chip enable terminal/ VCC function
When Chip enable terminal/ VCC pin is at low levels, the IC enters stand-by mode, all logic is reset and output is
turned OFF.
When Chip enable terminal/ VCC pin is at high levels, the stand-by mode is released
(4) Step pin function
CLK pin step signal input allows advancing excitation step
Input
VCC
L
Operation
CLK
*
Stand-by mode
H
Excitation step feed
H
Excitation step hold
No.A2252-7/20
STK682-010-E
(5) Forward / reverse switching function
CW/CCW
L
H
Operation
CW
CCW
CW / CCW
CW mode
CCW mode
CW mode
CLK
(1)
Excitation
(2)
(3)
(4)
(5)
(6) (5)
(4) (3)
(4) (5)
position
A phase output
B phase output
The internal D/A converter proceeds by a bit on the rising edge of the step signal input to the CLK pin. In addition,
CW and CCW mode are switched by CW and CCW pin setting.
In CW mode, the B phase current is delayed by 90 relative to the A phase current. In CCW mode, the B phase
current is advanced by 90 relative to the A phase current.
(6) Output enable function
When the ENABLE pin is set Low, the output is forced OFF and goes to high impedance. However, the internal logic
circuits are operating, so the excitation position proceeds when the CLK is input. Therefore, when ENABLE pin is
returned to High, the output level conforms to the excitation position proceeded by the CLK input.
ENABLE
CLK
MO
A phase output
0%
B phase output
High impedance output
No.A2252-8/20
STK682-010-E
(7) DECAY mode
The DECAY mode of the output current becomes only MIXED DECAY.
DECAY method
SLOW DECAY
MIXED DECAY
FAST DECAY
FDT voltage
3.5V to
1.1V to 3.1V or OPEN
to 0.8V
(8) Chopping frequency setting function
Chopping frequency is set as shown below by a capacitor between OSC1 pin and GND.
Fch = 1 / (C1+20pF / 10×10-6) (Hz)
(Example) When Cosc1=100pF, the chopping frequency is shown below.
Fch = 1 / ((20+ 100)×10-12 / 10×10-6) (Hz) = 83.3 (kHz)
Note
 The 20pF is a stray capacitance which is involved by the package of STK682-010-E.
(9) Output short-circuit protection circuit
Build-in output short-circuit protection circuit makes output to enter in stand-by mode. This function prevents the IC
from damaging when the output shorts circuit by a voltage short or a ground short, etc. When output short state is
detected, short-circuit detection circuit starts the operating and output is once turned OFF. After the timer latch time
(typ : 256μs), output is turned ON again. Still the output is at short state, the output is turned OFF and fixed in
stand-by mode.
When output is fixed in stand-by mode by output short protection circuit, output is released the latch by setting Chip
enable terminal/ VCC="L"
(10) Internal DOWN pin
The DOWN pin is an open drain connection.
This pin is turned ON when no rising edge of CLK between the input signals while a period determined by a
capacitor between OSC2 and GND, and outputs at low levels.
The DOWN pin output in once turned ON, is turned OFF at the next rising edge of CLK.
Holding current switching time (0.6sectyp) is set by an internal capacitor between OSC2 pin and GND.
(11) Output current tolerance
STK682-010-E Output current tolerance Io Tc
Output current (Iopeak) Io A
3.5
3
2.5
2
1-2 phase excitation
and more
1.5
2 phase excitation
1
0.5
0
0
10
20
30
40
50
60
70
80
90
100 110
Operating substrate temperature Tc C
No.A2252-9/20
STK682-010-E
(12) When mounting multiple drivers on a single PC board
When mounting multiple drivers on a single PC board, the GND design should mount a VCC
decoupling capacitor,C2 and C3, for each driver to stabilize the GND potential of the other drivers.
The key wiring points are as follows.
VM=24V
5V
5V
CW/CC
R1
R2
CLK
CW/CC
2
14
VM
3
FDT
6 STK682-010-E
VREF
5
OUT2
VCC
7
15
M1 16
OUT1
9
M2
17
M3
18
OUT
11 2A
ENABLE
19
OSC1
4
OUT
GND
13
1
PGND
8 10 12
NFB
NFA
RFB
C1
RFA
CLK
R1
FDT
VREF
2
3
6
14
STK682-010-E
5
VCC
7
15
M1 16
M2
17
M3
18
ENABLE
19
OSC1
4
GND
1
2phase
stepping
motor
9
11
13
8
NFB
R2
C3
C2
VM
RFB
PGND
10
OUT2
OUT1
2phase
stepping
OUT2A motor
OUT
12
NFA
RFA
C3
C2
C1
GND
No.A2252-10/20
STK682-010-E
(13) Output current vector locus (1 step normalized 90)
Channel 1 current ratio (%)
100.0
66.7
33.3
0.0
0.0
33.3
66.7
100.0
Channel 2 current ratio (%)
No.A2252-11/20
STK682-010-E
(14) Current setting ratio in each excitation mode
32W1-2 phase(%)16W1-2 phase(%) 8W1-2 phase(%) 4W1-2 phase(%) 2W1-2 phase(%) W1-2 phase(%)
STEP Ach Bch
θ0
100
0
θ1
100
1
θ2
100
2
θ3
100
4
θ4
100
5
θ5
100
6
θ6
100
7
θ7
100
9
θ8
100 10
θ9
99 11
θ10
99 12
θ11
99 13
θ12
99 15
θ13
99 16
θ14
99 17
θ15
98 18
θ16
98 20
θ17
98 21
θ18
98 22
θ19
97 23
θ20
97 24
θ21
97 25
θ22
96 27
θ23
96 28
θ24
96 29
θ25
95 30
θ26
95 31
θ27
95 33
θ28
94 34
θ29
94 35
θ30
93 36
θ31
93 37
θ32
92 38
θ33
92 39
θ34
91 41
θ35
91 42
θ36
90 43
θ37
90 44
θ38
89 45
θ39
89 46
θ40
88 47
θ41
88 48
θ42
87 49
θ43
86 50
θ44
86 51
θ45
85 52
θ46
84 53
θ47
84 55
θ48
83 56
θ49
82 57
82 58
θ50
θ51
81 59
θ52
80 60
θ53
80 61
θ54
79 62
θ55
78 62
θ56
77 63
θ57
77 64
θ58
76 65
θ59
75 66
θ60
74 67
θ61
73 68
θ62
72 69
θ63
72 70
θ64
71 71
1-2 phase(%)
2 phase(%)
32W1-2 phase(%)16W1-2 phase(%) 8W1-2 phase(%) 4W1-2 phase(%) 2W1-2 phase(%) W1-2 phase(%) 1-2 phase(%)
Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch STEP Ach
100
0 100
0 100
0 100
0 100
0 100
0
θ65
70
θ66
69
100
2
θ67
68
θ68
67
100
5 100
5
θ69
66
θ70
65
100
7
θ71
64
θ72
63
100 10 100 10 100 10
θ73
62
θ74
62
99 12
θ75
61
θ76
60
99 15 99 15
θ77
59
θ78
58
99 17
θ79
57
θ80
56
98 20 98 20 98 20 98 20
θ81
55
θ82
53
98 22
θ83
52
θ84
51
97 24 97 24
θ85
50
θ86
49
96 27
θ87
48
θ88
47
96 29 96 29 96 29
θ89
46
θ90
45
95 31
θ91
44
θ92
43
94 34 94 34
θ93
42
θ94
41
93 36
θ95
39
θ96
38
92 38 92 38 92 38 92 38 92 38
θ97
37
θ98
36
91 41
θ99
35
θ100
34
90 43 90 43
θ101
33
θ102
31
89 45
θ103
30
θ104
29
88 47 88 47 88 47
θ105
28
θ106
27
87 49
θ107
25
θ108
24
86 51 86 51
θ109
23
θ110
22
84 53
θ111
21
θ112
20
83 56 83 56 83 56 83 56
θ113
18
θ114
17
82 58
θ115
16
θ116
15
80 60 80 60
θ117
13
θ118
12
79 62
θ119
11
θ120
10
77 63 77 63 77 63
θ121
9
θ122
7
76 65
θ123
6
θ124
5
74 67 74 67
θ125
4
θ126
2
72 69
θ127
1
θ128
0
71 71 71 71 71 71 71 71 71 71 71 71 100 100
Bch Ach
72
72 69
73
74 67
75
76 65
77
77 63
78
79 62
80
80 60
81
82 58
82
83 56
84
84 53
85
86 51
86
87 49
88
88 47
89
89 45
90
90 43
91
91 41
92
92 38
93
93 36
94
94 34
95
95 31
95
96 29
96
96 27
97
97 24
97
98 22
98
98 20
98
99 17
99
99 15
99
99 12
99
100 10
100
100
7
100
100
5
100
100
2
100
100
0
2 phase(%)
Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch
72
74
67
74
63
77
60
80
56
83
51
86
47
88
43
90
38
92
34
94
29
96
24
97
20
98
15
99
76
77
63
77
56
83
47
88
38
92
29
96
20
98
79
80
82
83
56
83
38
92
20
98
84
86
87
88
89
90
91
92
38
92
93
94
95
96
96
97
98
98
99
99
99
100
10 100
10 100
100
100
5 100
100
100
0 100
0 100
0 100
0 100
0 100
No.A2252-12/20
STK682-010-E
(15) Current wave example in each excitation mode (2 phase, 1-2 phase, W1-2 phase, 4W1-2 phase)
2 phase excitation (CW mode)
CLK
(%)
100
IA
0
(%)
-100
100
IB
0
-100
1-2 phase excitation (CW mode)
CLK
(%)
100
IA
0
-100
(%)
100
IB
0
-100
No.A2252-13/20
STK682-010-E
W1-2 phase excitation (CW mode)
CLK
(%)
100
IA
0
-100
(%)
100
IB
0
-100
4W1-2 phase excitation (CW mode)
STP
MO
(%)
100
50
I1
0
-50
-100
(%)
100
50
I2
0
-50
-100
No.A2252-14/20
STK682-010-E
(16) Current control operation
SLOW DECAY current control operation
When FDT pin voltage is a voltage over 3.5 V, the constant-current control is operated in SLOW
DECAY mode.
(Sine-wave increasing direction)
CLK
CLK
Setting current
Setting current
Coil current
Blanking Time
fchop
Current mode
CHARGE
SLOW
CHARGE
SLOW
(Sine-wave decreasing direction)
CLK
S ettin g c u rren t
C o il c u rre n t
S ettin g c u rren t
B la n k in g Tim e
fch o p
C u rren t m o d e
CHARGE
SLOW
B la n k in g Tim e
SLOW
B la n k in g Tim e
SLO W
Each of current modes operates with the follow sequence.
 The IC enters CHARGE mode at a rising edge of the chopping oscillation.
(A period of CHARGE mode (Blanking Time) is forcibly present in approximately 1 μs, regardless of the current
value of the coil current (ICOIL) and set current (IREF) ).
 After the period of the blanking time, the IC operates in CHARGE mode until ICOIL ≥ IREF. After that,
the mode switches to the SLOW DECAY mode and the coil current is attenuated until the end of a
chopping period.
At the constant-current control in SLOW DECAY mode, following to the setting current from the coil
current may take time (or not follow) for the current delay attenuation.
No.A2252-15/20
STK682-010-E
FAST DECAY current control operation
When FDT pin voltage is a voltage under 0.8V, the constant-current control is operated in FAST DECAY mode.
(Sine-wave increasing direction)
CLK
Setting current
Setting current
Coil current
Blanking Time
fchop
Current mode
CHARGE
FAST
CHARGE
FAST
(Sine-wave decreasing direction)
CLK
Setting current
Coil current
Blanking Time
Setting current
fchop
Current mode
CHARGE
FAST
Blanking Time
FAST
CHARGE
FAST
Each of current modes operates with the follow sequence.
The IC enters CHARGE mode at a rising edge of the chopping oscillation.
(A period of CHARGE mode (Blanking Time) is forcibly present in approximately 1s, regardless of the current value
of the coil current (ICOIL) and set current (IREF)).
After the period of the blanking time, The IC operates in CHARGE mode until ICOIL  IREF. After that,
the mode switches to the FAST DECAY mode and the coil current is attenuated until the end of a chopping period.
At the constant-current control in FAST DECAY mode, following to the setting current from the coil current takes
short-time for the current fast attenuation, but, the current ripple value may be higher.
MIXED DECAY current control operation
No.A2252-16/20
STK682-010-E
(Sine-wave increasing direction)
CLK
STP
Setting current
Setting current
Coil current
Blanking Time
fchop
Current mode
CHARGE
SLOW
FAST
CHARGE
SLOW
FAST
(Sine-wave decreasing direction)
CLK
Setting current
Coil current
Setting current
Blanking Tim e
fchop
Current m ode
CHAR GE
SLO W
FAST
Blanking Tim e
FAST
CH AR GE
SLO W
Each of current modes operates with the follow sequence.
The IC enters CHARGE mode at a rising edge of the chopping oscillation.
(A period of CHARGE mode (Blanking Time) is forcibly present in approximately 1 μs, regardless of the current
value of the coil current (ICOIL) and set current (IREF)).
In a period of Blanking Time, the coil current (ICOIL) and the setting current (IREF) are compared.
If an ICOIL = IREF state exists during the charge period:
The IC operates in CHAGE mode until ICOIL  IREF. After that, it switches to SLOW DECAY mode and then
switches to FAST DECAY mode in the last approximately 1 μs of the period.
If no ICOIL = IREF state exists during the charge period:
The IC switches to FAST DECAY mode and the coil current is attenuated with the FAST DECAY operation until the
end of a chopping period.
The above operation is repeated.
Normally, in the sine wave increasing direction the IC operates in SLOW (+FAST) DECAY mode, and in the sine
wave decreasing direction the IC operates in FAST DECAY mode until the current is attenuated and reaches the set
value and the IC operates in SLOW (+FAST) DECAY mode.
No.A2252-17/20
STK682-010-E
Power Dissipation
Power dissipation calculation of STK682-010-E following becomes.
2-phase excitation
Pd=IOH×(Ronu + Rond)2
1-2-phase excitation
Pd=0.71×IOH×(Ronu + Rond)2
Please by substituting from electrical characteristic table value of Rond and Ronu.
Thermal design
[Operating range in which a heat sink is not used]
Use of a heat sink to lower the operating substrate temperature of the HIC (Hybrid IC) is effective in increasing the
quality of the HIC.
The size of heat sink for the HIC varies depending on the magnitude of the average power loss, PdAV, within the HIC.
The value of PdAV increases as the output current increases. To calculate PdAV, refer to “Calculating Internal HIC
Loss for the STK672-640C-E in the specification document.
Calculate the internal HIC loss, PdAV, assuming repeat operation such as shown in Figure 1 below, since conduction
during motor rotation and off time both exist during actual motor operations,
IO1
Motor phase current
(sink side)
IO2
0A
-IO1
T1
T2
T3
T0
Figure 1 Motor Current Timing
T1 : Motor rotation operation time
T2 : Motor hold operation time
T3 : Motor current off time
T2 may be reduced, depending on the application.
T0 : Single repeated motor operating cycle
IO1 and IO2 : Motor current peak values
Due to the structure of motor windings, the phase current is a positive and negative current with a pulse form.
Note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ.
The hybrid IC internal average power dissipation PdAV can be calculated from the following formula.
PdAV= (T1P1+T2P2+T30)  TO ---------------------------- (I)
(Here, P1 is the PdAV for IO1 and P2 is the PdAV for IO2)
If the value calculated using Equation (I) is 1.5W or less, and the ambient temperature, Ta, is 60C or less, there is no
need to attach a heat sink. Refer to Figure 2 for operating substrate temperature data when no heat sink is used.
[Operating range in which a heat sink is used]
Although a heat sink is attached to lower Tc if PdAV increases, the resulting size can be found using the value of
c-a in Equation (II) below and the graph depicted in Figure 3.
c-a = (Tc max-Ta)  PdAV ---------------------------- (II)
Tc max : Maximum operating substrate temperature =105C
Ta : HIC ambient temperature
Although a heat sink can be designed based on equations (I) and (II) above, be sure to mount the HIC in a set and
confirm that the substrate temperature, Tc, is 105C or less.
No.A2252-18/20
STK682-010-E
Figure 2 Substrate temperature rise, Tc (no heat
sink) - Internal average power dissipation, PdAV
Tc - PdAV
70
60
50
40
30
20
10
0
0
0.5
1.0
1.5
2.0
c-a - S
100
Heat sink thermal resistance, c-a - C/W
80
Substrate temperature rise, Tc - C
Figure 3 Heat sink area (Board thickness: 2mm) - c-a
2.5
3.0
Hybrid IC internal average power dissipation, PdAV - W
7
5
3
2
Wi t
7
5
ha
3
2
1.0
10
3.5
Wit
10
2
3
5
hn
o su
rfac
e fi
nish
flat
blac
k su
rfac
e fi
nish
7
100
2
3
Heat sink area, S - cm2
ITF02553
5
7 1000
ITF02554
Mitigated Curve of Package Power Loss, PdPK, vs. Ambient Temperature, Ta
Package power loss, PdPK, refers to the average internal power loss, PdAV, allowable without a heat sink.
The figure below represents the allowable power loss, PdPK, vs. fluctuations in the ambient temperature, Ta.
Power loss of up to 3.1W is allowable at Ta=25C, and of up to 1.75W at Ta=60C.
Allowable power dissipation, PdPK(no heat sink) - Ambient temperature, Ta
PdPK - Ta
Allowable power dissipation, PdPK - W
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
20
40
60
80
Ambient temperature,Ta - C
100
120
ITF02511
No.A2252-19/20
STK682-010-E
ORDERING INFORMATION
Device
STK682-010-E
Package
SIP-19
(Pb-Free)
Shipping (Qty / Packing)
15 / Tube
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PS No.A2252-20/20
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