3-Channel Constant-Current RGB LED Driver

CAT4103
3-Channel Constant-Current
RGB LED Driver
Description
The CAT4103 is a 3−channel, linear based constant−current LED
driver designed for RGB LED control, requiring no inductor and
provides a low noise operation. LED channel currents up to 175 mA
are programmed independently via separate external resistors. Low
output voltage operation of 0.4 V at 175 mA allows for more power
efficient designs across wider supply voltage range. The three LED
pins are compatible with high voltage up to 25 V supporting
applications with long strings of LEDs.
A high−speed 4−wire 25 MHz serial interface controls each
individual channel using a shift register and latch configuration.
Output data pins allow multiple devices to be cascaded and
programmed via one serial interface with no need for external drivers
or timing considerations. The device also includes a blanking control
pin (BIN) that can be used to disable all channels independently of the
interface.
Thermal shutdown protection is incorporated in the device to
disable the LED outputs whenever the die temperature exceeds 150°C.
The device is available in a 16−lead SOIC package.
Features
• 3 Independent Current Sinks Rated to 25 V
• LED Current to 175 mA per Channel Set by Separate External
•
•
•
•
•
•
•
•
Resistors
High−speed 25 MHz 4−wire Serial Interface
Buffered Output Drivers to Ensure Data Integrity
Cascadable Devices
Low Dropout Current Source (0.4 V at 175 mA)
3 V to 5.5 V Logic Supply
Thermal Shutdown Protection
16−lead SOIC Package
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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SOIC−16
V SUFFIX
CASE 751BG
PIN CONNECTIONS
GND
1
VDD
BIN
BOUT
LIN
LOUT
SIN
SOUT
CIN
COUT
RSET3
LED1
RSET2
LED2
LED3
RSET1
(Top View)
MARKING DIAGRAM
L4A
CAT4103VB
YMXXXX
L = Assembly Location
4 = Lead Finish − NiPdAu
A = Product Revision (Fixed as “A”)
CAT4103V = Device Code
B = Leave Blank
Y = Production Year (Last Digit)
M = Production Month (1−9, A, B, C)
XXXX = Last Four Digits of Assembly Lot Number
Applications
• Multi−color, Intelligent LED, Architectural Lighting
• High−visual Impact LED Signs and Displays
• LCD Backlight
ORDERING INFORMATION
Device
CAT4103V−GT2
(Note 1)
Package
Shipping
SOIC−16
(Pb−Free)
2,000/
Tape & Reel
1. Lead Finish NiPdAu
© Semiconductor Components Industries, LLC, 2010
March, 2010 − Rev. 1
1
Publication Order Number:
CAT4103/D
CAT4103
VIN
5 V to 25 V
VDD
3 V to 5.5 V
C1
1 mF
VDD
RED
LED1
GREEN
LED2
BOUT
BIN
CONTROLLER
LIN
SIN
CAT4103
LOUT
SOUT
NEXT
CAT4103
DEVICE
COUT
CIN
GND
BLUE
LED3
RSET1
R1
RSET2
R2
RSET3
R3
Figure 1. Typical Application Circuit
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
6
V
Input Voltage Range (SIN, BIN, CIN, LIN)
−0.3 V to VDD+0.3 V
V
Output voltage range (SOUT, BOUT, COUT, LOUT)
−0.3 V to VDD+0.3 V
V
LED1, LED2, LED3 Voltage
25
V
DC Output Current on LED1 to LED3
200
mA
Storage Temperature Range
−55 to +160
_C
Junction Temperature Range
−40 to +150
_C
Lead Soldering Temperature (10 sec.)
300
_C
ESD Rating: All Pins
Human Body Model
Machine Model
2000
200
VDD Voltage
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 2. RECOMMENDED OPERATING CONDITIONS
Range
Units
VDD
Parameter
3.0 to 5.5
V
Voltage applied to LED1 to LED3, outputs off
up to 25
V
Voltage applied to LED1 to LED3, outputs on
up to 6 (Note 2)
V
2 to 175
mA
−40 to +85
_C
Output Current on LED1 to LED3
Ambient Temperature Range
2. Keeping the LEDx pin voltage below 6 V in operation is recommended to minimize thermal dissipation in the package.
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CAT4103
Table 3. ELECTRICAL OPERATING CHARACTERISTICS (Min and Max values are over recommended operating conditions
unless specified otherwise. Typical values are at VIN = 5.0 V, TAMB = 25°C.)
Name
Symbol
Conditions
Min
Typ
Max
Units
DC CHARACTERISTICS
IDD1
Supply Current Outputs Off
VLED = 5 V, RSET = 24.9 kW
2
5
mA
IDD2
Supply Current Outputs Off
VLED = 5 V, RSET = 5.23 kW
4
10
mA
IDD3
Supply Current Outputs On
VLED = 0.5 V, RSET = 24.9 kW
2
5
mA
IDD4
Supply Current Outputs On
VLED = 0.5 V, RSET = 5.23 kW
4
10
mA
ILKG
LED Output Leakage
VLED = 5 V, Outputs Off
1
mA
RLIN
LIN Pull−down Resistance
140
180
250
kW
RBIN
BIN Pull−up Resistance
140
180
250
kW
VIH
VIL
SIN, BIN, CIN, LIN logic high level
SIN, BIN, CIN, LIN logic low level
IIL
Logic Input Leakage Current (CIN, SIN)
VI = VDD or GND
xOUT Logic High Output Voltage
xOUT Logic Low Output Voltage
IOH = −1 mA
IOL = 1 mA
VOH
VOL
VRSET
−1
0.7x VDD
V
0.3x VDD
RSETx Regulated Voltage
−5
0
5
VCC − 0.3 V
mA
V
0.3
1.17
1.2
1.23
V
TSD
Thermal Shutdown
150
°C
THYS
Thermal Hysteresis
20
°C
ILED/IRSET
VUVLO
RSET to LED Current Gain ratio
100 mA LED Current
Undervoltage Lockout (UVLO) Threshold
400
1.8
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3
V
CAT4103
Table 4. TIMING CHARACTERISTICS (Min and Max values are over recommended operating conditions unless specified
otherwise. Typical values are at VIN = 5.0 V, TAMB = 25°C.)
Name
Symbol
Conditions
Min
Typ
Max
Units
25
MHz
CIN
fcin
CIN Clock Frequency
tcwh
CIN Pulse Width High
18
ns
tcwl
CIN Pulse Width Low
18
ns
tssu
Setup time SIN to CIN
4
ns
tsh
Hold time SIN to CIN
4
ns
Tlwh
LIN Pulse width
20
ns
tlchd
Hold time LIN to CIN
4
ns
tlcsu
Setup time LIN to CIN
8
ns
SIN
LIN
LEDn
tledplon
Turn on Propagation delay LIN
LIN to LED(n) on
380
ns
tledploff
Turn off Propagation delay LIN
LIN to LED(n) off
130
ns
tledpbon
Turn on Propagation delay BIN
BIN to LED(n) on
380
ns
tledpboff
Turn off Propagation delay BIN
BIN to LED(n) off
130
ns
tledr
LED rise time (10% to 90%)
Pullup resistor = 50 W to 3.0 V
160
ns
tledf
LED fall time (90% to 10%)
Pullup resistor = 50 W to 3.0 V
140
ns
tsr
SOUT rise time (10% to 90%)
CL = 15 pF
5
ns
tsf
SOUT fall time (90% to 10%)
CL = 15 pF
5
ns
tsdf
Propagation delay time SOUT
CIN falling to SOUT falling
6
18
ns
tsdr
Propagation delay time SOUT
CIN falling to SOUT rising
6
18
ns
tcr
COUT rise time (10% to 90%)
CL = 15 pF
5
ns
tcf
COUT fall time (90% to 10%)
CL = 15 pF
5
ns
tcdf
Propagation delay time COUT
CIN falling to COUT falling
4
10
ns
tcdr
Propagation delay time COUT
CIN rising to COUT rising
4
10
ns
tlr
LOUT rise time (10% to 90%)
CL = 15 pF
5
SOUT
COUT
LOUT
ns
tlf
LOUT fall time (90% to 10%)
CL = 15 pF
5
tldf
Propagation delay time LOUT
LIN falling to LOUT falling
4
10
ns
ns
tldr
Propagation delay time LOUT
LIN rising to LOUT rising
5
10
ns
tbr
BOUT rise time (10% to 90%)
CL = 15 pF
5
ns
tbf
BOUT fall time (90% to 10%)
CL = 15 pF
5
ns
tbdf
Propagation delay time BOUT
BIN falling to BOUT falling
6
20
ns
tbdr
Propagation delay time BOUT
BIN rising to BOUT rising
8
20
ns
BOUT
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CAT4103
1/fcin
CIN
tssu
tsh
tcwl
tcwh
SIN
tsdf
tlchd
tlcsu
tsdr
SOUT
tlwd
LIN
Figure 2. Timing Diagram A
tledploff
tledplon
LIN
tledpboff
BIN
tledpbon
LED(n)
Figure 3. Timing Diagram B
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CAT4103
TYPICAL PERFORMANCE CHARACTERISTICS
(VIN = 5 V, VDD = 5 V, C1 = 1 mF, TAMB = 25°C unless otherwise specified.)
8.0
No Load
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
1.2
1.0
0.8
0.6
0.4
3.0
3.5
4.0
4.5
5.0
2.0
100
200
300
400
RSET CURRENT (mA)
Figure 4. Quiescent Current vs. Input Voltage
(ILED = 0 mA)
Figure 5. Quiescent Current vs. RSET Current
200
Full Load
160
LED CURRENT (mA)
5.5
5.0
4.5
120
80
40
3.0
3.5
4.0
4.5
5.0
0
5.5
0
0.2
0.4
0.6
0.8
INPUT VOLTAGE (V)
LED PIN VOLTAGE (V)
Figure 6. Quiescent Current vs. Input Voltage
(ILED = 175 mA)
Figure 7. LED Current vs. LED Pin Voltage
200
200
160
160
120
80
40
0
0
INPUT VOLTAGE (V)
LED CURRENT (mA)
QUIESCENT CURRENT (mA)
LED CURRENT (mA)
4.0
0
5.5
6.0
4.0
6.0
1.0
120
80
40
3.0
3.5
4.0
4.5
5.0
0
5.5
−40
0
40
80
INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 8. LED Current Change vs. Input
Voltage
Figure 9. LED Current Change vs.
Temperature
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120
CAT4103
TYPICAL PERFORMANCE CHARACTERISTICS
1.30
1.30
1.25
1.25
RSET VOLTAGE (V)
RSET VOLTAGE (V)
(VIN = 5 V, VDD = 5 V, C1 = 1 mF, TAMB = 25°C unless otherwise specified.)
1.20
1.15
1.10
3.0
3.5
4.0
4.5
5.0
1.20
1.15
1.10
−40
5.5
0
40
80
INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 10. RSET Pin Voltage vs. Input Voltage
Figure 11. RSET Pin Voltage vs. Temperature
200
LED CURRENT (mA)
160
120
80
40
0
0
120
15
30
45
60
RSET (kW)
Figure 12. LED Current vs. RSET Resistor
Figure 13. BIN Transient Response
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CAT4103
Table 5. PIN DESCRIPTIONS
Name
Pin Number
Function
GND
1
Ground Reference
BIN
2
Blank input pin
LIN
3
Latch Data input pin
SIN
4
Serial Data input pin
CIN
5
Serial Clock input pin
RSET3
6
LED current set pin for LED3
RSET2
7
LED current set pin for LED2
RSET1
8
LED current set pin for LED1
LED3
9
LED channel 3 cathode terminal
LED2
10
LED channel 2 cathode terminal
LED1
11
LED channel 1 cathode terminal
COUT
12
Serial Clock output pin
SOUT
13
Serial Data output pin
LOUT
14
Latch Data output pin
BOUT
15
Blank output pin
VDD
16
Device Supply pin
Pin Function
GND is the ground reference pin for the entire device. This
pin must be connected to the ground plane on the PCB.
BIN is the blank input used to disable all channels. When
low, all LED channels are enabled according to the output
latch content. When high, all LED channels are turned off.
This pin can be used to turn all the LEDs off while preserving
the data in the output latches.
LIN is the latch data input. On the rising edge of LIN, data
is loaded from the 3−bit serial shift register into the output
register latch. On the falling edge of LIN the data is latched
in the output register and isolated from the state of the serial
shift register.
SIN is the serial data input. Data is loaded into the internal
register on each rising edge of CIN.
CIN is the serial clock input. On each rising CIN edge, data
is transferred from SIN to the internal 3−bit serial shift
register.
RSET1 to RSET3 are the LED current set inputs. The
current pulled out of these pins will be mirrored in the
corresponding LED channel with a gain of 400.
LED1 to LED3 are the LED current sink inputs. These pins
are connected to the bottom cathodes of the LED strings.
The current sinks bias the LEDs with a current equal to 400
times the RSET pin current. For the LED sink to operate
correctly, the voltage on the LED pin must be above 0.4 V.
Each LED channel can withstand and operate with voltages
up to 25 V.
COUT is a driven output of CIN and can be connected to the
next device in the cascade.
SOUT is the output of the 3−bit serial shift register. Connect
to SIN of the next device in the cascade. SOUT is clocked
on the falling edge of CIN.
LOUT is a driven output of LIN and can be connected to the
next chip in the cascade.
BOUT is a driven output of BIN and can be connected to the
next chip in the cascade.
VDD is the positive supply pin voltage for the entire device.
A small 1 mF ceramic capacitor is recommended close to the
pin.
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CAT4103
Block Diagram
LED1 LED2 LED3
1.2 V Ref
BIN
LIN
+
VDD
CURRENT
SINKS
Current Setting
RSET1
Current Setting
RSET2
Current Setting
RSET3
BOUT
BLANK
LATCH
L0
L1
L2
LOUT
SIN
CIN
SHIFT
REGISTER
S0
S1
S2
D Q
SOUT
CK
CLOCK
COUT
GND
Figure 14. CAT4103 Functional Block Diagram
Basic Operation
The CAT4103 uses 3 independent current sinks to
accurately regulate the current in each LED channel to 400
times the current sink from the corresponding RSET pin.
Each of the resistors tied to the RSET1, RSET2, RSET3 pins
set the current respectively in the LED1, LED2, and LED3
channels. Table 6 shows some standard resistor values for
RSET and the corresponding LED current.
A high−speed 4−wire interface is provided to program the
state of each LED channel ON or OFF.
The 4−wire interface contains a 3−bit serial−to−parallel
shift register (S0−S2) and a 3−bit latch (L0−L2). The shift
register operates on a first−in first−out (FIFO) basis. The
most significant bit S2 corresponds to the first data entered
in from SIN. Programming the serial−to−parallel register is
accomplished via SIN and CIN input pins. On each rising
edge of the CIN signal the data from SIN is moved through
the shift register serially. Data is also moved out of SOUT
to the next device if programming more than one device on
the same interface.
On the rising edge of LIN, the data content of the serial to
parallel shift register is reflected in the latches. On the falling
edge of LIN, the state of the serial−to−parallel register at that
particular time is saved in the latches and does not change
regardless of the content of the serial to parallel register.
BIN is used to disable all LEDs off at one time while still
maintaining the data contents of the latch register. BIN is an
active low input pin. When low the outputs reflect the data
in the latches. When high the outputs are all high impedance
(LEDs off).
All 4−wire inputs have a corresponding output driver for
cascaded systems (SOUT, COUT, LOUT, BOUT). These
output buffers allow many CAT4103 drivers to be cascaded
without signal and timing degradation due to long wire
interconnections.
Table 6. RSET RESISTOR SETTINGS
LED Current [mA]
RSET [kW]
20
24.9
60
8.45
100
5.23
175
3.01
Tight current regulation for all channels is possible over
a wide range of input and LED voltages due to independent
current sensing circuitry on each channel. The LED
channels have a low dropout of 0.4 V or less for all current
ranges and supply voltages. This helps improve heat
dissipation and efficiency over other competing solutions.
Upon power−up, an under−voltage lockout circuit clears
all latches and shift registers and sets all outputs to off. Once
the VDD supply voltage is greater than the under−voltage
lockout threshold, the device can be programmed.
Pull−up and pull−down resistors are internally provided to
set the state of the BIN and LIN pins to low current off state
when not externally driven.
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CAT4103
Application Information
Cascading Multiple Devices
The CAT4103 is designed to be cascaded for driving
multiple RGD LEDs. Figure 16 shows three CAT4103
drivers cascaded together. The programming data from the
controller travels serially through each device. Figure 15
shows a programming example turning on the following
LED channels: BLUE3, GREEN2 and RED1. The
programming waveforms are measured from the controller
to the inputs of the first CAT4103.
Figure 15. Programming Example
5V
C1
C2
C3
1 mF
1 mF
1 mF
RED1
CONTROLLER
VDD LED1
GREEN1 BLUE1
LED2
BIN
LIN
SIN
C AT4103
#1
CIN
GND RSET1 RSET2
R1
R2
LED3
RED2
VDD LED1
BOUT
BIN
LOUT
LIN
SOUT
SIN
COUT
CIN
RSET3
R3
GREEN2 BLUE2
LED2
C AT4103
#2
GND RSET1 RSET2
R4
R5
LED3
BOUT
BIN
LOUT
LIN
SOUT
SIN
COUT
CIN
RSET3
R6
Figure 16. Three Cascaded CAT4103 Devices
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RED3
VDD LED1
GREEN3 BLUE3
LED2
LED3
BOUT
C AT4103
#3
LOUT
SOUT
COUT
GND RSET1 RSET2
R7
R8
RSET3
R9
CAT4103
Power Dissipation
Recommended Layout
The power dissipation (PD) of the CAT4103 can be
calculated as follows:
Bypass capacitor C1 should be placed as close to the IC as
possible. RSET resistors should be directly connected to the
GND pin of the device. For better thermal dissipation,
multiple via can be used to connect the GND pad to a large
ground plane. It is also recommended to use large pads and
traces on the PCB wherever possible to spread out the heat.
The LEDs for this layout are driven from a separate supply
(VLED+), but they can also be driven from the same supply
connected to VDD.
P D + (V DD
I DD) ) S(V LEDN
I LEDN)
where VLEDN is the voltage at the LED pin, and ILEDN is the
associated LED current. Combinations of high VLED
voltage or high ambient temperature can cause the CAT4103
to enter thermal shutdown. In applications where VLEDN is
high, a resistor can be inserted in series with the LED string
to lower PD.
Thermal dissipation of the junction heat consists
primarily of two paths in series. The first path is the junction
to the case (qJC) thermal resistance which is defined by the
package style, and the second path is the case to ambient
(qCA) thermal resistance, which is dependent on board
layout. The overall junction to ambient (qJA) thermal
resistance is equal to:
q JA + q JC ) q CA
For a given package style and board layout, the operating
junction temperature TJ is a function of the power
dissipation PD, and the ambient temperature, resulting in the
following equation:
T J + T AMB ) P D (q JC ) q CA) + T AMB ) P D q JA
When mounted on a double−sided printed circuit board
with two square inches of copper allocated for “heat
spreading”, the resulting qJA is about 74°C/W.
For example, at 60°C ambient temperature, the maximum
power dissipation is calculated as follow:
P Dmax +
Figure 17. Recommended Layout
(T Jmax * T AMB)
(150 * 60)
+
+ 1.2 W
q JA
74
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CAT4103
PACKAGE DIMENSIONS
SOIC−16, 150 mils
CASE 751BG−01
ISSUE O
SYMBOL
E1
E
MIN
NOM
MAX
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
D
9.80
9.90
10.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
0.25
1.27 BSC
e
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
PIN#1 IDENTIFICATION
TOP VIEW
D
h
q
A
e
b
A1
c
L
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAT4103
Example of Ordering Information (Note 5)
3.
4.
5.
6.
7.
Prefix
Device #
Suffix
CAT
4103
V
−G
T2
Company ID
(Optional)
Product Number
4103
Package
V: SOIC
Lead Finish
G: NiPdAu
Blank: Matte−Tin
Tape & Reel (Note 7)
T: Tape & Reel
2: 2,000 / Reel
All packages are RoHS−compliant (Lead−free, Halogen−free).
The standard plated finish is NiPdAu.
The device used in the above example is a CAT4103V−GT2 (SOIC, NiPdAu, Tape & Reel, 2,000/Reel).
For additional temperature options, please contact your nearest ON Semiconductor Sales office.
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
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CAT4103/D
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