MX29LV002C-002NC T-B, 3V, 2Mb, v2.0.pdf

MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• Byte mode only:
- 262,411 x8 (MX29LV002C/002NC)
- 524,288 x8 (MX29LV004C)
- 1,048,576 x8 (MX29LV008C)
• Sector Structure
- 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x 1
64K-Byte x 3 (MX29LV002C), 64K-Byte x 7 (MX29LV004C), 64K-Byte x 15 (MX29LV008C)
• Sector Protect
- Provides sector protect function to prevent program or erase operation in the protected sector
- Provides chip unprotect function to allow code changing
- Provides temporary sector unprotect function for code changing in previously protected sector
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 250mA from -1V to Vcc + 1V
• Low Vcc write inhibit : Vcc ≤ 1.4V
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
PERFORMANCE
• High Performance
- Fast access time: 45Q (MX29LV004C only), 55Q (for MX29LV004C and MX29LV008C), 70/90ns
- Fast program time: 9us/Byte typical utilizing accelerate function
- Fast erase time: 0.7s/sector
• Low Power Consumption
- Low active read current: 7mA (typical) at 5MHz
- Low standby current: 200nA (typical)
• Minimum 100,000 erase/program cycle
• 20 years data retention
SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being
erased
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI) only for 29LV002C/002NC, 29LV004C
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output only for 29LV004C, 29LV008C
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
PACKAGE
• 32-Pin TSOP (for MX29LV002C/002NC)
• 32-Pin PLCC (for MX29LV002C/002NC and MX29LV004C)
• 40-Pin TSOP (for MX29LV004C and MX29LV008C), which is not recommended for new design in
• All devices are RoHS Compliant
P/N:PM1301
REV. 2.0, DEC. 15, 2011
1
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV002C/002NC PIN CONFIGURATIONS
32 TSOP (TYPE 1)
A11
A9
A8
A13
A14
A17
WE#
VCC
RESET#
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MX29LV002C/002NC T/B
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
NC on MX29LV002NC
32 PLCC
PIN DESCRIPTION
32
30
29
A14
A6
A13
A5
A8
A4
A9
A3
9
A2
MX29LV002C/
002NC T/B
25
A10
CE#
Q5
Q4
Q3
VSS
PIN NAME
Address Input
Data Input/Output
Chip Enable Input
Write Enable Input
Hardware Reset Pin/Sector Protect
Unlock
Output Enable Input
Power Supply Pin (+3V)
Ground Pin
Q7
Q6
21
20
17
Q2
Q1
OE#
VCC
GND
OE#
A0
13
14
RESET#
A11
A1
Q0
SYMBOL
A0~A17
Q0~Q7
CE#
WE#
A17
1
WE#
A16
4
VCC
5
RESET#
A7
A15
A12
NC on MX29LV002NC
P/N:PM1301
REV. 2.0, DEC. 15, 2011
2
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV004C PIN CONFIGURATIONS
40 TSOP (Standard Type) (10mm x 20mm)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
MX29LV004C T/B
32 PLCC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
NC
NC
A10
Q7
Q6
Q5
Q4
VCC
VCC
NC
Q3
Q2
Q1
Q0
OE#
VSS
CE#
A0
32
30
29
A14
A6
A13
A5
A8
A4
A3
RESET#
A9
9
MX29LV004C T/B
25
A11
A2
OE#
A1
A10
A0
OE#
RY/BY#
VCC
GND
CE#
21
20
Q5
Q4
Q3
Q2
GND
17
Q7
PIN NAME
Address Input
Data Input/Output
Chip Enable Input
Write Enable Input
Hardware Reset Pin/Sector Protect Unlock (for 40-TSOP)
Output Enable Input
Ready/Busy# Output (for 40-TSOP)
Power Supply Pin (2.7V~3.6V)
Ground Pin
Q6
13
14
Q1
Q0
SYMBOL
A0~A18
Q0~Q7
CE#
WE#
A17
1
WE#
A16
4
VCC
5
A18
A7
A15
A12
PIN DESCRIPTION
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REV. 2.0, DEC. 15, 2011
3
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV008C PIN CONFIGURATIONS
40 TSOP (Standard Type) (10mm x 20mm)
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MX29LV008CT/CB
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
NC
A19
A10
Q7
Q6
Q5
Q4
VCC
VCC
NC
Q3
Q2
Q1
Q0
OE#
GND
CE#
A0
PIN DESCRIPTION
SYMBOL
A0~A19
Q0~Q7
CE#
WE#
RESET#
OE#
RY/BY#
VCC
GND
PIN NAME
Address Input
Data Input/Output
Chip Enable Input
Write Enable Input
Hardware Reset Pin
Output Enable Input
Ready/Busy Output
Power Supply Pin (2.7V~3.6V)
Ground Pin
P/N:PM1301
REV. 2.0, DEC. 15, 2011
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MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
BLOCK DIAGRAM
CE#
OE#
WE#
RESET#
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
STATE
HIGH VOLTAGE
MACHINE
(WSM)
LATCH
BUFFER
Y-DECODER
AND
STATE
X-DECODER
ADDRESS
A0-AM
WRITE
FLASH
REGISTER
ARRAY
ARRAY
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
AM: MSB address
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REV. 2.0, DEC. 15, 2011
5
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Table 1. BLOCK STRUCTURE
MX29LV002CT SECTOR ARCHITECTURE
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
Sector Size
Byte Mode
64Kbytes
64Kbytes
64Kbytes
32Kbytes
8Kbytes
8Kbytes
16Kbytes
Address range
Byte Mode (x8)
00000-0FFFF
10000-1FFFF
20000-2FFFF
30000-37FFF
38000-39FFF
3A000-3BFFF
3C000-3FFFF
A17
0
0
1
1
1
1
1
A16
0
1
0
1
1
1
1
Sector Address
A15
A14
X
X
X
X
X
X
0
X
1
0
1
0
1
1
A13
X
X
X
X
0
1
X
A17
0
0
0
0
0
1
1
A16
0
0
0
0
1
0
1
Sector Address
A15
A14
0
0
0
1
0
1
1
X
X
X
X
X
X
X
A13
X
0
1
X
X
X
X
MX29LV002CB SECTOR ARCHITECTURE
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
Sector Size
Byte Mode
16Kbytes
8Kbytes
8Kbytes
32Kbytes
64Kbytes
64Kbytes
64Kbytes
Address range
Byte Mode (x8)
00000-03FFF
04000-05FFF
06000-07FFF
08000-0FFFF
10000-1FFFF
20000-2FFFF
30000-3FFFF
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REV. 2.0, DEC. 15, 2011
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MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV004CT SECTOR ARCHITECTURE
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
Sector Size
Byte Mode
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
32Kbytes
8Kbytes
8Kbytes
16Kbytes
Address range
Byte Mode (x8)
00000-0FFFF
10000-1FFFF
20000-2FFFF
30000-3FFFF
40000-4FFFF
50000-5FFFF
60000-6FFFF
70000-77FFF
78000-79FFF
7A000-7BFFF
7C000-7FFFF
A18
0
0
0
0
1
1
1
1
1
1
1
A17
0
0
1
1
0
0
1
1
1
1
1
Sector Address
A16
A15
A14
0
X
X
1
X
X
0
X
X
1
X
X
0
X
X
1
X
X
0
X
X
1
0
X
1
1
0
1
1
0
1
1
1
A13
X
X
X
X
X
X
X
X
0
1
X
A17
0
0
0
0
0
1
1
0
0
1
1
Sector Address
A16
A15
A14
0
0
0
0
0
1
0
0
1
0
1
X
1
X
X
0
X
X
1
X
X
0
X
X
1
X
X
0
X
X
1
X
X
A13
X
0
1
X
X
X
X
X
X
X
X
MX29LV004CB SECTOR ARCHITECTURE
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
Sector Size
Byte Mode
16Kbytes
8Kbytes
8Kbytes
32Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
Address range
Byte Mode (x8)
00000-03FFF
04000-05FFF
06000-07FFF
08000-0FFFF
10000-1FFFF
20000-2FFFF
30000-3FFFF
40000-4FFFF
50000-5FFFF
60000-6FFFF
70000-7FFFF
P/N:PM1301
A18
0
0
0
0
0
0
0
1
1
1
1
REV. 2.0, DEC. 15, 2011
7
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV008CT SECTOR ARCHITECTURE
Sector
Sector Size
Address range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
32Kbytes
8Kbytes
8Kbytes
16kbytes
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
80000h-8FFFFh
90000h-9FFFFh
A0000h-AFFFFh
B0000h-BFFFFh
C0000h-CFFFFh
D0000h-DFFFFh
E0000h-EFFFFh
F0000h-F7FFFh
F8000h-F9FFFh
FA000h-FBFFFh
FC000h-FFFFFh
A19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
P/N:PM1301
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
Sector Address
A17
A16
A15
0
0
X
0
1
X
1
0
X
1
1
X
0
0
X
0
1
X
1
0
X
1
1
X
0
0
X
0
1
X
1
0
X
1
1
X
0
0
X
0
1
X
1
0
X
1
1
0
1
1
1
1
1
1
1
1
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
REV. 2.0, DEC. 15, 2011
8
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV008CB SECTOR ARCHITECTURE
Sector
Sector Size
Address range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
16Kbytes
8Kbytes
8Kbytes
32Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64kbytes
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
80000h-8FFFFh
90000h-9FFFFh
A0000h-AFFFFh
B0000h-BFFFFh
C0000h-CFFFFh
D0000h-DFFFFh
E0000h-EFFFFh
F0000h-FFFFFh
A19
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
P/N:PM1301
A18
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Sector Address
A17
A16
A15
0
0
0
0
0
0
0
0
0
0
0
1
0
1
X
1
0
X
1
1
X
0
0
X
0
1
X
1
0
X
1
1
X
0
0
X
0
1
X
1
0
X
1
1
X
0
0
X
0
1
X
1
0
X
1
1
X
A14
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A13
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
REV. 2.0, DEC. 15, 2011
9
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Table 2. BUS OPERATION--1
Mode Select
RESET#
CE#
WE#
OE#
Address
Q0~Q7
Device Reset
L
X
X
X
X
HighZ
Standby Mode
Vcc±0.3V
Vcc±0.3V
X
X
X
HighZ
Output Disable
H
L
H
H
X
HighZ
Read Mode
H
L
H
L
AIN
DOUT
Write
H
L
L
H
AIN
DIN
Temporary Sector
Unprotect
Vhv
X
X
X
AIN
DIN
Sector Protect
Vhv
L
L
H
Sector Address,
A6=L, A1=H, A0=L
DIN
Chip Unprotect
Vhv
L
L
H
Sector Address,
A6=H, A1=H, A0=L
DIN
Note:
1. Q0~Q7 are input (DIN) or output (DOUT) pins according to the requests of command sequence, sector protection, or data polling algorithm.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
10
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
BUS OPERATION--2
Item
Control Input
AM
to
CE# WE# OE#
A13
A12
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
Q0~Q7
Sector Protect
Verification
L
H
L
SA
x
Vhv
x
L
x
H
L
01h or 00h (Note1)
Read Silicon ID
Manufacturer Code
L
H
L
x
x
Vhv
x
L
x
L
L
C2H
Read Silicon ID
MX29LV002CT
L
H
L
x
x
Vhv
x
L
x
L
H
59H
Read Silicon ID
MX29LV002CB
L
H
L
x
x
Vhv
x
L
x
L
H
5AH
Read Silicon ID
MX29LV004CT
L
H
L
x
x
Vhv
x
L
x
L
H
B5H
Read Silicon ID
MX29LV004CB
L
H
L
x
x
Vhv
x
L
x
L
H
B6H
Read Silicon ID
MX29LV008CT
L
H
L
x
x
Vhv
x
L
x
L
H
3EH
Read Silicon ID
MX29LV008CB
L
H
L
x
x
Vhv
x
L
x
L
H
37H
Notes:
1. Sector unprotected code:00h. Sector protected code:01h.
2. AM: MSB of address.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
11
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
WRITE COMMANDS/COMMAND SEQUENCES
To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle,
all address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising
edge of CE# and WE#.
Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets
of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid
command will bring the device to an undefined state.
REQUIREMENTS FOR READING ARRAY DATA
Read array action is to read the data stored in the array. While the memory device is in powered up or has been
reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in
array, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address
of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being
read out will be displayed on output pin for microprocessor to access. If CE# or OE# is Vih, the output will be in
tri-state, and there will be no data displayed on output pin at all.
After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to the status of read array, and the device can read the data in any address in the array. In the process of
erasing, if the device receives the Erase suspend command, erase operation will be stopped temporarily after a
period of time no more than Tready1 and the device will return to the status of read array. At this time, the device
can read the data stored in any address except the sector being erased in the array. In the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. Similarly, if program command is issued after erase suspend, after program operation is completed, system
can still read array data in any address except the sectors to be erased
The device needs to issue reset command to enable read array operation again in order to arbitrarily read the
data in the array in the following two situations: 1. In program or erase operation, the programming or erasing failure causes Q5 to go high.
2. The device is in auto select mode or CFI mode.
In the two situations above, if reset command is not issued, the device is not in read array mode and system
must issue reset command before reading array data.
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REV. 2.0, DEC. 15, 2011
12
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
RESET# OPERATION
Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in
program or erase operation, the reset operation will take at most a period of Tready1 for the device to return to
read array mode. Before the device returns to read array mode, the RY/BY# pin remains low (busy status).
When RESET# pin is held at GND±0.3V, the device consumes standby current(Isb).However, device draws larger current if RESET# pin is held at Vil but not within GND±0.3V.
It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memory will be reset during system reset and allows system to read boot code from flash memory.
SECTOR PROTECT OPERATION
When a sector is protected, program or erase operation will be disabled on that protected sector. MX29LV002C/
MX29LV004C/MX29LV008C T/B provides two methods for sector protection.
Once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected
by asserting RESET# pin at Vhv. Refer to temporary sector unprotect operation for further details.
The first method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for the
algorithm for this method.
The other method is asserting Vhv on A9 and OE# pins, with A6 and CE# at Vil. The protection operation begins
at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details.
CHIP UNPROTECT OPERATION
MX29LV002C/MX29LV004C/MX29LV008C T/B provides two methods for chip unprotect. The chip unprotect
operation unprotects all sectors within the device. It is recommended to protect all sectors before activating chip
unprotect mode. All sector are unprotected when shipped from the factory.
The first method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for algorithm of the operation.
The other method is asserting Vhv on A9 and OE# pins, with A6 at Vih and CE# at Vil (see Table 2). The unprotect operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details.
TEMPORARY SECTOR UNPROTECT OPERATION
System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously
protected sectors can be programmed or erased just as it is unprotected. The devices returns to normal operation once Vhv is removed from RESET# pin and previously protected sectors are again protected.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
13
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
AUTOMATIC SELECT OPERATION
When the device is in Read array mode, erase-suspended read array mode or CFI mode, user can issue read
silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several
silicon IDs continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. In read silicon ID mode, issuing
reset command will reset device back to read array mode or erase-suspended read array mode.
Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE#, A6 and A1 at Vil. While
the high voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read
array mode or erase-suspended read array mode. When A0 is Low, device will output Macronix Manufacture ID
C2. When A0 is high, device will output Device ID.
VERIFY SECTOR PROTECT STATUS OPERATION
MX29LV002C/MX29LV004C/MX29LV008C T/B provides hardware sector protection against Program and Erase
operation for protected sectors. The sector protect status can be read through Sector Protect Verify command.
This method requires Vhv on A9 pin, Vih on WE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector address on A13 to AM pins. If the read out data is 01H, the designated sector is protected. Oppositely, if the read
out data is 00H, the designated sector is not protected.
DATA PROTECTION
To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode
during power up. Besides, only after successful completion of the specified command sets will the device begin
its erase or program operation.
Other features to protect the data from accidental alternation are described as followed.
LOW VCC WRITE INHIBIT
The device refuses to accept any write command when Vcc is less than 1.4V. This prevents data from spuriously
altered. The device automatically resets itself when Vcc is lower than 1.4V and write cycles are ignored until Vcc
is greater than 1.4V. System must provide proper signals on control pins after Vcc is larger than 1.4V to avoid
unintentional program or erase operation
WRITE PULSE "GLITCH" PROTECTION
CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write
cycle.
LOGICAL INHIBIT
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at
Vih, WE# a Vih, or OE# at Vil.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
14
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
POWER-UP SEQUENCE
Upon power up, MX29LV002C/MX29LV004C/MX29LV008C T/B is placed in read array mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences.
POWER-UP WRITE INHIBIT
When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on
the rising edge of WE#.
POWER SUPPLY DECOUPLING
A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
15
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
TABLE 3. MX29LV002C/MX29LV004C/MX29LV008C T/B COMMAND DEFINITIONS
Command
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus Cycle
4th Bus
Cycle
5th Bus Cycle
6th Bus Cycle
Read Mode
Addr
Data
Addr
Data
Addr
Data
Addr
Data
C2
ID
00/01
Addr
Data
Addr
Data
Command
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus Cycle
4th Bus
Cycle
5th Bus Cycle
6th Bus Cycle
Addr
Data
Automatic Select
Reset Mode Manufacturer
Sector Protect
Device ID
ID
Verify
XXX
555
555
555
F0
AA
AA
AA
2AA
2AA
2AA
55
55
55
555
555
555
90
90
90
(Sector)
X00
X01
X02
Chip Erase
555
AA
2AA
55
555
A0
555
AA
2AA
55
555
80
Addr
555
Data
AA
2AA
55
555
10
Sector Erase
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Program
555
AA
2AA
55
555
80
555
AA
2AA
55
Sector
30
Erase
Suspend
XXX
B0
Erase
Resume
XXX
30
Sector Protect CFI (Note 4)
XXX
60
sector
60
sector
40
sector
00/01
55
98
Notes:
1.Device ID :
29LV002C: 59H/5AH (Top/Bottom)
29LV004C: B5H/B6H (Top/Bottom)
29LV008C: 3EH/37H (Top/Bottom)
2. For sector protect verify result, 00H means sector is not protected, 01H means sector has been protected.
3. Sector Protect command is valid during Vhv at RESET# pin, Vih at A1 pin and Vil at A0, A6 pins. The last Bus
cyc is for protect verify.
4.For MX29LV002C/002NC and MX29LV004C.
5. It is not allowed to adopt any other code which is not in the above command definition table.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
16
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
RESET
In the following situations, executing reset command will reset device back to read array mode:
• Among erase command sequence (before the full command set is completed)
• Sector erase time-out period
• Erase fail (while Q5 is high)
• Among program command sequence (before the full command set is completed, erase-suspended program
included)
• Program fail (while Q5 is high, and erase-suspended program fail is included)
• Read silicon ID mode
• Sector protect verify
• CFI mode
While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset
device back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode,
user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command.
AUTOMATIC SELECT COMMAND SEQUENCE
Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not a sector is
protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by
a specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of
times without entering another command sequence. The reset command is necessary to exit the Automatic Select mode and back to read array. The following table shows the identification code with corresponding address.
Address
Data (Hex)
Manufacturer ID
X00
C2
Device ID
X01
ID
Top/Bottom Boot Sector
(Sector address) X 02
00/01
Unprotected/protected
Sector Protect Verify
Representation
There is an alternative method to that shown in Table 2, which is intended for EPROM programmers and requires
Vhv on address bit A9.
Notes:
Device ID : MX29LV002CT: 59, MX29LV002CB: 5A
MX29LV004CT: B5, MX29LV004CB: B6
MX29LV008CT: 3E, MX29LV008CB: 37
P/N:PM1301
REV. 2.0, DEC. 15, 2011
17
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
AUTOMATIC PROGRAMMING
The MX29LV002C/MX29LV004C/MX29LV008C T/B can provide the user program function by the form of ByteMode or Word-Mode. As long as the users enter the right cycle defined in the Table.3 (including 2 unlock cycles
and A0H), any data user inputs will automatically be programmed into the array.
Once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse,
verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse
if any of the cells does not pass verification. Meanwhile, the internal control will prohibit the programming to cells
that pass verification while the other cells fail in verification in order to avoid over-programming. With the internal
write state controller, the device requires the user to write the program command and data only.
Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status
from "0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is
not successfully programmed to "0".
Any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready1. When the embedded program algorithm
is complete or the program operation is terminated by hardware reset, the device will return to the reading array
data mode.
When the embedded program operation is on going, user can confirm if the embedded operation is finished or
not by the following methods:
Status
In progress*1
Finished
Exceed time limit
Q7
Q7#
Q7
Q7#
Q6
Toggling
Stop toggling
Toggling
Q5
0
0
1
RY/BY#*2
0
1
0
*1: The status "in progress" means both program mode and erase-suspended program mode.
*2: RY/BY# is an open drain output pin and should be weakly connected to Vcc through a pull-up resistor.
*3: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues
to toggle for about 1us or less and the device returns to read array state without programing the data in the protected sector.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
18
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
CHIP ERASE
Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first
two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles,
and the sixth cycle is the chip erase operation.
During chip erasing, all the commands will not be accepted except hardware reset or the working voltage is too
low that chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array.
When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or
not by the following methods:
Status
Q7
Q6
Q5
Q2
RY/BY#
In progress
0
Toggling
0
Toggling
0
Finished
1
Stop toggling
0
1
1
Exceed time limit
0
Toggling
1
Toggling
0
SECTOR ERASE
Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to issue. The first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also
"unlock cycles" and the sixth cycle is the sector erase command. After the sector erase command sequence is
issued, there is a time-out period of 50us counted internally. During the time-out period, additional sector address and sector erase command can be written multiply. Once user enters another sector erase command, the
time-out period of 50us is recounted. If user enters any command other than sector eras or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. The
number of sectors could be from one sector to all sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation begins.
During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user
can check the status as chip erase.
When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not
by the following methods:
Status
Time-out period
In progress
Finished
Q7
0
0
1
Q6
Toggling
Toggling
Stop toggling
Q5
0
0
0
Q3
0
1
1
Q2
Toggling
Toggling
1
RY/BY#*2
0
0
1
Exceed time limit
0
Toggling
1
1
Toggling
0
*1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible
to another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is valid.
*2: RY/BY# is open drain output pin and should be weakly connected to Vcc through a pull-up resistor.
*3: When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to
toggle for 100us or less and the device returned to read array status without erasing the data in the protected
sector.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
19
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
SECTOR ERASE SUSPEND
During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command
in the time-out period of sector erasure, device time-out period will be over immediately and the device will go
back to erase-suspended read array mode. If user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the Tready1 (<=20uS) suspend finishes
and the device will enter erase-suspended read array mode. User can judge if the device has finished erase suspend through Q6, Q7, and RY/BY#.
After device has entered erase-suspended read array mode, user can read other sectors not at erase suspend
by the speed of Taa; while reading the sector in erase-suspend mode, device will output its status. User can use
Q6 and Q2 to judge the sector is erasing or the erase is suspended.
Status
Erase suspend read in erase suspended sector
Erase suspend read in non-erase suspended sector
Erase suspend program in non-erase suspended sector
Q7
1
Data
Q7#
Q6
No toggle
Data
Toggle
Q5
0
Data
0
Q3
N/A
Data
N/A
Q2
RY/BY#
Toggle
1
Data
1
N/A
0
When the device has suspended erasing, user can execute the command sets except sector erase and chip
erase, such as read silicon ID, sector protect verify, program, CFI query and erase resume.
SECTOR ERASE RESUME
Sector erase resume command is valid only when the device is in erase suspend state. After erase resume, user
can issue another erase suspend command, but there should be a 400uS interval between erase resume and
the next erase suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the
time for erasing will increase.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
20
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE
MX29LV002C/MX29LV004C T/B features CFI mode. Host system can retrieve the operating characteristics,
structure and vendor-specified information such as identifying information, memory size, byte/word configuration,
operating voltages and timing information of this device by CFI mode. If the system writes the CFI Query command "98h", to address "55h"/"AAh" (depending on Word/Byte mode), the device will enter the CFI Query Mode,
any time the device is ready to read array data. The system can read CFI information at the addresses given in
Table 4.
Once user enters CFI query mode, user can not issue any other commands except reset command. The reset
command is required to exit CFI mode and go back to the mode before entering CFI. The system can write the
CFI Query command only when the device is in read mode, erase suspend, standby mode or automatic select
mode.
Table 4-1. CFI mode: Identification Data Values (MX29LV002C/002NC and 004C only)
(All values in these tables are in hexadecimal)
Description
Query-unique ASCII string "QRY"
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code
Address for alternate algorithm extended query table
Address (h)
10
11
12
13
14
15
16
17
18
19
1A
Data (h)
0051
0052
0059
0002
0000
0040
0000
0000
0000
0000
0000
Address (h)
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
Data (h)
0027
0036
0000
0000
0004
0000
000A
0000
0005
0000
0004
0000
Table 4-2. CFI Mode: System Interface Data Values
Description
Vcc supply minimum program/erase voltage
Vcc supply maximum program/erase voltage
VPP supply minimum program/erase voltage
VPP supply maximum program/erase voltage
Typical timeout per single word/byte write, 2n us
Typical timeout for maximum-size buffer write, 2n us
Typical timeout per individual block erase, 2n ms
Typical timeout for full chip erase, 2n ms
Maximum timeout for word/byte write, 2n times typical
Maximum timeout for buffer write, 2n times typical
Maximum timeout per individual block erase, 2n times typical
Maximum timeout for chip erase, 2n times typical
P/N:PM1301
REV. 2.0, DEC. 15, 2011
21
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Table 4-3. CFI Mode: Device Geometry Data Values
Description
n
Device size = 2 in number of bytes (MX29LV002C)
Device size = 2n in number of bytes (MX29LV004C)
Flash device interface description
Maximum number of bytes in buffer write = 2n (not support)
Number of erase regions within device
Index for Erase Bank Area 1
[2E,2D] = # of same-size sectors in region 1-1
[30, 2F] = sector size in multiples of 256-bytes
Index for Erase Bank Area 2
Index for Erase Bank Area 3
Index for Erase Bank Area 4 (for MX29LV002C)
Index for Erase Bank Area 4 (for MX29LV004C)
P/N:PM1301
Address (h)
27
27
28
29
2A
2B
2C
Data (h)
0012
0013
0000
0000
0000
0000
0004
2D
0000
2E
0000
2F
0040
30
0000
31
32
33
34
35
36
37
38
39
39
3A
3B
3C
0001
0000
0020
0000
0000
0000
0080
0000
0002
0006
0000
0000
0001
REV. 2.0, DEC. 15, 2011
22
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Description
Query - Primary extended table, unique ASCII string, PRI
Major version number, ASCII
Minor version number, ASCII
Unlock recognizes address (0= recognize, 1= don't recognize)
Erase suspend (2= to both read and program)
Sector protect (N= # of sectors/group)
Temporary sector unprotect (1=supported)
Sector protect/Chip unprotect scheme
Simultaneous R/W operation (0=not supported)
Burst mode (0=not supported)
Page mode (0=not supported)
P/N:PM1301
Address (h)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
Data (h)
0050
0052
0049
0031
0030
0000
0002
0001
0001
0004
0000
0000
0000
REV. 2.0, DEC. 15, 2011
23
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
ABSOLUTE MAXIMUM STRESS RATINGS
-65oC to +125oC
-65oC to +150oC
Surrounding Temperature with Bias
Storage Temperature
Voltage Range
VCC
-0.5V to +4.0 V
RESET#, A9 and OE#
-0.5V to +12.5V
The other pins
Output Short Circuit Current (less than one second)
-0.5V to Vcc +0.5V
200 mA
OPERATING TEMPERATURE AND VOLTAGE
Commercial (C) Grade
Surrounding Temperature (TA )
0°C to +70°C
Industrial (I) Grade
Surrounding Temperature (TA )
-40°C to +85°C
VCC Supply Voltages
Full Vcc Range
Regulated Vcc Voltage Range
+3.0 V to 3.6 V
P/N:PM1301
+2.7 V to 3.6 V
REV. 2.0, DEC. 15, 2011
24
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
DC CHARACTERISTICS
Symbol
Iilk
Iilk9
Iolk
Icr1
Icr2
Description
Input Leak
A9 Leak
Output Leak
Read Current (5MHz)
Read Current (1MHz)
Min.
Typ.
7mA
2mA
Max.
± 1.0uA
35uA
± 1.0uA
12mA
4mA
Icw
Write Current
15mA
30mA
Isb
Standby Current
0.2uA
5uA
Isbr
Reset Current
0.2uA
5uA
Isbs
Vil
Vih
Sleep Mode Current
Input Low Voltage
Input High Voltage
Very High Voltage for hardware Protect/
Unprotect/Auto Select/Temporary
Unprotect
Output Low Voltage
Ouput High Voltage
Ouput High Voltage
0.2uA
5uA
0.8V
Vcc+0.3V
Vhv
Vol
Voh1
Voh2
-0.5V
0.7xVcc
11.5V
0.85xVcc
Vcc-0.4V
P/N:PM1301
Remark
A9=12.5V
CE#=Vil, OE#=Vih
CE#=Vil, OE#=Vih
CE#=Vil, OE#=Vih,
WE#=Vil
Vcc=Vcc max,
other pin disable
Vcc=Vccmax,
RESET# enable,
other pin disable
12.5V
0.45V
Iol=4.0mA
Ioh1=-2mA
Ioh2=-100uA
REV. 2.0, DEC. 15, 2011
25
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
SWITCHING TEST CIRCUITS
Vcc
0.1uF
R2
TESTED DEVICE
CL
R1
+3.3V
DIODES=IN3064
OR EQUIVALENT
R1=6.2K ohm
R2=2.7K ohm
Test Condition
Output Load : 1 TTL gate
Output Load Capacitance,CL : 30pF(45Q/55Q/70ns)/100pF(90ns)
Rise/Fall Times : 5ns
In/Out reference levels :1.5V
SWITCHING TEST WAVEFORMS
3.0V
1.5V
1.5V
Test Points
0.0V
INPUT
OUTPUT
P/N:PM1301
REV. 2.0, DEC. 15, 2011
26
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
AC CHARACTERISTICS
MX29LV002C/002NC
Symbol
Taa
Tce
Toe
Tdf
Description
Valid data output after address
Valid data output after CE# low
Valid data output after OE# low
Data output floating after OE# high or CE# high
Output hold time from the earliest rising edge of address,
Toh
CE#, OE#
Trc
Read period time
Twc
Write period time
Tcwc Command write period time
Tas
Address setup time
Tah
Address hold time
Tds
Data setup time
Tdh
Data hold time
Tvcs
Vcc setup time
Tcs
Chip enable Setup time
Tch
Chip enable hold time
Toes
Output enable setup time
Read
Toeh Output enable hold time
Toggle & Data#
Polling
Tws
WE# setup time
Twh
WE# hold time
Tcep
CE# pulse width
Tceph CE# pulse width high
Twp
WE# pulse width
Twph WE# pulse width high
Tbusy Program/Erase active time by RY/BY#
Tghwl Read recover time before write
Tghel Read recover time before write (CE# Control)
Twhwh1 Byte Program operation
Twhwh2 Sector Erase Operation
Tbal
Sector Add hold time
P/N:PM1301
Min.
Typ.
Max.
70/90
70/90
30/35
25/30
Unit
ns
ns
ns
ns
0
ns
70/90
70/90
70/90
0
45
35/45
0
50
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
10
ns
0
0
35
30
35
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
sec
us
0
0
90
9
0.7
300
8
50
REV. 2.0, DEC. 15, 2011
27
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV004C (Restricated Vcc=3.0V~3.6V for 45R/55R)
Symbol
Taa
Tce
Toe
Tdf
Description
Min.
Valid data output after address
Valid data output after CE# low
Valid data output after OE# low
Data output floating after OE# high or CE# high
Output hold time from the earliest rising edge of address,
Toh
0
CE#, OE#
Trc
Read period time
45/55/70/90
Twc
Write period time
70/90
Tcwc Command write period time
70/90
Tas
Address setup time
0
Tah
Address hold time
45
Tds
Data setup time
35/45
Tdh
Data hold time
0
Tvcs
Vcc setup time
50
Tcs
Chip enable Setup time
0
Tch
Chip enable hold time
0
Toes
Output enable setup time
0
Read
0
Toeh Output enable hold time
Toggle & Data#
10
Polling
Tws
WE# setup time
0
Twh
WE# hold time
0
Tcep
CE# pulse width
35
Tceph CE# pulse width high
30
Twp
WE# pulse width
35
Twph WE# pulse width high
30
Tbusy Program/Erase active time by RY/BY#
Tghwl Read recover time before write
0
Tghel Read recover time before write (CE# Control)
0
Twhwh1 Byte Program operation
Twhwh2 Sector Erase Operation
Tbal
Sector Add hold time
Typ.
Max.
45/55/70/90
45/55/70/90
30/30/30/35
25/25/25/30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
90
9
0.7
300
8
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
sec
us
Notes: Only 40-TSOP provide RY/BY# pin.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
28
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV008C (Restricated Vcc=3.0V~3.6V for 55R)
Symbol
Taa
Tce
Toe
Tdf
Description
Valid data output after address
Valid data output after CE# low
Valid data output after OE# low
Data output floating after OE# high or CE# high
Output hold time from the earliest rising edge of address,
Toh
CE#, OE#
Trc
Read period time
Twc
Write period time
Tcwc Command write period time
Tas
Address setup time
Tah
Address hold time
Tds
Data setup time
Tdh
Data hold time
Tvcs
Vcc setup time
Tcs
Chip enable Setup time
Tch
Chip enable hold time
Toes
Output enable setup time
Read
Toeh Output enable hold time
Toggle & Data#
Polling
Tws
WE# setup time
Twh
WE# hold time
Tcep
CE# pulse width
Tceph CE# pulse width high
Twp
WE# pulse width
Twph WE# pulse width high
Tbusy Program/Erase active time by RY/BY#
Tghwl Read recover time before write
Tghel Read recover time before write (CE# Control)
Twhwh1 Byte Program operation
Twhwh2 Sector Erase Operation
Tbal
Sector Add hold time
P/N:PM1301
Min.
Typ.
Max.
55/70/90
55/70/90
30/30/35
25/25/30
Unit
ns
ns
ns
ns
0
ns
55/70/90
70/90
70/90
0
45
35/45
0
50
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
10
ns
0
0
35
30
35
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
sec
us
0
0
90
9
0.7
300
8
50
REV. 2.0, DEC. 15, 2011
29
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 1. COMMAND WRITE OPERATION
Tcwc
CE#
Vih
Vil
Tcs
WE#
Tch
Vih
Vil
Toes
OE#
Twph
Twp
Vih
Vil
Addresses
Vih
VA
Vil
Tah
Tas
Tdh
Tds
Data
Vih
Vil
DIN
VA: Valid Address
P/N:PM1301
REV. 2.0, DEC. 15, 2011
30
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
READ/RESET OPERATION
Figure 2. READ TIMING WAVEFORMS
CE#
Tce
Vih
Vil
Vih
WE#
OE#
Vil
Toeh
Tdf
Toe
Vih
Vil
Toh
Taa
Trc
Vih
Addresses
Outputs
ADD Valid
Vil
Voh
HIGH Z
DATA Valid
HIGH Z
Vol
P/N:PM1301
REV. 2.0, DEC. 15, 2011
31
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
AC CHARACTERISTICS
Item
Trp1
Trp2
Trh
Trb1
Trb2
Description
RESET# Pulse Width (During Automatic Algorithms)
RESET# Pulse Width (NOT During Automatic Algorithms)
RESET# High Time Before Read
RY/BY# Recovery Time (to CE#, OE# go low)
RY/BY# Recovery Time (to WE# go low)
RESET# PIN Low (During Automatic Algorithms) to Read or
Tready1
Write Algorithms) to Read or Write
Tready2 RESET# PIN Low (NOT During Automatic
Setup
MIN
MIN
MIN
MIN
MIN
Speed
500
500
50
0
50
Unit
ns
ns
ns
ns
ns
MAX
20
us
MAX
500
ns
Figure 3. RESET# TIMING WAVEFORM
Trb1
CE#, OE#
Trb2
WE#
Tready1
RY/BY#
RESET#
Trp1
Reset Timing during Automatic Algorithms
CE#, OE#
Trh
RY/BY#
RESET#
Trp2
Tready2
Reset Timing NOT during Automatic Algorithms
P/N:PM1301
REV. 2.0, DEC. 15, 2011
32
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
ERASE/PROGRAM OPERATION
Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM
CE#
Tch
Twp
WE#
Twph
Tcs
Tghwl
OE#
Last 2 Erase Command Cycle
Twc
Address
2AAh
VA
SA
Tds
Data
Read Status
Tah
Tas
Tdh
55h
VA
In
Progress Complete
10h
Tbusy
Trb
RY/BY#
SA: 555h for chip erase
P/N:PM1301
REV. 2.0, DEC. 15, 2011
33
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Data# Polling Algorithm or
Toggle Bit Algorithm
NO
Data=FFh ?
YES
Auto Chip Erase Completed
P/N:PM1301
REV. 2.0, DEC. 15, 2011
34
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Read Status
CE#
Tch
Twhwh2
Twp
WE#
Twph
Tcs
Tghwl
OE#
Tbal
Last 2 Erase Command Cycle
Twc
Address
Tas
Sector
Address 0
2AAh
Tds
Data
Tdh
55h
Sector
Address 1
Sector
Address n
Tah
VA
VA
In
Progress Complete
30h
30h
Tbusy
30h
Trb
RY/BY#
P/N:PM1301
REV. 2.0, DEC. 15, 2011
35
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
Last Sector
to Erase
NO
YES
Data# Polling Algorithm or
Toggle Bit Algorithm
Data=FFh
NO
YES
Auto Sector Erase Completed
P/N:PM1301
REV. 2.0, DEC. 15, 2011
36
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
NO
Toggle Bit checking Q6
ERASE SUSPEND
not toggled
YES
Read Array or
Program
Reading or
Programming End
NO
YES
Write Data 30H
ERASE RESUME
Continue Erase
Another
Erase Suspend ?
NO
YES
P/N:PM1301
REV. 2.0, DEC. 15, 2011
37
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS
CE#
Tch
Twhwh1
Twp
WE#
Tcs
Twph
Tghwl
OE#
Last 2 Program Command Cycle
Address
555h
VA
PA
Tds
Data
Last 2 Read Status Cycle
Tah
Tas
VA
Tdh
A0h
Status
PD
Tbusy
DOUT
Trb
RY/BY#
P/N:PM1301
REV. 2.0, DEC. 15, 2011
38
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 10. CE# CONTROLLED WRITE TIMING WAVEFORM
WE#
Twhwh1 or Twhwh2
Tcep
CE#
Tceph
Tghwl
OE#
Tah
Tas
Address
555h
Tds
Data
VA
PA
VA
Tdh
A0h
Status
PD
DOUT
Tbusy
RY/BY#
P/N:PM1301
REV. 2.0, DEC. 15, 2011
39
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 11. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Data# Polling Algorithm or
Toggle Bit Algorithm
next address
Read Again Data:
Program Data?
No
YES
No
Last Word to be
Programed
YES
Auto Program Completed
P/N:PM1301
REV. 2.0, DEC. 15, 2011
40
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
SECTOR PROTECT/CHIP UNPROTECT
Figure 12. Sector Protect/Chip Unprotect Waveform (RESET# Control)
150us: Sector Protect
15ms: Chip Unprotect
1us
CE#
WE#
OE#
Verification
Data
60h
SA, A6
A1, A0
60h
40h
VA
VA
Status
VA
Vhv
RESET#
Vih
VA: valid address
P/N:PM1301
REV. 2.0, DEC. 15, 2011
41
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 13-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect Mode
No
First CMD=60h?
Yes
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 60h
Wait 150us
Reset
PLSCNT=1
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 40h
Retry Count +1
Read at Sector Address
with [A6,A1,A0]:[0,1,0]
No
Retry Count=25?
No
Data=01h?
Yes
Yes
Device fail
Protect another
sector?
Yes
No
Temporary Unprotect Mode
RESET#=Vih
Write RESET CMD
Sector Protect Done
P/N:PM1301
REV. 2.0, DEC. 15, 2011
42
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 13-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect
No
First CMD=60h?
Yes
All sectors
protected?
No
Protect All Sectors
Yes
Write [A6,A1,A0]:[1,1,0]
data: 60h
Wait 15ms
Write [A6,A1,A0]:[1,1,0]
data: 40h
Retry Count +1
Read [A6,A1,A0]:[1,1,0]
No
Retry Count=1000?
No
Data=00h?
Yes
Device fail
Yes
Temporary Unprotect
Write reset CMD
Chip Unprotect Done
P/N:PM1301
REV. 2.0, DEC. 15, 2011
43
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 14. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control)
CE#
Twpp1
WE#
Toesp
12V
3V
Verify
OE#
Tvlht
Tvlht
A1
A6
12V
3V
A9
AM-A13
Tvlht
Sector Address
Data
01H
F0H
Toe
Notes:
Tvlht (Voltage transition time)=4us min.
Twpp1 (Write pulse width for sector protect)=100ns min, 10us(Typ.)
Twpp2 (Write pulse width for chip unprotected)=100ns min, 12ms(Typ.)
Toesp (OE# setup time to WE# active)=4us min.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
44
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 15. SECTOR PROTECTION ALGORITHM (A9, OE# Control)
START
Write Sector Addr
Retry Count=0
OE#=Vhv, A9=Vhv, CE#=Vil
A6=Vil
Activate WE# Pulse
Time Out 150us
Retry Count+1
WE#=Vih, CE#=OE#=Vil
A9=Vhv
Read at Sector Address
with A1=1
No
PLSCNT=32?
.
No
Data=01H?
Yes
Device Failed
Protect Another
Sector?
Yes
Remove Vhv from A9
Write Reset Command
Sector Protect
Done
P/N:PM1301
REV. 2.0, DEC. 15, 2011
45
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 16. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control)
CE#
Twpp2
WE#
Toesp
Verify
12V
VCC
OE#
Tvlht
Tvlht
A1
12V
VCC
A9
Tvlht
A6
AM-A13
Sector Address
Data
00H
F0H
Toe
Notes:
Tvlht (Voltage transition time)=4us min.
Twpp1 (Write pulse width for sector protect)=100ns min, 10us(Typ.)
Twpp2 (Write pulse width for chip unprotected)=100ns min, 12ms(Typ.)
Toesp (OE# setup time to WE# active)=4us min.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
46
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 17. CHIP UNPROTECTION ALGORITHM (A9, OE# Control)
START
Protect All Sectors
Retry Count=0
OE#=A9=Vhv
CE#=Vil, A6=Vih
Activate WE# Pulse
Time Out 50ms
Retry Count +1
Sector Protect Verify from
first sector with CE#=OE#=vil,
A9=Vhv, A1=1
No
Data=00H?
go to next sector
No
Yes
No
All sectors have
been verified?
PLSCNT=1000?
Yes
Device Failed
Yes
Remove Vhv from A9
Write Reset Command
Chip Unprotect
Done
* Before chip unprotect, all sectors should be protected.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
47
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Table 5. TEMPORARY SECTOR UNPROTECT
Parameter
Alt
Description
Condition
Speed
Unit
Trpvhh
Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET#
MIN
500
ns
Tvhhwl
Trsp RESET# Vhv to WE# Low
MIN
4
us
Figure 18. TEMPORARY SECTOR UNPROTECT WAVEFORMS
Program or Erase Command Sequence
CE#
WE#
Tvhhwl
RY/BY#
Vhv
12V
RESET#
0 or Vih
Vil or Vih
Trpvhh
Trpvhh
P/N:PM1301
REV. 2.0, DEC. 15, 2011
48
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 19. TEMPORARY SECTOR UNPROTECT FLOWCHART
Start
Apply Reset# pin Vhv Volt
Enter Program or Erase Mode
Mode Operation Completed
(1) Remove Vhv Volt from Reset#
(2) RESET# = Vih
Completed Temporary Sector
Unprotected Mode
Notes:
1. Temporary unprotect all protected sectors Vhv=11.5~12.5V.
2. The protected conditions of the protected sectors are the same to temporary sector unprotect mode.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
49
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 20. SILICON ID READ TIMING WAVEFORM
CE#
Vih
Vil
Tce
Vih
WE#
Vil
Toe
Vih
OE#
Tdf
Vil
Toh
Toh
Vhv
Vih
A9
A0
Vil
Vih
Vil
Taa
A1
Taa
Vih
Vil
ADD
DATA
Q0-Q7
Vih
Vil
Vih
Vil
DATA OUT
DATA OUT
C2H
Device ID
Notes:
Device ID : MX29LV002CT: 59, MX29LV002CB: 5A
MX29LV004CT: B5, MX29LV004CB: B6
MX29LV008CT: 3E, MX29LV008CB: 37
P/N:PM1301
REV. 2.0, DEC. 15, 2011
50
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
WRITE OPERATION STATUS
Figure 21. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
CE#
Tch
WE#
Toe
OE#
Toeh
Tdf
Trc
Address
VA
VA
Taa
Toh
Q7
Complement
Complement
True
Valid Data
Q0-Q6
Status Data
Status Data
True
Valid Data
High Z
High Z
Tbusy
RY/BY#
P/N:PM1301
REV. 2.0, DEC. 15, 2011
51
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 22. Data# Polling Algorithm
Start
Read Q7~Q0 at valid address
(Note 1)
Q7 = Data# ?
No
Yes
No
Q5 = 1 ?
Yes
Read Q7~Q0 at valid address
Q7 = Data# ?
(Note 2)
No
Yes
FAIL
Pass
Notes:
1. For programming, valid address means program address.
For erasing, valid address means erase sectors address.
2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
52
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 23. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
CE#
Tch
WE#
Toe
OE#
Toeh
Tdf
Trc
Address
VA
VA
VA
VA
Taa
Toh
Q6/Q2
Valid Status
(first read)
Valid Status
Valid Data
(second read)
(stops toggling)
Valid Data
Tbusy
RY/BY#
VA : Valid Address
P/N:PM1301
REV. 2.0, DEC. 15, 2011
53
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 24. Toggle Bit Algorithm
Start
Read Q7-Q0 Twice
(Note 1)
NO
Q6 Toggle ?
YES
NO
Q5 = 1?
YES
Read Q7~Q0 Twice
NO
Q6 Toggle ?
YES
PGM/ERS fail
Write Reset CMD
PGM/ERS Complete
Notes:
1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
P/N:PM1301
REV. 2.0, DEC. 15, 2011
54
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device powerup. If the timing in the figure is ignored, the device may not operate correctly.
Vcc
Vcc(min)
GND
Tvr
Tvcs
Tf
CE#
WE#
Tce
Vil
Vih
Vil
Tf
OE#
WP#/ACC
Tr
Vil
Vih
Taa
Tr or Tf
Valid
Address
Vil
Voh
DATA
Toe
Vih
Tr or Tf
ADDRESS
Tr
Vih
High Z
Valid
Ouput
Vol
Vih
Vil
Figure A. AC Timing at Device Power-Up
Symbol
Tvr
Tr
Tf
Parameter
Vcc Rise Time
Input Signal Rise Time
Input Signal Fall Time
Min.
20
Max.
500000
20
20
Unit
us/V
us/V
us/V
Note: Not tested 100%.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
55
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Chip Erase Time
Sector Erase Time
Erase/Program Cycles
Chip Programming Time
Byte Programming Time
Min.
MX29LV002C
MX29LV004C
MX29LV008C
100,000
MX29LV002C
MX29LV004C
MX29LV008C
Limits
Typ.
2.5
4
8
0.7
Max.
16
32
32
8
3.0
4.5
9
9
7
13.5
27
300
Units
sec
sec
sec
sec
Cycles
sec
sec
sec
us
DATA RETENTION
Parameter
Condition
Min.
Data retention
55˚C
20
Max.
Unit
years
LATCH-UP CHARACTERISTICS
Min.
-1.0V
-1.0V
-100mA
Input Voltage voltage difference with GND on all pins except I/O pins
Input Voltage voltage difference with GND on all I/O pins
Vcc Current
All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing
Max.
12.5V
Vcc + 1.0V
+100mA
PIN CAPACITANCE
Parameter Symbol
CIN2
COUT
CIN
Parameter Description
Control Pin Capacitance
Output Capacitance
Input Capacitance
Test Set
VIN=0
VOUT=0
VIN=0
P/N:PM1301
Typ.
Max.
12
12
8
Unit
pF
pF
pF
REV. 2.0, DEC. 15, 2011
56
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
ORDERING INFORMATION
MX29LV002C
MX29LV002CTTC-70G
Access
Time (ns)
70
MX29LV002CTTC-90G
90
30
5
32 Pin TSOP
MX29LV002CBTC-70G
70
30
5
32 Pin TSOP
MX29LV002CBTC-90G
90
30
5
32 Pin TSOP
MX29LV002CTTI-70G
70
30
5
32 Pin TSOP
MX29LV002CTTI-90G
90
30
5
32 Pin TSOP
MX29LV002CBTI-70G
70
30
5
32 Pin TSOP
MX29LV002CBTI-90G
90
30
5
32 Pin TSOP
MX29LV002CTQC-70G
70
30
5
32 Pin PLCC
MX29LV002CTQC-90G
90
30
5
32 Pin PLCC
MX29LV002CBQC-70G
70
30
5
32 Pin PLCC
MX29LV002CBQC-90G
90
30
5
32 Pin PLCC
MX29LV002CTQI-70G
70
30
5
32 Pin PLCC
MX29LV002CTQI-90G
90
30
5
32 Pin PLCC
MX29LV002CBQI-70G
70
30
5
32 Pin PLCC
MX29LV002CBQI-90G
90
30
5
32 Pin PLCC
PART NO.
Operating Current Standby Current
MAX. (mA)
MAX. (uA)
30
5
P/N:PM1301
PACKAGE
Remark
32 Pin TSOP
REV. 2.0, DEC. 15, 2011
57
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV002NC
MX29LV002NCTTC-70G
Access
Time (ns)
70
MX29LV002NCTTC-90G
90
30
5
32 Pin TSOP
MX29LV002NCBTC-70G
70
30
5
32 Pin TSOP
MX29LV002NCBTC-90G
90
30
5
32 Pin TSOP
MX29LV002NCTTI-70G
70
30
5
32 Pin TSOP
MX29LV002NCTTI-90G
90
30
5
32 Pin TSOP
MX29LV002NCBTI-70G
70
30
5
32 Pin TSOP
MX29LV002NCBTI-90G
90
30
5
32 Pin TSOP
MX29LV002NCTQC-70G
70
30
5
32 Pin PLCC
MX29LV002NCTQC-90G
90
30
5
32 Pin PLCC
MX29LV002NCBQC-70G
70
30
5
32 Pin PLCC
MX29LV002NCBQC-90G
90
30
5
32 Pin PLCC
MX29LV002NCTQI-70G
70
30
5
32 Pin PLCC
MX29LV002NCTQI-90G
90
30
5
32 Pin PLCC
MX29LV002NCBQI-70G
70
30
5
32 Pin PLCC
MX29LV002NCBQI-90G
90
30
5
32 Pin PLCC
PART NO.
Operating Current Standby Current
MAX. (mA)
MAX. (uA)
30
5
P/N:PM1301
PACKAGE
Remark
32 Pin TSOP
REV. 2.0, DEC. 15, 2011
58
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV004C
MX29LV004CTTC-55Q
Access
Time (ns)
55
MX29LV004CBTC-55Q
55
30
5
40 Pin TSOP
MX29LV004CTTC-70G
70
30
5
40 Pin TSOP
MX29LV004CBTC-70G
70
30
5
40 Pin TSOP
MX29LV004CTTC-90G
90
30
5
40 Pin TSOP
MX29LV004CBTC-90G
90
30
5
40 Pin TSOP
MX29LV004CTTI-55Q
55
30
5
40 Pin TSOP
MX29LV004CBTI-55Q
55
30
5
40 Pin TSOP
MX29LV004CTTI-70G
70
30
5
40 Pin TSOP
MX29LV004CBTI-70G
70
30
5
40 Pin TSOP
MX29LV004CTTI-90G
90
30
5
40 Pin TSOP
MX29LV004CBTI-90G
90
30
5
40 Pin TSOP
MX29LV004CTQC-55Q
55
30
5
32 Pin PLCC
MX29LV004CBQC-55Q
55
30
5
32 Pin PLCC
MX29LV004CTQC-70G
70
30
5
32 Pin PLCC
MX29LV004CBQC-70G
70
30
5
32 Pin PLCC
MX29LV004CTQC-90G
90
30
5
32 Pin PLCC
MX29LV004CBQC-90G
90
30
5
32 Pin PLCC
MX29LV004CTQI-55Q
55
30
5
32 Pin PLCC
MX29LV004CBQI-55Q
55
30
5
32 Pin PLCC
MX29LV004CTQI-70G
70
30
5
32 Pin PLCC
MX29LV004CBQI-70G
70
30
5
32 Pin PLCC
MX29LV004CTQI-90G
90
30
5
32 Pin PLCC
MX29LV004CBQI-90G
90
30
5
32 Pin PLCC
MX29LV004CTTI-45Q
45
30
5
40 Pin TSOP
MX29LV004CBTI-45Q
45
30
5
40 Pin TSOP
PART NO.
Operating Current Standby Current
MAX. (mA)
MAX. (uA)
30
5
PACKAGE
Remark
40 Pin TSOP
* 40-TSOP is not recommended for new design in.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
59
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV008C
PART NO.
MX29LV008CTTC-55Q
MX29LV008CTTC-70G
MX29LV008CTTC-90G
MX29LV008CBTC-55Q
MX29LV008CBTC-70G
MX29LV008CBTC-90G
MX29LV008CTTI-55Q
MX29LV008CTTI-70G
MX29LV008CTTI-90G
MX29LV008CBTI-55Q
MX29LV008CBTI-70G
MX29LV008CBTI-90G
Access
Time (ns)
55
70
90
55
70
90
55
70
90
55
70
90
Operating Current Standby Current
MAX. (mA)
MAX. (uA)
30
5
30
5
30
5
30
5
30
5
30
5
30
5
30
5
30
5
30
5
30
5
30
5
PACKAGE
Remark
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
40 Pin TSOP
* 40-TSOP is not recommended for new design in.
P/N:PM1301
REV. 2.0, DEC. 15, 2011
60
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
PART NAME DESCRIPTION
MX 29
LV 002 C T T C
70 G
OPTION:
G: RoHS compliant package
Q: Restricted Vcc (3.0V~3.6V) with RoHS compliant package
SPEED:
45: 45ns
55: 55ns
70: 70ns
90: 90ns
TEMPERATURE RANGE:
C: Commercial (0° C to 70° C)
I: Industrial (-40° C to 85° C)
PACKAGE:
Q: PLCC
T: TSOP
BOOT BLOCK TYPE:
T: Top Boot
B: Bottom Boot
REVISION:
C
DENSITY & MODE:
002/002N: 2Mb, x8 Boot Block
004: 4Mb, x8 Boot Block
008: 8Mb, x8 Boot Block
TYPE:
LV: 3V
DEVICE:
29:Flash
P/N:PM1301
REV. 2.0, DEC. 15, 2011
61
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
PACKAGE INFORMATION
P/N:PM1301
REV. 2.0, DEC. 15, 2011
62
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
P/N:PM1301
REV. 2.0, DEC. 15, 2011
63
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
P/N:PM1301
REV. 2.0, DEC. 15, 2011
64
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
REVISION HISTORY
Revision No. Description
1.1
1. Corrected wrong CFI address data
1.2
1. Added statement 1.3
1. Correct typo
1.4
1. Revised statement
1.5
1. Added note 5 into table 3. Command Definitions
1.6
1. Modified Figure 10. CE# Controlled Write Timing Waveform
1.7
1. Modified Erase and Programming Performance table
2. 40-TSOP is not recommended for new design in
3. Revised Twc, Tcwc, Tds timing spec
4. Removed non Pb-free part no.
1.8
1. Modified wrong sector architecture of MX29LV002CT
1.9
1. Added data retention table
2. Changed data retention from 10-years to 20-years
3. Modified the sector erase time max from 15s to 8s
2.0
1. Modified description for RoHS compliance
2. Added note
P/N:PM1301
Page
Date
P21~23
AUG/25/2006
P67
NOV/06/2006
P16,18,19, DEC/12/2007
P42,52
P21
DEC/28/2007
P16
JAN/17/2008
P39
FEB/21/2008
P56
JUL/31/2008
P1,59,60
P28
P57~61
P6
OCT/21/2008
P56
JUL/06/2009
P1
P27~29,56
P1,61
DEC/15/2011
P55
REV. 2.0, DEC. 15, 2011
65
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Except for customized products which has been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2004~2011. All rights reserved.
Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, NBiit, Macronix NBit, eLiteFlash,
XtraROM, Phines, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE are trademarks or registered
trademarks of Macronix International Co., Ltd. The names and brands of other companies are for identification
purposes only and may be claimed as the property of the respective companies.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
66