ATAN0144 ATA8520D Reference Design APPLICATION NOTE Features • • • • • • Reference design for SIGFOX application with ATA8520 transmitter or ATA8520D transceiver device Compatible with uplink only or uplink/downlink operation In compliance with SIGFOX certification, i.e., class levels regarding TX output power and RX sensitivity In compliance with CE/ETSI certification Compatible with discreet solutions and solutions with front-end modules (FEM) Includes schematic, layout and BOM Description This application note describes the reference design to develop and complete a PCB layout for a system using the ATA8520 transmitter (uplink only) [1] or ATA8520D transceiver (uplink/downlink) [2]. The recommended design is used in the SIGFOX- and CE-certified ATA8520-EK1-E evaluation kit. In the development of a PCB, various requirements must be taken into account: • • • SIGFOX certification [3] ETSI/CE certification [4] BOM-optimized system design In addition to the above requirements, the following specifications must be considered: • • • • • SIGFOX classification for uplink operation, i.e., range definition Selection of operating mode, i.e., uplink only or uplink and downlink operation Current consumption and power supply, i.e., battery operation Antenna selection, i.e., antenna gain and size BOM cost Atmel-9407A-ATAN0144_Application Note-11/2015 Table of Contents Features.......................................................................................................................... 1 Description.......................................................................................................................1 1. Block Diagram of the ATAB0101A-Rev3.1 PCB........................................................ 3 2. RF Design..................................................................................................................6 3. Digital Design...........................................................................................................12 4. Digital and RF Layout.............................................................................................. 13 5. End-Of-Line Testing................................................................................................. 18 6. References.............................................................................................................. 19 Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 2 Block Diagram of the ATAB0101A-Rev3.1 PCB The ATA8520-EK1-E evaluation kit and the ATA8520-EK2-E/-EK3-E extension boards use the same PCB ATAB0101A-Rev3.x with a different bill of material (BOM). Figure 1-1 shows the block diagram of the PCB ATAB0101A-V3.1 for the ATA8520-EK1-E kit with the schematic and layout referenced in [5]. The PCB ATAB0101A-Rev3.2 for the ATA8520-EK2-E kit and ATAB0101A-Rev3.3 for the ATA8520-EK3E kit are not shown, but use the same RF front end with a different digital section. Figure 1-1 Block Diagram of ATA8520-EK1-E Kit for Uplink and Downlink Operation ATAB0101A-Rev3.1 PCB TWI bus Host MCU ATmega328P 32.768kHz Temperature sensor AT30TS75A power event reset power-on SPI bus RF Transceiver ATA8520D 24.305MHz power 3V supply direction 1. TX SAW 868.3MHz RX SAW 869.5MHz LNA ~10dB BFR360F RF Switch BGS12AL7-4 SMA 50Ω Antenna The PCB includes the following functional blocks: 1. 2. 3. 4. Host MCU The Host MCU is an ATmega328P MCU for the ATA8520-EK1-E and ATA8520-EK2-E kit, and a SAM (Cortex-M) device for the ATA8520-EK3-E. The host MCU runs the target application and controls the ATA8520D RF transceiver and AT30TS75A temperature sensor. For the ATA8520-EK2E and -EK3-E extension boards the MCU is located on the development kit attached to the board and must be ordered separately. RF transceiver The ATA8520D RF transceiver operates as an RF modem device, including the SIGFOX protocol stack, firmware and RF transmit and receive functions. If only the transmit function is required, the ATA8520 device can be used instead. The devices ATA8520 and ATA8520D are pin-to-pin compatible. Temperature sensor The AT30TS75A is a temperature sensor with a digital TWI interface (I2C compatible). The supply power for the sensor is controlled by the host MCU. RX SAW filter Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 3 5. 6. 7. The RX SAW filter is recommended for receive operation and has an RF blocking function for outof-band RF signals. The RF RX frequency range is 869.525MHz +-96kHz as defined by SIGFOX. TX SAW filter The TX SAW filter is recommended for suppressing spurious out-of-band emissions, i.e., 2nd and 3rd harmonics of the RF TX frequency 868.13MHz ±96kHz. This filter must be capable of supporting RF power levels up to 15dBm. LNA The RF LNA is required to achieve the final RX sensitivity level of −126dBm as defined by SIGFOX. The ATA8520D transceiver has a typical RX sensitivity level of −121dBm and the LNA must additionally compensate for RX SAW filter loss. This results in a total gain of ~10dB. The LNA is switched ON/OFF by the RF transceiver. RF switch The RF switch selects the RX or TX signal to be routed to the external antenna. The direction is controlled by the RF transceiver. An external switch of the transceiver is used instead of its internal switch to facilitate the PCB layout and avoid any instabilities and spurious emissions due to crosstalk in combination with the TX SAW filter. If the downlink (receive) operation is not required, the design can be simplified as shown in Figure 1-2. Figure 1-2 Block Diagram for ATA8520-EK1-E Kit for Uplink Only Operation ATAB0101A-Rev3.1 PCB TWI bus Host MCU ATmega328P 32.768kHz Temperature sensor AT30TS75A power event reset power-on SPI bus RF Transmitter ATA8520 24.305MHz 3V supply TX SAW 868.3MHz SMA 50Ω Antenna In this application, the RX path with LNA and RX SAW is removed together with the external RF switch. The key parameters for these applications are listed in Table 1-1. Table 1-1 Key Parameters for Figure 1-1 and Figure 1-2 Parameters Uplink/Downlink (Figure 1-1) TX frequency TX RF power conducted at 25°C, 868.13MHz Uplink Only (Figure 1-2) 868.13MHz ±96kHz ~10dBm ~11dBm Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 4 Parameters Uplink/Downlink (Figure 1-1) TX SAW filter Uplink Only (Figure 1-2) 868.3MHz Pass band: 868.0MHz to 868.6MHz Attenuation: ~3dB Max. source power: 15dBm at 50Ω RX frequency 869.525MHz ±96kHz -- RX sensitivity conducted at 25°C, 869.525MHz −126dBm -- RX SAW filter 869.6MHz -- Pass band: 868.6MHz to 870.6MHz Attenuation: ~3dB Max. source power: 10dBm at 50Ω LNA Frequency range: 800MHz to 900MHz -- Gain: ~10dB Noise figure: 2dB RF switch Frequency range: 800MHz to 900MHz -- Attenuation: ~0.5dB The above mentioned power levels are for typical environment conditions and power supply values: • At 24-25°C environmental temperature • For 3.0V supply voltage in 3V supply mode (see data sheets [1] and [2]) • Including crystal offset calibration at 868.13MHz and 24-25°C (see application notes [11] and [12]). Any changes in the above conditions will have an impact on the output power levels (see data sheets [1] and [2]) and the spurious emission which is also related to the antenna characteristics chosen for the final system. Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 5 2. RF Design RF design is a critical aspect of PCB development because it requires correct 50Ω matching of the RF transceiver and SAW filters. Atmel recommends following the application notes and datasheets for the: • • • RF transmitter [1] or transceiver [2] device (summarized in the following section) TX and RX SAW filter [6], [7] LNA [8] Figure 2-1 shows the RF section of the schematic for the ATAB0101A-Rev3.x PCB. All parts not mounted are indicated and the 50Ω matching tracks are highlighted in bold. The RF section includes the following main components: • U2 － ATA8520 RF transmitter or ATA8520D RF transceiver device • XTAL1 － 24.305MHz crystal for ATA8520/ATA8520D device (see [9]) • SAW2 － B3744 TX SAW filter The following is also required for downlink operation with the ATA8520D: • Q2 － BSS84 power switch transistor for LNA • Q3 － BFR360F LNA RF transistor • SAW1 － TA1457A RX SAW filter • U9 － BGS12AS7-4 RF antenna switch Figure 2-1 lists information about some critical RF components used in this design which are used and tested with the PCB ATAB0101A-V3.1. Table 2-1 RF Components Component Value XTAL1 24.305MHz Part no. / Manufacturer KDS: DSX321G, 1C324305AB0B NDK: NX3225SA, EXS00A-CS08559 NX2016SA, EXS00A-CS08560 SAW1 869.6MHz TaiSaw: TA1457A ~ 3dBi insertion loss SAW2 868.3MHz TDK/EPCOS: B3744 ~ 3dBi insertion loss 15dBm source power U9 – RF Switch 800 to 900MHz Infineon: BGS12AS7-4 ~ 0.4dBi insertion loss Q3 - LNA 800 to 900MHz Infineon: BFR360F >10dB gain < 2dB noise figure at 3V supply C RF components Murata, Kemet, TDK ±0.25pF or ±5% Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 6 Component Value Part no. / Manufacturer L RF components Murata, Taiyo Yuden, Coilcraft, Abracon, Johanson Technology ±2% or ±5% L2 Choke Murata Figure 2-1 RF Section for Up- and Downlink Operation 3.3V 2 Q2 RPB7 1 BSS84LT1G 3 L2 BLM15HG102SN1D 3.3V BR13 0Ω C30 RF_PWRON GND RF 1 50ohms GND GND 2 3 GND 100nF GND 47pF R24 47kΩ C28 50ohms Controlled Impedance 7 4 5 CTRL C33 L9 8.2nH L8 18nH R6 0Ω 100nF R26 36Ω GND C1 100pF C32 47kΩ C31 47pF BR12 0Ω XAnt1 LTT-SASF56GT R28 10Ω R27 6 VDD GND RF1 RFIN GND CTRL RF2 50ohms 3 2 C29 1 Q3 BFR360F 220pF GND 5.6pF GND GND U9 BGS12AL7-4 GND RF_EVENT RF_PWRON L3 18nH RPB7 RF_EVENT RF_NSS 28 27 GND MISO 0.068µF 3.3V 25 26 PB4 PB5 PB6 PB3 MOSI 23 SCK 22 RPB0 21 RPB0 GND C21 20 19 RPC5 18 RPC4 17 RPC3 GND 22nF PC2 2 30 PC3 C24 1 PB7 31 PC4 VS_PA NC 5.6pF RF_OUT 9 1pF 8 PC5 24 16 BR9 2.7nH C6 DVCC SPDT_TX PC1 L10 50ohms C9b DGND 15 7 NC PC0 6 U2 ATA8520D SPDT_ANT VS 5 PB0 14 4 SPDT_RX AVCC 0Ω 0Ω L3b 18nH CTRL 3.3V PB1 13 BR11 PB2 RFIN 12 3 BR10 NC XTAL2 2 11 1 0Ω XTAL1 0Ω 1 AGND GND BR7 BR6 NC 12nH NC 32 GND 3 3.3V 2 29 GND L1 6 GND IN GND R25 10kΩ RF_Transmitter SAW2 B3744 10 OUT GND GND 2.2pF GND RF_NSS 1pF 4 C27 GND GND C25 1pF 5 27nH 1 TA1457A GND 50ohms C9 GND L7 2 IN/OUT OUT/IN 6 2.2pF 3 GND GND 5 27nH C27 GND SAW1 4 L6 50ohms GND RPC2 BR9: insert jumper for 3V supply only! RPC1 RF_NRES 3.3V XTAL1 1 3 24.305MHz 2 GND C23 C22 220nF 2.2µF GND GND C7 100pF GND If uplink only operation is required the ATA8520 or ATA8520D can be used with the SAW2 filter implemented for TX operation. The antenna switch U9 can be replaced with a 0Ω resistor between pin1 and pin5 of the switch footprint and the pins 1, 2, 3, 4 and 6 of the device U2 have to be connected to GND. Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 7 Figure 2-2 RF Section for Uplink only Operation XAnt1 LTT-SASF56GT 1 RF 50ohms C1 100pF GND GND 50ohms R6 0Ω 2 3 50ohms RF_NSS C9 RF_EVENT RF_PWRON 1pF 5.6pF 2 3.3V 25 PB3 PB4 RF_NSS 27 26 RF_EVENT 28 PB5 RPB7 29 PB6 30 PC4 VS_PA PC3 C24 1 PB7 31 RF_OUT 0.068µF MOSI 23 SCK 22 RPB0 21 RPB0 GND C21 20 19 RPC5 18 RPC4 17 RPC3 GND 22nF PC2 1pF 8 PC5 NC C6 DVCC SPDT_TX 9 C9b DGND PC1 BR9 2.7nH NC 24 16 L10 50ohms U2 ATA8520D SPDT_ANT PC0 7 PB0 15 6 SPDT_RX 14 5 L3b 18nH PB1 VS 4 PB2 RFIN AVCC 3 GND MISO NC 12 2 XTAL2 1 1 AGND 32 GND NC NC 3 11 2 6 GND IN GND GND XTAL1 GND SAW2 B3744 10 OUT 4 GND 5 R25 10kΩ RF-Transmitter 13 L3 18nH GND RPC2 BR9: insert jumper for 3V supply only! RPC1 RF_NRES 3.3V XTAL1 1 3 24.305MHz 2 GND C23 C22 220nF 2.2µF GND GND C7 100pF GND For the connection to the host MCU the following signals have to be used as shown in Figure 2-3: • • • • SPI connections: – PB3 / MISO data signal – PB2 / MOSI data signal – PB1 / SCK clock signal – PB5 / NSS chip select signal PB6 / Event signal IRQ PC1 or PC2 or PC3 or PC4 or PC5 / NPWRONx wake-up signal or PB4 / PWRON wake-up signal PC0 / NRESET chip reset signal (optional) For the device wake-up only one signal is necessary while the NPWRONx signals have to be connected to GND for wake-up and the PWRON signal has to be connected to VDD for wake-up. If PWRON is not used it has to be connected to GND. If the NPWRONx signals are not used they can be left open as they have an internal pull-up resistor. The reset signal PC0 / NRESET can be used but is not required to reset the device. The device has a power-up reset and a SPI command for the reset operation. The pin PC0 has an internal pull-up resistor and can be left open if not used. Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 8 Figure 2-3 Connections to Host MCU IRQ NSS MISO PB3 PB4 PB5 PB6 PB7 Atmel ATA8520D SPDT_ANT DGND DVCC NC 24 21 20 PC4 18 VS_PA PC3 17 11 12 13 14 15 Microcontroller C5 PC2 PC5 RF_OUT 10 SCK 22 SPDT_TX 9 MOSI 23 19 NC 8 PB0 PC1 7 25 PB1 PC0 6 26 SPDT_RX VS 5 27 RF_IN AVCC 4 28 PB2 XTAL2 3 NC XTAL1 2 29 AGND NC 1 30 NC 31 32 16 Wake/Monitor Q1 C3 C4 VS = 5V VDD To save a pin connection there is an alternative way to connect the host MCU as shown in Figure 2-4. The wake-up pin PB4 / PWRON can be used together with the chip-select signal NSS to wake-up the device and the NPWRONx signals are not used. This requires that the signal NSS has to be kept at low level when performing the SPI command “OFF mode” (0x05) to keep the device in OFF mode. When pulling the signal NSS high the device will wake-up and stay wake-up until performing a reset or an “OFF mode” command. Figure 2-4 Alternative Connections to Host MCU IRQ NSS MISO SPDT_ANT PB3 PB5 PB6 PB7 PB4 DGND DVCC NC 24 21 20 RF_OUT PC4 18 VS_PA PC3 17 Q1 11 12 C3 13 14 15 Microcontroller C5 PC2 19 10 SCK 22 PC5 9 MOSI 23 SPDT_TX NC 8 25 PB0 Atmel ATA8520D PC1 7 SPDT_RX PC0 6 26 PB1 VS 5 27 RF_IN AVCC 4 28 PB2 XTAL2 3 NC XTAL1 2 29 AGND NC 1 30 NC 31 32 16 C4 VS = 5V VDD The following guidelines must be considered for RF design: Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 9 ATA8520 and ATA8520D (U2) Guidelines: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. The decoupling capacitor of AVCC, C23 must be placed as close to pin 12 as possible because otherwise the series inductance would be too high and supply bypassing no longer effective at high frequencies. The decoupling capacitor of DVCC, C21 must be placed as close to pin 20 as possible. This decoupling capacitor should be connected directly to the DGND pin and ground layer using vias. Otherwise the sensitivity of the receiver or the spurious performance of the transmitter may suffer due to spurious clock emission by the integrated AVR. The decoupling capacitor of VS_PA, C24 must be placed as close to pin 8 as possible because otherwise the series inductance would be too high and the power amplifier might not work correctly. An extra capacitor placed close to pin 8 (VS_PA) and another capacitor close to pin 13 (VS) is thus necessary even in a 3V application. The decoupling capacitor of VS, C22 must be placed as close to pin 13 as possible because otherwise the series inductance would be too high and supply bypassing no longer effective at high frequencies. Direct connection of the DGND pin to the exposed die pad must be avoided and at least four vias placed under the exposed die pad. Failure to do this causes isolation of the integrated AVR from RF front end to be worse. The exposed die pad is also the RF ground for receive and transmit operation. Reduced sensitivity or lower output power may result from bad ground connection on the exposed die pad. The crystal must be placed as close to the IC as possible to avoid extra capacitance on XTAL1 and XTAL2. It is advisable to design the lines carrying the RF signal to be as short as possible and place the elements of the matching networks as close to the IC as possible. Pin 5 must remain open. Avoid routing XTAL, AVCC and VS lines in parallel and close to each other over long distances; doing so reduces the coupling of the XTO signals to the supply voltage. Failure to do so may cause spurious receiver or transmitter emissions. Avoid routing XTAL1 and XTAL2 lines in parallel and close to each other over long distances so that the XTO oscillation margin is not reduced. Pin 1 should be connected to GND. If the internal SPDT switch is not used, connect pins 3, 4 and 6 to GND. The internal SPDT switch is controlled by the ATA8520D firmware and used to select the antenna direction with the U9 external switch. To facilitate this, SPDT_RX pin 3 and SPDT_TX pin 6 are connected to the logical level required for the RF switch control pin 6, which is connected to the SPDT_ANT pin 4 of the transceiver. PB7 pin 29 controls LNA power switch during receive operation. SAW Filter Guidelines: 1. 2. 3. The TX SAW filter SAW2 should be selected to operate at up to 15dBm of source power and with 50Ω matching elements. The RX SAW filter SAW1 should be used with 50Ω matching elements. The typical insertion loss of an SAW filter is ~3dB. LNA Guidelines: 1. 2. The LNA is placed between the antenna and SAW filter. The required gain is ~10dB with a noise figure of ~2dB. Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 10 3. 4. Typical current consumption is ~5mA at 3V supply. An L2 choke is used for suppressing noise from the supply voltage. RF Switch Guidelines: 1. 2. The RF switch is used for 50Ω RF signals. The supply voltage can be derived from PB0 pin 22, which controls the power for a front-end module (FEM). It can alternatively be connected directly to a 3V supply due to the low current consumption (as shown in Figure 2-1), or the RF_PWRON signal applied for switching on the RF device can be used. 3. The direction is controlled by the internal SPDT switch (as shown in Figure 2-1) or by using the PB7 pin 29 of the transceiver. Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 11 Digital Design The MCU and sensor-related blocks are designed as specified in their datasheet and following the guidelines given there."The maximum clock frequency is ~8MHz, which is not critical for the design and layout. Figure 3-1 shows the digital section of the schematic for the ATAB0101A-Rev3.1 PCB and includes the following main components: • U1 － ATmega328P MCU (alternative ATmega168PA or ATmega88PA can also be used instead as they are pin-to-pin compatible) • XTAL2 － 32.768kHz crystal to operate at low power, i.e., for internal timer 2 operation • U3 － AT30TS75A temperature sensor with a TWI (I2C) digital interface • Q1 － BSS84 sensor power switch transistor • LD1 － Sensor power LED (green) • LD2 － General purpose LED (red) • SW1 － General purpose button All other sensor components on the PCB are not mounted, but the footprint is provided for future enhancements. The MCU I/Os are also available on connector pins for prototyping. The power supply attached to connector X1 should be 2.9V to 3.1V, in compliance with the transmitter/transceiver supply and sensor supply. The max. MCU clock for 3V supply is ~10MHz (see [10]). Figure 3-1 Digital Section PC1 23 PC0 2 C5 100pF GND 21 A1 GND A2 20 19 3.3V 100nF LD1 2 1 GND SML-310MTT86N C11 R2 LED 100nF GND GND 5 1kΩ C12 17 100nF 6 3Vsens 18 GND 7 AT30TS75 GND SCK PB4 (MISO) ALERT R1 LD2 2 1 GND 1kΩ GND SML-LX0603SRW-TR BTN SW1 R4 1 3 300Ω 2 4 GND 16 3.3V 3Vsens 3 R3 10kΩ XISP1 ext. Power A0 C64 8 SKRAALE010 X1 1 SCL 22 MCU ISP 3.3V 4 VCC MISO 15 MOSI 14 LED 9 32.768kHz RF_NSS GND PB3 (MOSI/OC2A) (SCK) PB5 PB2 (OC1B/SS) PB6 (TOSC2/XTAL2) XTAL2 3 R62 10kΩ SDA 3.3V MISO 1 2 SCK 3 4 MCU_NRES 5 6 MOSI GND GND Q1 BSS84LT1G SNS_PWR PC3 SDA SCL MCU NRES PD0 RF EVENT PC2 25 (ADC2) PC2 (ADC3) PC3 26 27 (SDA/ADC4) PC4 28 (SCL/ADC5) PC5 29 30 (RXD) PD0 (RESET) PC6 31 32 ADC6 AVCC PB1 (OC1A) 100nF AREF PB6 (TOSC1/XTAL1) 10 C13 GND21 VCC6 PD5 (T1/OC0A) 8 GND5 13 7 RF_NRES 6 U1 ATmega328P-MU VCC4 BTN GND 3.3V ADC7 GND3 24 3Vsens U3 SDA 1 GND (ADC0) PC0 PB0 (ICP1/CLKO) 5 3Vsens (ADC1) PC1 PD7 (AIN1) 4 R61 10kΩ SCL 2 PD4 (T0/XCK) 11 3 T-Sensor 3Vsens PD3 (INT1/OC2B) RPB0 2 RF_PWRON 12 1 PD4 PD6 (AIN0/OC0A) SNS_PWR (TXD) PD1 (INT0) PD2 33 GND PD1 ATAB0101A-V3.1 (Standalone Kit): GND PAD 3. 2 3.3V Power switch for sensors Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 12 4. Digital and RF Layout The PCB layout is described in the following section and follows the guidelines given above. Figure 4-1 shows the top layer of the PCB where all RF signals are routed. The critical sections are: • • • The RX signal path with LNA and RX SAW filter The TX signal path with TX SAW filter The crystal connections to the ATA8520 or ATA8520D device Figure 4-1 Signal and RF Signal Layout Figure 4-2 shows the second layer, i.e., the GND layer. The cut in the middle of the PCB isolates the critical LNA section and RF signals from the digital area. This improves the noise level for the LNA, which operates at very low signal levels of −126dBm. The second area is to isolate the crystal and to improve the temperature drift behavior of the crystal. Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 13 Figure 4-2 Ground Plane Layout Figure 4-3 shows the third layer, i.e., the supply layer with the same structure as shown in Figure 4-2. The areas for the 5V supply (used for the ATA8520-EK2-E kit only) and the 3V sensor supply are also shown. Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 14 Figure 4-3 5V/3V Supply Plane Layout The fourth layer used for signal routing is not shown here; however it is included in the PCB data [5]. To change the PCB for uplink only operation the modifications shown in Figure 2-2 have to be applied to the top layer signal plane. This is shown in Figure 4-4. It is not required to do these changes for uplink only operation but can be used for PCB testing. Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 15 Figure 4-4 Layout Changes for Uplink only Operation Figure 4-5 shows the PCB stack layer composition. For 50Ω signal matching, it is important to have the material and setup of layer LY-Top and layer LY-2 as shown in Figure 4-5. Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 16 Figure 4-5 PCB stack layer The manufacturing data for the PCB is as follows: • • • • • • • • • • PCB material: IT-180A, 1.57mm thick Layers: 4 Finish: ENIG Minimum via hole size: 0.4mm Minimum via pad size: 0.7mm Minimum track width: 0.2mm (7.87mils) Minimum spacing: 0.254mm (10mils) Internal power plane (negative) – mid-layer 1, GND Internal power plane (negative) – mid-layer 2, PWR (split plane) Controlled impedance: 50Ω Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 17 5. End-Of-Line Testing The final PCB should be tested end-of-line as described in [11]. An important step is the required RF frequency calibration due to the crystal frequency offset as well as the PCB capacitance for the crystal signal connections to the ATA8520D transceiver device. This additional capacitance is not compensated for by the internal capacitors and requires an offset correction. The ATA8520 and ATA8520D devices can store the crystal compensation values given by the crystal manufacturer in an internal EEPROM. During EOL testing, these crystal parameters are corrected with the actual crystal offset and the additional PCB offset characteristic and programmed into the internal EEPROM.. This calibration ensures the SIGFOX operation with the remaining temperature drift for the crystal frequency. Additional calibration at a second temperature is required depending on the temperature range for the operation of the final SIGFOX node product. This is described in [12] and is mandatory for CE compliant operation and testing (see [13]). For SIGFOX compliant operation this step is not required as the crystal temperature drift is already taken into account for the RF frequency selection during up- and downlink operation. Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 18 6. References [1] ATA8520 transmitter datasheet [2] ATA8520D transceiver datasheet [3] SIGFOX RF module qualification Atmel, M_000C_6D5A_02, October 5, 2015 [4] CE Certification E817418C-CC, October 27, 2015 [5] ATAB0101A-V3.1_design_documentation.pdf [6] EPCOS/TDK SAW Filter B3744, B39871B3744H110 [7] TAI-SAW SAW Filter TA1457A [8] Infineon, Application Note No. 150, Rev. 1.2, “900 MHz Low-Noise Amplifier Using the BFR360F Transistor in TSFP-3 Package” [9] NDK NX3225SA 24.305MHz, EXS00A-CS08551 / EXS00A-CS08559 or KDS DSX321G 24.305MHz, 1C324305AB0B [10] ATmega328P datasheet [11] ATAN0136 - ATA8520D Production and EOL Testing [12] ATAN0142 - ATA8520D Crystal Calibration [13] ATAN0140 - ATA8520D CE Conformance Testing and SIGFOX Certification Atmel ATA8520D Reference Design [APPLICATION NOTE] Atmel-9407A-ATAN0144_Application Note-11/2015 19 Atmel Corporation © 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com 2015 Atmel Corporation. / Rev.: Atmel-9407A-ATAN0144_Application Note-11/2015 ® ® ® Atmel , Atmel logo and combinations thereof, Enabling Unlimited Possibilities , AVR , and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. 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