ATtiny20 - Summary

ATtiny20
8-bit AVR Microcontroller
with 2K Bytes In-System Programmable Flash
DATASHEET SUMMARY
Features
z High performance, low power 8-bit AVR® microcontroller
z Advanced RISC architecture
z
z
z
z
112 powerful instructions – most single clock cycle execution
16 x 8 general purpose working registers
Fully static operation
Up to 12 MIPS throughput at 12MHz
z Non-volatile program and data memories
z
z
z
z
2K bytes of in-system programmable flash program memory
128 bytes internal SRAM
Flash write/erase cycles: 10,000
Data retention: 20 years at 85oC / 100 years at 25oC
z Peripheral features
z
z
z
z
z
z
z
One 8-bit timer/counter with two PWM channels
One 16-bit timer/counter with two PWM channels
10-bit analog to digital converter
z 8 single-ended channels
Programmable watchdog timer with separate on-chip oscillator
On-chip analog comparator
Master/slave SPI serial interface
Slave TWI serial interface
z Special microcontroller features
z
z
z
z
z
In-system programmable
External and internal interrupt sources
Low power idle, ADC noise reduction, stand-by and power-down modes
Enhanced power-on reset circuit
Internal calibrated oscillator
z I/O and packages
z
z
z
z
14-pin SOIC/TSSOP: 12 programmable I/O lines
12-ball WLCSP: 10 programmable I/O lines
15-ball UFBGA: 12 programmable I/O lines
20-pad VQFN: 12 programmable I/O lines
z Operating voltage:
z
1.8 – 5.5V
z Programming voltage:
z
5V
z Speed grade
z
z
z
0 – 4MHz @ 1.8 – 5.5V
0 – 8MHz @ 2.7 – 5.5V
0 – 12MHz @ 4.5 – 5.5V
z Industrial temperature range
z Low power consumption
Active mode:
z 200 μA at 1MHz and 1.8V
z Idle mode:
z 25μA at 1MHz and 1.8V
z Power-down mode:
z < 0.1μA at 1.8V
z
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
1.
Pin Configurations
1.1
SOIC & TSSOP
Figure 1-1. SOIC/TSSOP
VCC
(PCINT8/TPICLK/T0/CLKI) PB0
(PCINT9/TPIDATA/MOSI/SDA/OC1A) PB1
(PCINT11/RESET) PB3
(PCINT10/INT0/MISO/OC1B/OC0A/CKOUT) PB2
(PCINT7/SCL/SCK/T1/ICP1/OC0B/ADC7) PA7
(PCINT6/SS/ADC6) PA6
14
2
13
3
12
4
11
5
10
6
9
7
8
GND
PA0 (ADC0/PCINT0)
PA1 (ADC1/AIN0/PCINT1)
PA2 (ADC2/AIN1/PCINT2)
PA3 (ADC3/PCINT3)
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
VQFN
NOTE
Bottom pad should be
soldered to ground.
DNC: Do Not Connect
16
17
18
13
4
12
5
11
10
3
9
14
8
15
2
7
1
6
(PCINT4/ADC4) PA4
(PCINT3/ADC3) PA3
(PCINT2/AIN1/ADC2) PA2
(PCINT1/AIN0/ADC1) PA1
(PCINT0/ADC0) PA0
19
20
DNC
DNC
DNC
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6/SS)
Figure 1-2. VQFN
PA7 (ADC7/OC0B/ICP1/T1/SCL/SCK/PCINT7)
PB2 (CKOUT/OC0A/OC1B/MISO/INT0/PCINT10)
PB3 (RESET/PCINT11)
PB1 (OC1A/SDA/MOSI/TPIDATA/PCINT9)
PB0 (CLKI/T0/TPICLK/PCINT8)
DNC
DNC
GND
VCC
DNC
1.2
1
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
2
1.3
UFBGA
Figure 1-3. UFBGA
1
2
3
4
2
1
A
B
B
C
C
D
D
BOTTOM VIEW
UFBGA Pin Configuration
1
A
1.4
3
A
TOP VIEW
Table 1-1.
4
2
3
4
PA5
PA6
PB2
B
PA4
PA7
PB1
PB3
C
PA3
PA2
PA1
PB0
D
PA0
GND
GND
VCC
Wafer Level Chip Scale Package
Figure 1-4. WLCSP
1
2
3
4
A
A
B
B
C
C
D
D
TOP VIEW
Table 1-2.
D
2
PA4
3
4
PA1
PA6
B
C
BOTTOM VIEW
WLCSP Ball Configuration
1
A
6 5 4 3 2 1
PA5
6
PA2
GND
PA7
PB2
5
VDD
PB1
PB3
PB0
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
3
1.5
Pin Description
1.5.1
VCC
Supply voltage.
1.5.2
GND
Ground.
1.5.3
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is
not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 20-4 on
page 170. Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
1.5.4
Port A (PA7:PA0)
Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port A has alternate functions as analog inputs for the ADC, analog comparator and pin change interrupt as described
in “Alternate Port Functions” on page 47.
1.5.5
Port B (PB3:PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers
have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET
capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated
when a reset condition becomes active, even if the clock is not running.
The port also serves the functions of various special features of the ATtiny20, as listed on page 37.
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
4
2.
Overview
ATtiny20 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATtiny20 achieves throughputs approaching 1 MIPS per
MHz allowing the system designer to optimize power consumption versus processing speed.
Figure 2-1. Block Diagram
VCC
RESET
PROGRAMMING
LOGIC
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
CALIBRATED
OSCILLATOR
PROGRAM
FLASH
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
INSTRUCTION
REGISTER
SRAM
RESET FLAG
REGISTER
INSTRUCTION
DECODER
INTERRUPT
UNIT
MCU STATUS
REGISTER
CONTROL
LINES
GENERAL
PURPOSE
REGISTERS
TIMER/
COUNTER0
X
Y
Z
ISP
INTERFACE
TIMER/
COUNTER1
ALU
SPI
ANALOG
COMPARATOR
STATUS
REGISTER
TWI
ADC
8-BIT DATA BUS
DIRECTION
REG. PORT A
DATA REGISTER
PORT A
DRIVERS
PORT A
PA[7:0]
DIRECTION
REG. PORT B
DATA REGISTER
PORT B
DRIVERS
PORT B
GND
PB[3:0]
ATtiny20 [DATASHEET]
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5
The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed
in one single instruction executed in one clock cycle. The resulting architecture is compact and code efficient while
achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATtiny20 provides the following features:
z
2K bytes of in-system programmable Flash
z
128 bytes of SRAM
z
Twelve general purpose I/O lines
z
16 general purpose working registers
z
An 8-bit Timer/Counter with two PWM channels
z
A 16-bit Timer/Counter with two PWM channels
z
Internal and external interrupts
z
An eight-channel, 10-bit ADC
z
A programmable Watchdog Timer with internal oscillator
z
A slave two-wire interface
z
A master/slave serial peripheral interface
z
An internal calibrated oscillator
z
Four software selectable power saving modes
The device includes the following modes for saving power:
z
Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI, TWI, and interrupt
system to continue functioning
z
ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping the CPU and all
I/O modules except the ADC
z
Power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or
hardware reset
z
Standby mode: the oscillator is running while the rest of the device is sleeping, allowing very fast start-up
combined with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip, in-system
programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory
programmer.
The ATtiny20 AVR is supported by a suite of program and system development tools, including macro assemblers
and evaluation kits.
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
6
3.
General Information
3.1
Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available
for download at http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These
code examples assume that the part specific header file is included before compilation. Be aware that not all C
compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please
confirm with the C compiler documentation for more details.
3.3
Capacitive Touch Sensing
Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcontrollers.
The QTouch Library includes support for QTouch® and QMatrix® acquisition methods.
Touch sensing is easily added to any application by linking the QTouch Library and using the Application
Programming Interface (API) of the library to define the touch channels and sensors. The application then calls the
API to retrieve channel information and determine the state of the touch sensor.
The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of
implementation, refer to the QTouch Library User Guide – also available from the Atmel website.
3.4
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 100 years at 25°C.
3.5
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of other AVR
microcontrollers manufactured on the same process technology.
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
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4.
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F
SREG
I
T
H
S
V
N
Z
C
Page 14
0x3E
SPH
Stack Pointer High Byte
0x3D
SPL
Stack Pointer Low Byte
Page 13
Page 13
0x3C
CCP
CPU Change Protection Byte
Page 13
0x3B
RSTFLR
–
–
–
–
WDRF
BORF
EXTRF
PORF
Page 35
0x3A
MCUCR
ICSC01
ICSC00
–
BODS
SM2
SM1
SM0
SE
Pages 26, 38
–
–
–
0x39
OSCCAL
0x38
Reserved
–
–
–
Oscillator Calibration Byte
–
0x37
CLKMSR
–
–
–
–
–
–
CLKMS1
CLKMS0
Page 20
0x36
CLKPSR
–
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Page 21
–
–
–
PRTWI
PRSPI
PRTIM1
PRTIM0
PRADC
Page 27
0x35
PRR
0x34
QTCSR
0x33
NVMCMD
–
Page 22
–
QTouch Control and Status Register
–
Page 7
NVM Command
Page 166
0x32
NVMCSR
NVMBSY
–
–
–
–
–
–
–
0x31
WDTCSR
WDIF
WDIE
WDP3
–
WDE
WDP2
WDP1
WDP0
Page 33
0x30
SPCR
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
Page 132
0x2F
SPSR
SPIF
WCOL
–
–
–
–
SSPS
SPI2X
0x2E
SPDR
SPI Data Register
Page 166
Page 133
Page 134
0x2D
TWSCRA
TWSHE
–
TWDIE
TWASIE
TWEN
TWSIE
0x2C
TWSCRB
–
–
–
–
–
TWAA
0x2B
TWSSRA
TWDIF
TWASIF
TWCH
TWRA
TWC
TWBE
0x2A
TWSA
TWI Slave Address Register
0x29
TWSAM
TWI Slave Address Mask Register
Page 147
0x28
TWSD
TWI Slave Data Register
Page 146
0x27
GTCCR
TSM
–
–
–
–
–
–
PSR
Page 104
0x26
TIMSK
ICE1
–
OCIE1B
OCIE1A
TOIE1
OCIE0B
OCIE0A
TOIE0
Pages 74, 101
Pages 75, 102
TWPME
TWSME
TWCMD[1.0]
TWDIR
Page 143
Page 144
TWAS
Page 145
Page 146
0x25
TIFR
ICF1
–
OCF1B
OCF1A
TOV1
OCF0B
OCF0A
TOV0
0x24
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
–
–
WGM11
WGM10
Page 96
0x23
TCCR1B
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
Page 98
0x22
TCCR1C
FOC1A
FOC1B
–
–
–
–
–
–
0x21
TCNT1H
Timer/Counter1 – Counter Register High Byte
Page 100
Page 100
0x20
TCNT1L
Timer/Counter1 – Counter Register Low Byte
Page 100
0x1F
OCR1AH
Timer/Counter1 – Compare Register A High Byte
Page 100
0x1E
OCR1AL
Timer/Counter1 – Compare Register A Low Byte
Page 100
0x1D
OCR1BH
Timer/Counter1 – Compare Register B High Byte
Page 101
0x1C
OCR1BL
Timer/Counter1 – Compare Register B Low Byte
Page 101
0x1B
ICR1H
Timer/Counter1 - Input Capture Register High Byte
Page 101
0x1A
ICR1L
Timer/Counter1 - Input Capture Register Low Byte
0x19
TCCR0A
COM0A1
COM0A0
COM0B1
COM0B0
–
–
WGM01
WGM00
Page 69
0x18
TCCR0B
FOC0A
FOC0B
–
–
WGM02
CS02
CS01
CS00
Page 72
Page 101
0x17
TCNT0
Timer/Counter0 – Counter Register
Page 73
0x16
OCR0A
Timer/Counter0 – Compare Register A
Page 74
0x15
OCR0B
0x14
ACSRA
Timer/Counter0 – Compare Register B
ACD
ACBG
ACO
ACI
ACIE
Page 74
ACIC
ACIS1
ACIS0
Page 106
0x13
ACSRB
HSEL
HLEV
ACLP
–
ACCE
ACME
ACIRS1
ACIRS0
Page 107
0x12
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
Page 122
0x11
ADCSRB
VDEN
VDPD
–
–
ADLAR
ADTS2
ADTS1
ADTS0
Page 123
0x10
ADMUX
–
REFS
REFEN
ADC0EN
MUX3
MUX2
MUX1
MUX0
Page 120
0x0F
ADCH
ADC Conversion Result – High Byte
0x0E
ADCL
ADC Conversion Result – Low Byte
Page 121
0x0D
DIDR0
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
0x0C
GIMSK
–
–
PCIE1
PCIE0
–
–
0x0B
GIFR
–
–
PCIF1
PCIF0
–
–
0x0A
PCMSK1
–
–
–
–
PCINT11
0x09
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
0x08
PORTCR
–
–
–
–
Page 121
ADC0D
Page 124
–
INT0
Page 39
–
INTF0
Page 40
PCINT10
PCINT9
PCINT8
Page 40
PCINT3
PCINT2
PCINT1
PCINT0
Page 41
–
–
BBMB
BBMA
Page 56
Page 57
0x07
PUEB
–
–
–
–
PUEB3
PUEB2
PUEB1
PUEB0
0x06
PORTB
–
–
–
–
PORTB3
PORTB2
PORTB1
PORTB0
Page 57
0x05
DDRB
–
–
–
–
DDRB3
DDRB2
DDRB1
DDRB0
Page 57
0x04
PINB
–
–
–
–
PINB3
PINB2
PINB1
PINB0
Page 58
0x03
PUEA
PUEA7
PUEA6
PUEA5
PUEA4
PUEA3
PUEA2
PUEA1
PUEA0
Page 57
0x02
PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
Page 57
0x01
DDRA
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Page 57
0x00
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
Page 57
ATtiny20 [DATASHEET]
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8
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI
and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such
Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
ATtiny20 [DATASHEET]
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5.
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add without Carry
Rd ← Rd + Rr
Z,C,N,V,S,H
ADC
Rd, Rr
Add with Carry
Rd ← Rd + Rr + C
Z,C,N,V,S,H
1
SUB
Rd, Rr
Subtract without Carry
Rd ← Rd - Rr
Z,C,N,V,S,H
1
1
SUBI
Rd, K
Subtract Immediate
Rd ← Rd - K
Z,C,N,V,S,H
1
SBC
Rd, Rr
Subtract with Carry
Rd ← Rd - Rr - C
Z,C,N,V,S,H
1
SBCI
Rd, K
Subtract Immediate with Carry
Rd ← Rd - K - C
Z,C,N,V,S,H
1
AND
Rd, Rr
Logical AND
Rd ← Rd • Rr
Z,N,V,S
1
ANDI
Rd, K
Logical AND with Immediate
Rd ← Rd • K
Z,N,V,S
1
OR
Rd, Rr
Logical OR
Rd ← Rd v Rr
Z,N,V,S
1
ORI
Rd, K
Logical OR with Immediate
Rd ← Rd v K
Z,N,V,S
1
EOR
Rd, Rr
Exclusive OR
Rd ← Rd ⊕ Rr
Z,N,V,S
1
COM
Rd
One’s Complement
Rd ← $FF − Rd
Z,C,N,V,S
1
NEG
Rd
Two’s Complement
Rd ← $00 − Rd
Z,C,N,V,S,H
1
1
SBR
Rd,K
Set Bit(s) in Register
Rd ← Rd v K
Z,N,V,S
CBR
Rd,K
Clear Bit(s) in Register
Rd ← Rd • ($FFh - K)
Z,N,V,S
1
INC
Rd
Increment
Rd ← Rd + 1
Z,N,V,S
1
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V,S
1
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V,S
1
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Z,N,V,S
1
SER
Rd
Set Register
Rd ← $FF
None
1
Relative Jump
PC ← PC + k + 1
None
2
Indirect Jump to (Z)
PC(15:0) ← Z, PC(21:16) ← 0
None
2
BRANCH INSTRUCTIONS
RJMP
k
IJMP
Relative Subroutine Call
PC ← PC + k + 1
None
3/4
ICALL
Indirect Call to (Z)
PC(15:0) ← Z, PC(21:16) ← 0
None
3/4
RET
Subroutine Return
PC ← STACK
None
4/5
RETI
Interrupt Return
PC ← STACK
I
Compare, Skip if Equal
if (Rd = Rr) PC ← PC + 2 or 3
None
RCALL
CPSE
k
Rd,Rr
4/5
1/2/3
CP
Rd,Rr
Compare
Rd − Rr
Z, C,N,V,S,H
1
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
Z, C,N,V,S,H
1
CPI
Rd,K
Compare with Immediate
Rd − K
Z, C,N,V,S,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC ← PC + 2 or 3
None
1/2/3
1/2/3
1
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC ← PC + 2 or 3
None
SBIC
A, b
Skip if Bit in I/O Register Cleared
if (I/O(A,b)=0) PC ← PC + 2 or 3
None
1/2/3
SBIS
A, b
Skip if Bit in I/O Register is Set
if (I/O(A,b)=1) PC ← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC←PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC←PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ← PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ← PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ← PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ← PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ← PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V,H
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V,H
1
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
10
Mnemonics
Operands
Description
Operation
Flags
#Clocks
SBI
A, b
Set Bit in I/O Register
I/O(A, b) ← 1
None
1
CBI
A, b
Clear Bit in I/O Register
I/O(A, b) ← 0
None
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ← T
None
1
1
SEC
Set Carry
C←1
C
CLC
Clear Carry
C←0
C
1
SEN
Set Negative Flag
N←1
N
1
CLN
Clear Negative Flag
N←0
N
1
SEZ
Set Zero Flag
Z←1
Z
1
CLZ
Clear Zero Flag
Z←0
Z
1
SEI
Global Interrupt Enable
I←1
I
1
CLI
Global Interrupt Disable
I←0
I
1
SES
Set Signed Test Flag
S←1
S
1
CLS
Clear Signed Test Flag
S←0
S
1
SEV
Set Two’s Complement Overflow.
V←1
V
1
CLV
Clear Two’s Complement Overflow
V←0
V
1
SET
Set T in SREG
T←1
T
1
CLT
Clear T in SREG
T←0
T
1
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H←1
H←0
H
H
1
1
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Copy Register
Rd ← Rr
None
LDI
Rd, K
Load Immediate
Rd ← K
None
1
LD
Rd, X
Load Indirect
Rd ← (X)
None
1/2
LD
Rd, X+
Load Indirect and Post-Increment
Rd ← (X), X ← X + 1
None
2
LD
Rd, - X
Load Indirect and Pre-Decrement
X ← X - 1, Rd ← (X)
None
2/3
1/2
LD
Rd, Y
Load Indirect
Rd ← (Y)
None
LD
Rd, Y+
Load Indirect and Post-Increment
Rd ← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Decrement
Y ← Y - 1, Rd ← (Y)
None
2/3
1/2
LD
Rd, Z
Load Indirect
Rd ← (Z)
None
LD
Rd, Z+
Load Indirect and Post-Increment
Rd ← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Decrement
Z ← Z - 1, Rd ← (Z)
None
2/3
LDS
Rd, k
Store Direct from SRAM
Rd ← (k)
None
1
ST
X, Rr
Store Indirect
(X) ← Rr
None
1
ST
X+, Rr
Store Indirect and Post-Increment
(X) ← Rr, X ← X + 1
None
1
ST
- X, Rr
Store Indirect and Pre-Decrement
X ← X - 1, (X) ← Rr
None
2
1
ST
Y, Rr
Store Indirect
(Y) ← Rr
None
ST
Y+, Rr
Store Indirect and Post-Increment
(Y) ← Rr, Y ← Y + 1
None
1
ST
- Y, Rr
Store Indirect and Pre-Decrement
Y ← Y - 1, (Y) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ← Rr
None
1
ST
Z+, Rr
Store Indirect and Post-Increment.
(Z) ← Rr, Z ← Z + 1
None
1
ST
-Z, Rr
Store Indirect and Pre-Decrement
Z ← Z - 1, (Z) ← Rr
None
2
1
STS
k, Rr
Store Direct to SRAM
(k) ← Rr
None
IN
Rd, A
In from I/O Location
Rd ← I/O (A)
None
1
OUT
A, Rr
Out to I/O Location
I/O (A) ← Rr
None
1
PUSH
Rr
Push Register on Stack
STACK ← Rr
None
2
POP
Rd
Pop Register from Stack
Rd ← STACK
None
2
MCU CONTROL INSTRUCTIONS
BREAK
Break
(see specific descr. for Break)
None
1
NOP
No Operation
None
1
SLEEP
WDR
Sleep
Watchdog Reset
None
None
1
(see specific descr. for Sleep)
(see specific descr. for WDR)
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
1
11
6.
Ordering Information
6.1
ATtiny20
Speed
Supply Voltage
Temperature Range
Package (2)
12U-1
14S1
12 MHz
1.8 – 5.5V
14X
Industrial
(-40°C to +85°C) (4)
15CC1
20M2
Ordering Code (1)
ATtiny20-UUR
ATtiny20-SSU
ATtiny20-SSUR
ATtiny20-XU
ATtiny20-XUR
ATtiny20-CCU
ATtiny20-CCUR
ATtiny20-MMH (3)
ATtiny20-MMHR (3)
Notes: 1. Code indicators:
z
H: NiPdAu lead finish
z
U: matte tin
z
R: tape & reel
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of
Hazardous Substances (RoHS).
3. Topside marking for ATtiny20:
z
1st Line: T20
z
2nd & 3rd Line: manufacturing data
4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
Package Type
12U-1
12-ball 1.540 x 1.388mm Body, 0.433 mm thick, 0.40 mm Pitch (3x4 Staggered Array), WLCSP
14S1
14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
14X
14-lead, 4.4 mm Body, Thin Shrink Small Outline Package (TSSOP)
15CC1
15-ball (4 x 4 Array), 0.65 mm Pitch, 3.0 x 3.0 x 0.6 mm, Ultra Thin Fine-Pitch Ball Grid Array Package (UFBGA)
20M2
20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
12
7.
Packaging Information
7.1
12U-3
*!j
@;
+, G &#&' *
&#\
+ ' $%
' + &k
*
- M Q &#&' P M Q &#&' P *
H
*
&#&&
-
H
H
iJQ,W
-;
=$$=?%$H?-%=?Q?%@=$H-XHY$$W
$%?
G
-<$*=>
&#'[
&#+
&#[&
&#&'
&#&
J
&#Z
&#Z
&#ZZ
$
+
%
&
'
'
?
#&&&*-
-
&#Z*-
H
&#+&&*-
-
&#+&&*-
&#&\'
;
*
\
*
#+&
H
#&Z*-
HQ$,W
[email protected]
#'''
!$`
$,
Q$,W
?!]J]!^_!`!^!J""#
"""""#
?]]"_"f#
?=$
*
*&
!"#!
7,7/(
8qJ""#'''`#+&!!*vq&#'[!!
_q&#+&!!_Q+`-vWq
w>-Q'+&W
*3&
'5$:,1*12
5(9
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
13
7.2
14S1
1
E
H
E
N
L
Top View
End View
e
COMMON DIMENSIONS
(Unit of Measure = mm/inches)
b
A1
A
D
Side View
MIN
NOM
MAX
A
1.35/0.0532
–
1.75/0.0688
A1
0.1/.0040
–
0.25/0.0098
SYMBOL
b
0.33/0.0130
–
0.5/0.0200 5
D
8.55/0.3367
–
8.74/0.3444 2
E
3.8/0.1497
–
3.99/0.1574 3
H
5.8/0.2284
–
6.19/0.2440
L
0.41/0.0160
–
1.27/0.0500 4
e
Notes:
NOTE
1.27/0.050 BSC
1. This drawing is for general information only; refer to JEDEC Drawing MS-012, Variation AB for additional information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not
exceed 0.15 mm (0.006") per side.
3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm
(0.010") per side.
4. L is the length of the terminal for soldering to a substrate.
5. The lead width B, as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value
of 0.61 mm (0.024") per side.
2/5/02
Package Drawing Contact:
[email protected]
TITLE
DRAWING NO.
14S1, 14-lead, 0.150" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
14S1
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
REV.
A
14
7.3
14X
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
JEDEC Standard MO-153 AB-1.
INDEX MARK
PIN
1
4.50 (0.177)
4.30 (0.169)
5.10 (0.201)
4.90 (0.193)
0.65 (.0256) BSC
1.20 (0.047) MAX
0.15 (0.006)
0.05 (0.002)
0.30 (0.012)
0.19 (0.007)
6.50 (0.256)
6.25 (0.246)
SEATING
PLANE
0.20 (0.008)
0.09 (0.004)
0º~ 8º
0.75 (0.030)
0.45 (0.018)
05/16/01
Package Drawing Contact:
[email protected]
TITLE
14X (Formerly "14T") , 14-lead (4.4 mm Body) Thin Shrink
Small Outline Package (TSSOP)
DRAWING NO. .
REV. .
14X
B
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
15
7.4
15CC1
1
2
3
4
0.08
A
Pin#1 ID
B
SIDE VIEW
D
C
D
b1
A1
E
A
A2
TOP VIEW
E1
15-Øb
e
D
e
COMMON DIMENSIONS
(Unit of Measure = mm)
C
D1
B
A
SYMBOL
MIN
NOM
MAX
A
–
–
0.60
A1
0.12
–
–
0.38 REF
A2
A1 BALL CORNER
1
2
3
4
BOTTOM VIEW
b
0.25
b1
0.25
D
2.90
Note1: Dimension “b” is measured at the maximum ball dia. in a plane parallel
1
–
–
2
3.00
3.10
1.95 BSC
3.10
3.00
1.95 BSC
E1
e
to the seating plane.
0.35
0.30
D1
E 2.90
NOTE
0.65 BSC
Note2: Dimension “b1” is the solderable surface defined by the opening of the
solder resist layer.
TITLE
Package Drawing Contact:
[email protected]
15CC1, 15-ball (4 x 4 Array), 3.0 x 3.0 x 0.6 mm
package, ball pitch 0.65 mm,
Ultra thin, Fine-Pitch Ball Grid Array Package (UFBGA)
GPC
CBC
DRAWING NO.
07/06/10
REV.
15CC1
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
C
16
7.5
20M2
D
C
y
Pin 1 ID
E
SIDE VIEW
TOP VIEW
A1
A
D2
16
17
18
19
20
COMMON DIMENSIONS
(Unit of Measure = mm)
C0.18 (8X)
15
1
Pin #1 Chamfer
(C 0.3)
14
2
e
E2
13
3
12
4
11
5
b
10
9
8
7
6
K
L
BOTTOM VIEW
0.3 Ref (4x)
SYMBOL
MIN
NOM
MAX
A
0.75
0.80
0.85
A1
0.00
0.02
0.05
b
0.17
0.22
0.27
C
0.152
D
2.90
3.00
3.10
D2
1.40
1.55
1.70
E 2.90
3.00
3.10
E2
1.40
1.55
1.70
e
–
0.45
–
L
0.35
0.40
0.45
–
–
0.00
–
K 0.20
y
NOTE
0.08
10/24/08
Package Drawing Contact:
[email protected]
TITLE
20M2, 20-pad, 3 x 3 x 0.85 mm Body, Lead Pitch 0.45 mm,
1.55 x 1.55 mm Exposed Pad, Thermally Enhanced
Plastic Very Thin Quad Flat No Lead Package (VQFN)
GPC
ZFC
DRAWING NO.
20M2
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
REV.
B
17
8.
Errata
The revision letters in this section refer to the revision of the corresponding ATtiny20 device.
8.1
Rev. A
Issue:
Lock bits re-programming
Resolution:
Attempt to re-program Lock bits to present, or lower protection level (tampering attempt),
causes erroneously one, random line of Flash program memory to get erased. The Lock bits
will not get changed, as they should not.
Workaround: Do not attempt to re-program Lock bits to present, or lower protection level.
Issue:
MISO output driver is not disabled by Slave Select (SS) signal
Resolution:
When SPI is configured as a slave and the MISO pin is configured as an output the pin output
driver is constantly enabled, even when the SS pin is high. If other slave devices are connected
to the same MISO line this behaviour may cause drive contention.
Workaround: Monitor SS pin by software and use the DDRB2 bit of DDRB to control the MISO pin driver.
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
18
9.
Datasheet Revision History
Revision
Date
Comments
8235F
09/2014
Changed text in Section 7.1 from 12U-1 to 12U-3.
Updated back page.
8235E
03/13
Updated WLCSP ball configuration on page 3.
Updated WLCSP package drawing, “12U-3” on page 13
8235D
10/12
Updated Document template, and “Pin Configurations” on page 2
8235C
06/12
Updated “Ordering Information” on page 12.
Added Wafer Level Chip Scale Package “12U-3” on page 13.
Removed Preliminary status.
8235B
04/11
Updated Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0], Idle Mode
description on page 6, “Capacitive Touch Sensing” on page 7 (section updated and moved),
“Disclaimer” on page 7, Sentence on low impedance sources in “Analog Input Circuitry” on
page 116, Description on 16-bit registers on page 9, Description on Stack Pointer on page 10,
List of active modules in “Idle Mode” on page 23, Description on reset pulse width in
“Watchdog Reset” on page 30, Program code on page 37, Bit description in Figure 11-3 on
page 62, Section “Compare Output Mode and Waveform Generation” on page 63, Signal
descriptions in Figure 11-5 on page 64, and Figure 11-7 on page 67, Equations on page 65,
page 66, and page 67, Terminology in sections describing extreme values on page 66, and
page 67, Description on creating frequency waveforms on page 67, Signal routing in Figure 121 on page 76, TOP definition in Table 12-1 on page 77, Signal names in Figure 12-3 on page
79, TWSHE bit description in “TWSCRA – TWI Slave Control Register A” on page 143, SPI
slave assembly code example on page 129, Table 21-1 on page 174, Section “Speed” on page
168, Characteristics in Figure 21-3 on page 176, and Figure 21-8 on page 179.
Added Note on internal voltage reference in Table 15-4 on page 121, PRADC in Table 21-2 on
page 175, MISO output driver errata for device rev. A in “Errata” on page 18
8235A
03/10
Initial revision
ATtiny20 [DATASHEET]
Atmel-8235FS-AVR-ATtiny20-Datasheet_09/2014
19
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