AT34C02 - Mature

Features
• Permanent Software Write Protection for the First-half of the Array
– Software Procedure to Verify Write Protect Status
• Hardware Write Protection for the Entire Array
• Low-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
Internally Organized 256 x 8
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
100 kHz (1.8V) and 400 kHz (2.7V and 5.0V) Compatibility
16-byte Page Write Modes
Partial Page Writes Are Allowed
Self-timed Write Cycle (5 ms max)
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade Devices Available
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead TSSOP, and 8-ball dBGA2
Packages
• Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
•
•
•
•
•
•
•
•
•
Two-wire Serial
EEPROM
with Permanent
Software Write
Protect
2K (256 x 8)
Description
The AT34C02 provides 2048 bits of serial electrically-erasable and programmable
read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of
the device incorporates a software write protection feature while hardware write protection for the entire array is available via an external pin as well. Once the software
write protection is enabled, by sending a special command to the device, it cannot be
reversed. The hardware write protection is controlled with the WP pin and can be used
to protect the entire array, whether or not the software write protection has been
enabled. This allows the user to protect none, first-half, or all of the array depending
on the application. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operations are essential. The AT34C02
is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead
TSSOP and 8-ball dBGA2 packages and is accessed via a two-wire serial interface. In
addition, it is available in 1.8V (1.8V to 5.5V) versions.
AT34C02
Note:
Not recommended for new
design; please refer to
AT34CO2C datasheet.
Table 1. Pin Configurations
8-lead PDIP
Pin Name
Function
A0 - A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
A0
A1
A2
GND
1
2
3
4
8
7
6
5
8
7
6
5
VCC
WP
SCL
SDA
8-lead SOIC
VCC
WP
SCL
SDA
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A0
A1
A2
GND
Bottom View
8-lead TSSOP
A0
A1
A2
GND
1
2
3
4
8-lead MAP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
8-ball dBGA2
VCC
WP
SCL
SDA
VCC
WP
SCL
SDA
8
1
7
2
6
3
5
4
A0
A1
A2
GND
Bottom View
Rev. 0958Q–SEEPR–1/07
1
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125 °C
*NOTICE:
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Figure 1. Block Diagram
VCC
GND
WP
START
STOP
LOGIC
SCL
SDA
SERIAL
CONTROL
LOGIC
WRITE PROTECT
CIRCUITRY
EN
H.V. PUMP/TIMING
LOAD
A2
A1
A0
R/W
COMP
LOAD
DATA WORD
ADDR/COUNTER
DATA RECOVERY
SOFTWARE WRITE
PROTECTED AREA
(00H - 7FH)
INC
X DEC
DEVICE
ADDRESS
COMPARATOR
EEPROM
Y DEC
DIN
SERIAL MUX
DOUT/ACK
LOGIC
DOUT
2
AT34C02
0958Q–SEEPR–1/07
AT34C02
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device
address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other
AT24Cxx devices. When the pins are hardwired, as many as eight 2K devices may be
addressed on a single bus system. (Device addressing is discussed in detail under
“Device Addressing,” page 9.) A device is selected when a corresponding hardware and
software match is true. If these pins are left floating, the A2, A1, and A0 pins will be
internally pulled down to GND. However, due to capacitive coupling that may appear
during customer applications, Atmel recommends always connecting the address pins
to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using
a pull-up resistor, Atmel recommends using 10kΩ or less.
Table 2. AT34C02 Write Protection Modes
WP Pin Status
Write Protect Register
Part of the Array Write Protected
VCC
–
Full Array (2K)
GND or Floating
Not Programmed
Normal Read/Write
GND or Floating
Programmed
First-Half of Array
(1K: 00H - 7FH)
Table 3. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol
Test Condition
CI/O
CIN
Note:
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
3
0958Q–SEEPR–1/07
Table 4. DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, TAE = –40°C to +125°C,
VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol
Parameter
Test Condition
VCC1
Supply Voltage
VCC2
Supply Voltage
ICC
Supply Current VCC = 5.0V
READ at 100 kHz
ICC
Supply Current VCC = 5.0V
ISB1
Max
Units
1.8
5.5
V
2.7
5.5
V
0.4
1.0
mA
WRITE at 100 kHz
2.0
3.0
mA
Standby Current VCC = 1.8V
VIN = VCC or VSS
0.6
3.0
µA
ISB2
Standby Current VCC = 2.7V
VIN = VCC or VSS
1.6
4.0
µA
ISB3
Standby Current VCC = 5.0V
VIN = VCC or VSS
8.0
18.0
µA
ILI
Input Leakage Current
VIN = VCC or VSS
0.10
3.0
µA
ILO
Output Leakage Current
VOUT = VCC or VSS
0.05
3.0
µA
–0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
(1)
Min
Typ
VIL
Input Low Level
VIH
Input High Level(1)
VOL2
Output Low Level VCC = 3.0V
IOL = 2.1 mA
0.4
V
VOL1
Output Low Level VCC = 1.8V
IOL = 0.15 mA
0.2
V
Note:
4
1. VIL min and VIH max are reference only and are not tested.
AT34C02
0958Q–SEEPR–1/07
AT34C02
Table 5. AC Characteristics
Applicable over recommended operating range from TAI = –40°C to +85°C, TAE = –40°C to +125°C, VCC = +1.8V to +5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
1.8V
Symbol
Parameter
Min
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
tHIGH
Clock Pulse Width High
2.7V, 5.0V
Max
Min
100
Max
Units
400
kHz
4.7
1.2
µs
4.0
0.6
µs
(1)
tI
Noise Suppression Time
tAA
Clock Low to Data Out Valid
0.1
tBUF
Time the bus must be free before a new
transmission can start(1)
4.7
1.2
µs
tHD.STA
Start Hold Time
4.0
0.6
µs
tSU.STA
Start Set-up Time
4.7
0.6
µs
tHD.DAT
Data In Hold Time
0
0
µs
tSU.DAT
Data In Set-up Time
200
100
ns
100
(1)
Inputs Rise Time
tR
(1)
4.5
0.1
50
ns
0.9
µs
1.0
0.3
µs
300
300
ns
tF
Inputs Fall Time
tSU.STO
Stop Set-up Time
4.7
0.6
µs
tDH
Data Out Hold Time
100
50
ns
tWR
Write Cycle Time
Endurance(1)
5.0V, 25°C, Page Mode
Note:
5
1M
5
1M
ms
Write
Cycles
1. This parameter is characterized and is not 100% tested.
5
0958Q–SEEPR–1/07
Memory Organization
AT34C02, 2K Serial EEPROM: The 2K is internally organized with 16 pages of 16 bytes
each. Random word addressing requires a 8-bit data word address.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see
Figure 5 on page 8). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT34C02 features a low-power standby mode which is enabled:
(a) upon power-up or (b) after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any
two-wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition.
6
AT34C02
0958Q–SEEPR–1/07
AT34C02
Figure 2. Bus Timing SCL: Serial Clock SDA: Serial Data I/O
Figure 3. Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O
SCL
SDA
8th BIT
ACK
WORDn
twr
STOP
CONDITION
Note:
(1)
START
CONDITION
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
7
0958Q–SEEPR–1/07
Figure 5. Start and Stop Condition
Figure 6. Output Acknowledge
8
AT34C02
0958Q–SEEPR–1/07
AT34C02
Device Addressing
The 2K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 8 on page 12).
The device address word consists of a mandatory one-zero sequence for the first four
most-significant bits (1010) for normal read and write operations and 0110 for writing to
the write protect register.
The next 3 bits are the A2, A1 and A0 device address bits for the AT34C02 EEPROM.
These 3 bits must compare to their corresponding hard-wired input pins.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the chip will return to a standby state. The device will not acknowledge if the
write protect register has been programmed and the control code is 0110.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t WR , to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (see Figure 9 on page 12).
The device will acknowledge a write command, but not write the data, if the software or
hardware write protection has been enabled. The write cycle time must be observed
even when the write protection is enabled.
PAGE WRITE: The 2K device is capable of 16-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen
more data words. The EEPROM will respond with a zero after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (see
Figure 10 on page 13).
The data word address lower four bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than sixteen data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten. The address “roll over” during write is from
the last byte of the current page to the first byte of the same page.
The device will acknowledge a write command, but not write the data, if the software or
hardware write protection has been enabled. The write cycle time must be observed
even when the write protection is enabled.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero allowing the read or write sequence to continue.
9
0958Q–SEEPR–1/07
Write Protection
The software write protection, once enabled, permanently write protects only the firsthalf of the array (00H - 7FH) while the hardware write protection, via the WP pin, is used
to protect the entire array.
SOFTWARE WRITE PROTECTION: The software write protection is enabled by sending a command, similar to a normal write command, to the device which programs the
write protect register. This must be done with the WP pin low. The write protect register
is programmed by sending a write command with the device address of 0110 instead of
1010 with the address and data bit being don’t cares (see Figure 7 on page 11). Once
the software write protection has been enabled, the device will no longer acknowledge
the 0110 control byte. The software write protection cannot be reversed even if the
device is powered down. The write cycle time must be observed.
HARDWARE WRITE PROTECTION: The WP pin can be connected to VCC, GND, or
left floating. Connecting the WP pin to VCC will write protect the entire array, regardless
of whether or not the software write protection has been enabled. The software write
protection register cannot be programmed when the WP pin is connected to VCC. If the
WP pin is connected to GND or left floating, the write protection mode is determined by
the status of the software write protect register.
10
AT34C02
0958Q–SEEPR–1/07
AT34C02
WP Connected to GND or Floating
Start
R/W Bit
Write Protect Register
Acknowledgment
from Device
1010
R
X
ACK
Read Array
1010
W
Programmed
ACK
Can Write to Second Half (80H - FFH) Only
1010
W
Not Programmed
ACK
Can Write to Full Array
0110
R
Programmed
No ACK
0110
R
Not Programmed
ACK
0110
W
Programmed
No ACK
0110
W
Not Programmed
ACK
Program Write Protect Register (irreversible)
Action from Device
Stop - Indicates Write Protect Register is Programmed
Read Out Data Don’t Care. Indicates WP Register is Not Prog
Stop - Indicates Write Protect Register is Programmed
WP Connected to VCC
1010
R
X
ACK
Read Array
1010
W
Programmed
ACK
Device Write Protect
1010
W
Not Programmed
ACK
Device Write Protect
0110
R
Programmed
No ACK
0110
R
Not Programmed
ACK
0110
W
Programmed
No ACK
0110
W
Not Programmed
ACK
Stop - Indicates Write Protect Register is Programmed
Read Out Data Don’t Care. Indicates WP Register is Not Prog
Stop - Indicates Write Protect Register is Programmed
Cannot Program Write Protect Register
Figure 7. Setting Write Protect Register
S
T
A
R
T
SDA LINE
CONTROL
BYTE
0 1 1 0
WORD
ADDRESS
S
T
O
P
DATA
0
A
C
K
A
C
K
A
C
K
= Don't Care
Read Operations
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page to the first
byte of the first page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
To end the command, the microcontroller does not respond with an input zero but does
generate a following stop condition (see Figure 11 on page 13).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
11
0958Q–SEEPR–1/07
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. To end the command, the microcontroller
does not respond with a zero but does generate a following stop condition (see Figure
12 on page 13).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condition (see Figure 13 on page 13).
WRITE PROTECT REGISTER STATUS: To find out if the register has been programmed, the same procedure is used as to program the register except that the R/W
bit is set to 1. If the device acknowledges, then the write protect register has not been
programmed. Otherwise, it has been programmed and the device is permanently write
protected at the first half of the array.
Figure 8. Device Address
Figure 9. Byte Write
12
AT34C02
0958Q–SEEPR–1/07
AT34C02
Figure 10. Page Write
Figure 11. Current Address Read
Figure 12. Random Read
Figure 13. Sequential Read
13
0958Q–SEEPR–1/07
Ordering Information(1)
Ordering Code
Package
Operation Range
8P3
8S1
8A2
8Y1
8U3-1
Lead-free/Halogen-free/
Industrial Temperature
(–40°C to 85°C)
AT34C02N-10SE-2.7
AT34C02-10TE-2.7
8S1
8A2
Automotive
(–40°C to 125°C)
AT34C02N-10SQ-2.7(2)
AT34C02-10TQ-2.7(2)
8S1
8A2
Lead-free/Halogen-free/Automotive
(–40°C to 125°C)
Die Sale
Industrial Temperature
(–40°C to 85°C)
AT34C02-10PU-1.8(2)
AT34C02N-10SU-1.8(2)
AT34C02-10TU-1.8(2)
AT34C02Y1-10YU-1.8(2)
AT34C02U3-10UU-1.8(2)
AT34C02-W1.8-11(3)
Notes:
1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics
Tables.
2. “U” and “Q” designate Green package + RoHS compliant.
3. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8A2
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8U3-1
8-ball, die Ball Grid Array Package (dBGA2)
Options
–1.8
14
Low Voltage (1.8V to 5.5V)
AT34C02
0958Q–SEEPR–1/07
AT34C02
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
MIN
NOM
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
D1
0.005
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
SYMBOL
A
b2
b3
b
4 PLCS
Side View
L
Notes:
0.210
0.100 BSC
eA
0.300 BSC
0.115
NOTE
2
3
3
e
L
MAX
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
15
0958Q–SEEPR–1/07
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
Side View
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.00
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
∅
0˚
–
8˚
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
R
16
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1
REV.
B
AT34C02
0958Q–SEEPR–1/07
AT34C02
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
3, 5
E
e
D
A2
6.40 BSC
E1
4.30
4.40
4.50
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
L
0.65 BSC
0.45
L1
Notes:
4
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
17
0958Q–SEEPR–1/07
8Y1 – MAP
PIN 1 INDEX AREA
A
1
3
2
4
PIN 1 INDEX AREA
E1
D1
D
L
8
Bottom View
COMMON DIMENSIONS
(Unit of Measure = mm)
A
Side View
5
e
End View
Top View
6
b
A1
E
7
SYMBOL
MIN
NOM
MAX
A
–
–
0.90
A1
0.00
–
0.05
D
4.70
4.90
5.10
E
2.80
3.00
3.20
D1
0.85
1.00
1.15
E1
0.85
1.00
1.15
b
0.25
0.30
0.35
e
L
NOTE
0.65 TYP
0.50
0.60
0.70
2/28/03
R
18
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1
DRAWING NO.
REV.
8Y1
C
AT34C02
0958Q–SEEPR–1/07
AT34C02
8U3-1 – dBGA2
E
D
1.
b
A1
PIN 1 BALL PAD CORNER
A2
Top View
A
Side View
PIN 1 BALL PAD CORNER
1
2
3
4
8
7
6
5
(d1)
d
e
COMMON DIMENSIONS
(Unit of Measure = mm)
(e1)
Bottom View
8 SOLDER BALLS
1. Dimension “b” is measured at the maximum solder ball diameter.
This drawing is for general information only.
SYMBOL
MIN
NOM
A
0.71
0.81
0.91
A1
0.10
0.15
0.20
A2
0.40
0.45
0.50
b
0.20
0.25
0.30
MAX
D
1.50 BSC
E
2.00 BSC
e
0.50 BSC
e1
0.25 REF
d
1.00 BSC
d1
0.25 REF
NOTE
6/24/03
R
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
DRAWING NO.
REV.
PO8U3-1
A
19
0958Q–SEEPR–1/07
Revision History
20
Doc. Rev.
Date
Comments
0958Q
1/2007
Revision history implemented.
Added Note to Page 1: Not recommended for new design;
please refer to AT34CO2C datasheet.
AT34C02
0958Q–SEEPR–1/07
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