AT24C32D/64D Automotive - Complete

AT24C32D and AT24C64D
I2C Automotive Temperature Serial EEPROM
32K (4096 x 8), 64K (8192 x 8)
DATASHEET
Features

Standard-voltage operation
̶











VCC = 2.5V to 5.5V
Automotive temperature range –40C to 125C
Internally organized 4096 x 8 (32K), 8192 x 8 (64K)
2-wire serial interface compatible with I2C
Schmitt Trigger, filtered inputs for noise suppression
Bidirectional data transfer protocol
400kHz compatibility
Write protect pin for hardware data protection
32-byte page write modes
Partial page writes are allowed
Self-timed write cycle (5ms max)
High-reliability
̶
̶

Endurance: 1 million write cycles
Data retention: 100 years
8-lead JEDEC SOIC and 8-lead TSSOP packages
Description
The Atmel® AT24C32D/64D provides 32768/65536 bits of Serial Electrically
Erasable and Programmable Read-Only Memory (EEPROM) organized as
4096/8192 words of eight bits each. The device is optimized for use in many
automotive applications where low-power and low-voltage operation are essential.
AT24C32D/64D is available in space-saving 8-lead JEDEC SOIC and 8-lead
TSSOP packages and is accessed via a 2-wire serial interface. This device
operates from 2.5V to 5.5V.
Figure 1.
Pin Configurations
Pin Name
Function
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
A0 to A2
Address Inputs
8-lead SOIC
A0
A1
A2
GND
1
8
2
7
3
6
4
5
8-lead TSSOP
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
8
2
7
3
6
4
5
VCC
WP
SCL
SDA
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
1.
Absolute Maximum Ratings*
Operating Temperature  55C to +125C
Storage Temperature 65C to +150C
Voltage on any pin
with respect to ground 1.0V to +7.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA
2.
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions beyond those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device reliability.
Block Diagram
VCC
GND
WP
Start
Stop
Logic
Serial
Control
Logic
LOAD
Device
Address
Comparator
A2
A1
A0
R/W
LOAD
Data Word
ADDR/Counter
DOUT
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
Data Recovery
INC
EEPROM
Serial MUX
DOUT/ACK
Logic
DIN
AT24C32D/64D Automotive [DATASHEET]
H.V. Pump/Timing
COMP
Y DEC
2
EN
X DEC
SCL
SDA
3.
Pin Description
Serial Clock (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative
edge clock data out of each device.
Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open-collector devices.
Device Addresses (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired or left not
connected for hardware compatibility with other Atmel AT24C devices. When the pins are hardwired, as many
as eight 32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail in
Section 6., Device Addressing). If the pins are left floating, the A2, A1, and A0 pins will be internally pulled down
to GND if the capacitive coupling to the circuit board VCC plane is <3pF. If coupling is >3pF, Atmel recommends
connecting the pin to GND.
Write Protect (WP): AT24C32D/64D has a Write Protect pin that provides hardware data protection. The Write
Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is
connected to VCC, the write protection feature is enabled and operates as shown in the following table.
Table 3-1.
Write Protect
WP Pin Status
Part of the Array Protected
At VCC
Full (32K/64K) Array
At GND
Normal Read/Write Operations
AT24C32D/64D Automotive [DATASHEET]
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3
4.
Memory Organization
AT24C32D/64D, 32K/64KSerial EEPROM: The 32K/64K is internally organized as 128/256 pages of 32 bytes
each. Random word addressing requires a 12/13 bit data word address.
4.1
Pin Capacitance(1)
Symbol
Test Condition
CI/O
CIN
Note:
4.2
1.
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (SCL)
6
pF
VIN = 0V
This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TA = -40°C to +125°C,
VCC = +2.5V to +5.5V (unless otherwise noted).
Symbol
Parameter
Max
Units
VCC1
Supply Voltage
5.5
V
ICC
Supply Current VCC = 5.0V
Read at 100kHz
0.4
1.0
mA
ICC
Supply Current VCC = 5.0V
Write at 100kHz
2.0
3.0
mA
ISB1
Standby Current VCC = 2.5V
VIN = VCC or VSS
1.6
4.0
μA
ISB2
Standby Current VCC = 5.0V
VIN = VCC or VSS
4.0
6.0
μA
ILI
Input Leakage Current
VIN = VCC or VSS
0.10
3.0
μA
ILO
Output Leakage Current
VOUT = VCC or VSS
0.05
3.0
μA
Min
Typ
0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
2.5
(1)
VIL
Input Low Level
VIH
Input High Level(1)
VOL2
Output Low Level VCC = 3.0V
IOL = 2.1mA
0.4
V
VOL1
Output Low Level VCC = 1.8V
IOL = 0.15mA
0.2
V
Note:
4
Test Condition
1.
VIL min and VIH max are reference only and are not tested.
AT24C32D/64D Automotive [DATASHEET]
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
4.3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +125°C, VCC = +2.5V to +5.5V,
CL = 1 TTL Gate and 100pF (unless otherwise noted). Test conditions are listed in Note 3.
Symbol
Parameter
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
1.2
μs
tHIGH
Clock Pulse Width High
0.6
μs
tI
Noise Suppression Time(1)
tAA
Clock Low to Data Out Valid
0.1
tBUF
Time the bus must be free before
a new transmission can start(2)
1.2
μs
tHD.STA
Start Hold Time
0.6
μs
tSU.STA
Start Set-up Time
0.6
μs
tHD.DAT
Data In Hold Time
0
μs
tSU.DAT
Data In Set-up Time
100
ns
tR
Inputs Rise Time(2)
300
ns
tF
Inputs Fall Time(2)
300
ns
tSU.STO
Stop Set-up Time
0.6
μs
tDH
Data Out Hold Time
50
ns
tWR
Write Cycle Time
Endurance(2)
5.0V, 25C, Page Mode
Note:
1.
2.
3.
Min
Max
Units
400
kHz
50
ns
0.9
μs
5
1M
ms
Write Cycles
This parameter is characterized and is not 100% tested (TA = 25C).
This parameter is characterized.
AC measurement conditions:

RL (connects to VCC): 1.3k (2.5V, 5.5V), 10k (1.7V)

Input pulse voltages: 0.3VCC to 0.7VCC

Input rise and fall times:  50ns

Input and output timing reference voltages: 0.5 x VCC
AT24C32D/64D Automotive [DATASHEET]
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
5
5.
Device Operation
Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods (see Figure 5-4 on page 7). Data changes during SCL high
periods will indicate a Start or Stop condition as defined below.
Start Condition: A high-to-low transition of SDA with SCL high is a Start condition which must precede any
other command (see Figure 5-5 on page 7).
Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After a read sequence, the
Stop command will place the EEPROM in a standby power mode (see Figure 5-5 on page 7).
Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock
cycle.
Standby Mode: AT24C32D/64D features a low-power standby mode which is enabled:
Upon power-up.
After the receipt of the stop bit and the completion of any internal operations.


Memory Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by
following these steps:
1.
Clock up to nine cycles,
2.
3.
Look for SDA high in each cycle while SCL is high,
Create a Start condition.
Figure 5-1.
Memory Reset
Dummy Clock Cycles
1
SCL
2
3
8
9
Start
Bit
Start
Bit
Stop
Bit
SDA
Figure 5-2.
Bus Timing: SCL
Serial Clock, SDA: Serial Data I/O
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA In
tAA
SDA Out
6
AT24C32D/64D Automotive [DATASHEET]
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
tDH
tBUF
Figure 5-3.
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
8th bit
SDA
ACK
WORDn
twr(1)
Start
Condition
Stop
Condition
Note:
1.
Figure 5-4.
The write cycle time tWR is the time from a valid Stop condition of a write sequence to the end of the internal
clear/write cycle.
Data Validity
SDA
SCL
Data Stable
Data Stable
Data
Change
Figure 5-5.
Start and Stop Definition
SDA
SCL
Start
Stop
AT24C32D/64D Automotive [DATASHEET]
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7
Figure 5-6.
Output Acknowledge
1
SCL
8
9
Data In
Data Out
Start
6.
Acknowledge
Device Addressing
The 32K/64K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a
read or write operation (see Figure 8-1 on page 9).
The device address word consists of a mandatory one, zero sequence for the first four most significant bits as
shown. This is common to all the Serial EEPROM devices.
The 32K/64K uses the three device address bits, A2, A1, and A0, to allow as many as eight devices on the same
bus. These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal
proprietary circuit that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is
high and a write operation is initiated if this bit is low.
If the device address meets the requirements listed above, the device will acknowledge with a zero by pulling the
SDA signal low. If the comparison is not made, the device will return to a standby state and the SDA signal will float
high.
7.
Write Operations
Byte Write: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the
first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the
EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this
Write cycle and the EEPROM will not respond until the write is complete (see Figure 8-2 on page 9).
Page Write: The 32K/64K EEPROM is capable of 32-byte page writes.
A Page Write is initiated the same as a Byte Write, but the microcontroller does not send a stop condition after the
first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the
microcontroller can transmit up to thirty-one more data words. The EEPROM will respond with a zero after each
data word received. The microcontroller must terminate the Page Write sequence with a stop condition (see Figure
8-3 on page 10).
The data word address lower five bits are internally incremented following the receipt of each data word. The
higher data word address bits are not incremented, retaining the memory page row location. When the word
address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the
8
AT24C32D/64D Automotive [DATASHEET]
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
same page. If more than thirty-one data words are transmitted to the EEPROM, the data word address will rollover and previous data will be overwritten.
Acknowledge Polling: Once the internally timed Write cycle has started and the EEPROM inputs are disabled,
Acknowledge Polling can be initiated. This involves sending a start condition followed by the device address
word. The Read/Write bit is representative of the operation desired. Only if the internal write cycle has
completed will the EEPROM respond with a zero, allowing the Read or Write sequence to continue.
8.
Read Operations
Read operations are initiated the same way as Write operations with the exception that the Read/Write select bit
in the device address word is set to one. There are three Read operations; Current Address Read, Random
Address Read, and Sequential Read.
Current Address Read: The internal data word address counter maintains the last address accessed during
the last Read or Write operation, incremented by one. This address stays valid between operations as long as
the chip power is maintained. The address roll-over during Read is from the last byte of the last memory page to
the first byte of the first page. The address roll-over during Write is from the last byte of the current page to the
first byte of the same page.
Once the device address with the Read/Write select bit set to one is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an
input zero but does generate a following Stop condition (see Figure 8-4 on page 10).
Random Read: A Random Read requires a dummy Byte Write sequence to load in the data word address.
Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a current address read
by sending a device address with the Read/Write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond with a zero but does
generate a following stop condition (see Figure 8-5 on page 10).
Sequential Read: Sequential Reads are initiated by either a Current Address Read or a Random Address
Read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM
receives an acknowledge, it will continue to increment the data word address and serially clock out sequential
data words. When the memory address limit is reached, the data word address will roll-over and the Sequential
Read will continue. The Sequential Read operation is terminated when the microcontroller does not send an
acknowledge (pull the SDA signal low), but does generate the Stop condition. (see Figure 8-6 on page 10).
Figure 8-1.
1
0
Device Address
1
0
A2 A1 A0 R/W
MSB
LSB
Figure 8-2.
Byte Write
S
T
A
R
T
Device
Address
W
R
I
T
E
M
S
B
1.
2.
Second
Word Address
S
T
O
P
Data
t
SDA Line
Notes:
First
Word Address
L R A
S / C
BW K
M
S
B
A
C
K
L A
SC
B K
A
C
K
* = Don't care bits
t = Don't care bit for AT24C32D
AT24C32D/64D Automotive [DATASHEET]
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
9
Figure 8-3.
Page Write
S
T
A
R
T
Device
Address
W
R
I
T
E
First
Word Address (n)
Data (n)
S
T
O
P
Data (n + x)
t
SDA Line
M
S
B
Notes:
Second
Word Address (n)
1.
2.
A
C
K
LR A
S / C
BW K
A
C
K
A
C
K
A
C
K
* = Don't care bits
t = Don't care bit for AT24C32D
Figure 8-4.
Current Address Read
S
T
A
R
T
R
E
A
D
Device
Address
S
T
O
P
DATA
SDA Line
M
S
B
Figure 8-5.
N
O
LR A
S / C
BW K
A
C
K
Random Read
S
T
A
R
T
Device
Address
W
R
I
T
E
S
T
A
R
T
1st, 2nd Word
Address (n)
Device
Address
R
E
A
D
S
T
O
P
Data (n)
SDA Line
M
S
B
A
C
K
LR A
S / C
BW K
A
C
K
N
O
A
C
K
Dummy Write
Note:
1.
Figure 8-6.
* = Don’t care bits
Sequential Read
Device
Address
R
E
A
D
Data (n)
A
C
K
Data (n + 1)
A
C
K
Data (n + 2)
A
C
K
S
T
O
P
Data (n + x)
SDA Line
R A
/ C
WK
10
AT24C32D/64D Automotive [DATASHEET]
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
N
O
A
C
K
8.1
Power Recommendation
The device internal POR (Power-On Reset) threshold is just below the minimum operating voltage of the device.
Power shall rise monotonically from 0.0Vdc to full VCC in less than 1ms. Hold at full VCC for at least 100μs before
the first operation. Power shall drop from full VCC to 0.0Vdc in less than 1ms. Power dropping to a non-zero level
and then slowly going to zero is not recommended. Power shall remain off (0.0Vdc) for 0.5s minimum. Please
consult Atmel if your power conditions do not meet the above recommendations.
AT24C32D/64D Automotive [DATASHEET]
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
11
9.
Product Markings
AT24C32D and AT24C64D: Package Marking Information
8-lead TSSOP
8-lead SOIC
ATPYWW
###D @
AAAAAAA
ATMLPYWW
###D
@
AAAAAAAA
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT24C32D
Truncation Code ###: 32D
AT24C64D
Truncation Code ###: 64D
Date Codes
Y = Year
2: 2012
3: 2013
4: 2014
5: 2015
Voltages
6: 2016
7: 2017
8: 2018
9: 2019
M = Month
A: January
B: February
...
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Assembly
Lot Number
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
Trace Code
D: 2.5V min
Grade/Lead Finish Material
P: Automotive/NiPdAu
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
3/13/12
TITLE
Package Mark Contact:
[email protected]
12
24C32-64DAM, AT24C32D and AT24C64D Automotive
Package Marking Information
AT24C32D/64D Automotive [DATASHEET]
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
DRAWING NO.
REV.
24C32-64DAM
B
10.
Ordering Code Details
AT 2 4 C 3 2 D - S S P D - T
Atmel Designator
Shipping Carrier Option
T = Tape and reel
Product Family
Operating Voltage
D = 2.5V to 5.5V
Device Density
32 = 32K
64 = 64K
Device Revision
Package Device Grade or
Wafer/Die Thickness
P = Green, NiPdAu lead finish,
Automotive temperature range
(-40°C to +125°C)
Package Option
SS
X
= JEDEC SOIC
= TSSOP
AT24C32D/64D Automotive [DATASHEET]
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13
11.
Ordering Code Information
11.1
Atmel AT24C32D Ordering Information
Ordering Code
AT24C32D-SSPD-T(1)
AT24C32D-XPD-T
Note:
1.
(1)
Lead Finish
Package
NiPdAu
(Lead-free/Halogen-free)
8S1
8X
Voltage
Operation Range
2.5V to 5.5V
Automotive Temperature
(40C to 125C)
Tape and reel delivery:


SOIC 4k/reel
TSSOP 5k/reel
Package Type
14
8S1
8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X
8-lead, 4.4mm wide, Plastic Thin Shrink Small Outline Package (TSSOP)
AT24C32D/64D Automotive [DATASHEET]
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
11.2
Atmel AT24C64D Ordering Information
Ordering Code
AT24C64D-SSPD-T(1)
AT24C64D-XPD-T
Note:
1.
(1)
Lead Finish
Package
NiPdAu
(Lead-free/Halogen-free)
8S1
8X
Voltage
Operation Range
2.5V to 5.5V
Automotive Temperature
(40C to 125C)
Tape and reel delivery:


SOIC 4k/reel
TSSOP 5k/reel
Package Type
8S1
8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X
8-lead, 4.4mm wide, Plastic Thin Shrink Small Outline Package (TSSOP)
AT24C32D/64D Automotive [DATASHEET]
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15
12.
Packaging Information
12.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
SYMBOL MIN
A
1.35
NOM
MAX
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
6/22/11
Package Drawing Contact:
[email protected]
16
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
AT24C32D/64D Automotive [DATASHEET]
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
GPC
SWB
DRAWING NO.
REV.
8S1
G
12.2
8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
H
N
L
Top View
End View
A
b
A1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
A2
Side View
Notes:
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
SYMBOL
D
1. This drawing is for general information only. Refer to JEDEC
Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion. Allowable
Dambar protrusion shall be 0.08mm total in excess of the b
dimension at maximum material condition. Dambar cannot be
located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
NOTE
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
2, 5
4.40
4.50
3, 5
–
0.30
4
E
6.40 BSC
E1
4.30
b
0.19
e
L
0.65 BSC
0.45
L1
C
0.60
0.75
1.00 REF
0.09
-
0.20
12/8/11
TITLE
Package Drawing Contact:
[email protected]
GPC
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
TNR
DRAWING NO.
8X
AT24C32D/64D Automotive [DATASHEET]
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
REV.
E
17
13.
Revision History
Doc. Rev.
Date
8800C
02/2014
Comments
Remove bulk ordering options, update the Random Read figure, footers, and disclaimer page.
Add AC measurement conditions note to the AC Characteristics table.
Remove preliminary status.
8800B
10/2012
Update 8X — TSSOP package drawing.
Update Atmel logos and dicslaimer/copy page.
8800A
18
03/2012
Initial document release.
AT24C32D/64D Automotive [DATASHEET]
Atmel-8800C-SEEPROM-AT24C32D-64D-Auto-Datasheet_022014
XXXXXX
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