ATtiny828 - Summary

ATtiny828
8-bit AVR Microcontroller with 8K Bytes In-System
Programmable Flash
DATASHEET SUMMARY
Features
z High Performance, Low Power Atmel® AVR® 8-bit Microcontroller
z Advanced RISC Architecture
z
123 Powerful Instructions – Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
z Fully Static Operation
z Up to 20 MIPS Throughput at 20 MHz
z
z Non-volatile Program and Data Memories
z
z
z
z
z
8K Bytes of In-System Programmable Flash Program Memory
z Endurance: 10,000 Write/Erase Cycles
256 Bytes of In-System Programmable EEPROM
z Endurance: 100,000 Write/Erase Cycles
512 Bytes Internal SRAM
Optional Boot Code Section with Independent Lock Bits
Data Retention: 20 Years at 85oC / 100 Years at 25oC
z Peripheral Features
z
z
z
z
z
z
z
One 8-bit and one 16-bit Timer/Counter with Two PWM Channels, Each
Programmable Ultra Low Power Watchdog Timer
On-chip Analog Comparator
10-bit Analog to Digital Converter
z 28 External and 4 Internal, Single-ended Input Channels
Full Duplex USART with Start Frame Detection
Master/Slave SPI Serial Interface
Slave I2C Serial Interface
z Special Microcontroller Features
z
z
z
z
z
z
z
Low Power Idle, ADC Noise Reduction, and Power-down Modes
Enhanced Power-on Reset Circuit
Programmable Brown-out Detection Circuit with Supply Voltage Sampling
External and Internal Interrupt Sources
z Pin Change Interrupt on 28 Pins
Calibrated 8MHz Oscillator with Temperature Calibration Option
Calibrated 32kHz Ultra Low Power Oscillator
High-Current Drive Capability on 8 I/O Pins
z I/O and Packages
z
32-lead TQFP, and 32-pad QFN/MLF: 28 Programmable I/O Lines
z Speed Grade
z
0 – 2 MHz @ 1.7 – 1.8V
0 – 4 MHz @ 1.8 – 5.5V
z 0 – 10 MHz @ 2.7 – 5.5V
z 0 – 20 MHz @ 4.5 – 5.5V
z
8371AS–AVR–08/12
z Low Power Consumption
z
Active Mode: 0.2 mA at 1.8V and 1MHz
Idle Mode: 30 µA at 1.8V and 1MHz
z Power-Down Mode (WDT Enabled): 1 µA at 1.8V
z Power-Down Mode (WDT Disabled): 100 nA at 1.8V
z
Pin Configurations
ATtiny828 Pinout in MLF32.
32
31
30
29
28
27
26
25
PC1 (PCINT17/ADC17/TOCC1/INT0/CLKO)
PC0 (PCINT16/ADC16/TOCC0/SS/XCK)
PD3 (PCINT27/ADC27/SCL/SCK)
PD2 (PCINT26/ADC26/RESET/DW)
PD1 (PCINT25/ADC25/MISO)
PD0 (PCINT24/ADC24/SDA/MOSI)
PB7 (PCINT15/ADC15)
PB6 (PCINT14/ADC14)
Figure 1.
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PB5 (PCINT13/ADC13)
PB4 (PCINT12/ADC12)
PB3 (PCINT11/ADC11)
GND
PB2 (PCINT10/ADC10)
PB1 (PCINT9/ADC9)
AVCC
PB0 (PCINT8/ADC8)
24
23
22
21
20
19
18
17
PB5 (PCINT13/ADC13)
PB4 (PCINT12/ADC12)
PB3 (PCINT11/ADC11)
GND
PB2 (PCINT10/ADC10)
PB1 (PCINT9/ADC9)
AVCC
PB0 (PCINT8/ADC8)
(PCINT0/ADC0) PA0
(PCINT1/ADC1/AIN0) PA1
(PCINT2/ADC2/AIN1) PA2
(PCINT3/ADC3) PA3
(PCINT4/ADC4) PA4
(PCINT5/ADC5) PA5
(PCINT6/ADC6) PA6
(PCINT7/ADC7) PA7
9
10
11
12
13
14
15
16
(PCINT18/ADC18/TOCC2/RXD/INT1) PC2
(PCINT19/ADC19/TOCC3/TXD) PC3
(PCINT20/ADC20/TOCC4) PC4
VCC
GND
(PCINT21/ADC21/TOCC5/ICP1/T0) PC5
(PCINT22/ADC22/CLKI/TOCC6) PC6
(PCINT23/ADC23/TOCC7/T1) PC7
NOTE: Bottom pad should be
soldered to ground
32
31
30
29
28
27
26
25
PC1 (PCINT17/ADC17/TOCC1/INT0/CLKO)
PC0 (PCINT16/ADC16/TOCC0/SS/XCK)
PD3 (PCINT27/ADC27/SCL/SCK)
PD2 (PCINT26/ADC26/RESET/DW)
PD1 (PCINT25/ADC25/MISO)
PD0 (PCINT24/ADC24/SDA/MOSI)
PB7 (PCINT15/ADC15)
PB6 (PCINT14/ADC14)
ATtiny828 Pinout in TQFP32.
(PCINT18/ADC18/TOCC2/RXD/INT1) PC2
(PCINT19/ADC19/TOCC3/TXD) PC3
(PCINT20/ADC20/TOCC4) PC4
VCC
GND
(PCINT21/ADC21/TOCC5/ICP1/T0) PC5
(PCINT22/ADC22/CLKI/TOCC6) PC6
(PCINT23/ADC23/TOCC7/T1) PC7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 2.
(PCINT0/ADC0) PA0
(PCINT1/ADC1/AIN0) PA1
(PCINT2/ADC2/AIN1) PA2
(PCINT3/ADC3) PA3
(PCINT4/ADC4) PA4
(PCINT5/ADC5) PA5
(PCINT6/ADC6) PA6
(PCINT7/ADC7) PA7
1.
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
2
1.1
Pin Description
1.1.1
VCC
Supply voltage.
1.1.2
AVCC
AVCC is the supply voltage pin for the A/D converter and a selection of I/O pins. This pin should be externally connected
to VCC even if the ADC is not used. If the ADC is used, it is recommended this pin is connected to VCC through a low-pass
filter, as described in “Noise Canceling Techniques” on page 145.
All pins of Port A and Port B are powered by AVCC. All other I/O pins take their supply voltage from VCC.
1.1.3
GND
Ground.
1.1.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not
running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 107 on page 250.
Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
1.1.5
Port A (PA7:PA0)
This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have high sink
and standard source capability. See Table 107 on page 250 for port drive strength.
As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternative pin functions for pin change interrupts, the analog comparator, and ADC. See “Alternative Port
Functions” on page 63.
1.1.6
Port B (PB7:PB0)
This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have high sink
and standard source capability. See Table 103 on page 247 for port drive strength.
As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternative pin functions for pin change interrupts, and ADC. See “Alternative Port Functions” on page 63.
1.1.7
Port C (PC7:PC0)
This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have high sink
and standard source capability. Optionally, extra high sink capability can be enabled. See Table 103 on page 247 for port
drive strength.
As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternative pin functions for pin change interrupts, ADC, timer/counter, external interrupts, and serial
interfaces. See “Alternative Port Functions” on page 63.
1.1.8
Port D (PD3:PD0)
This is a 4-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers of PD0 and PD3
have symmetrical drive characteristics, with both sink and source capability. Output buffer PD1 has high sink and
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
3
standard source capability, while PD2 only has weak drive characteristics due to its use as a reset pin. See Table 103 on
page 247 for port drive strength.
As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternative pin functions for pin change interrupts, ADC, serial interfaces, and debugWire. See “Alternative
Port Functions” on page 63.
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
4
2.
Overview
ATtiny828 is a low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the ATtiny828 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
Figure 3.
VCC
Block Diagram
RESET
GND
ON-CHIP
DEBUGGER
POWER
SUPERVISION:
POR
BOD
RESET
EEPROM
CALIBRATED ULP
OSCILLATOR
CALIBRATED
OSCILLATOR
WATCHDOG
TIMER
ISP
INTERFACE
DEBUG
INTERFACE
8-BIT
TIMER/COUNTER
16-BIT
TIMER/COUNTER
TWO-WIRE
INTERFACE
USART
TIMING AND
CONTROL
PROGRAM
MEMORY
DATA
MEMORY
(FLASH)
(SRAM)
TEMPERATURE
SENSOR
CPU CORE
ANALOG
COMPARATOR
MULTIPLEXER
VOLTAGE
REFERENCE
ADC
8-BIT DATA BUS
PORT A
PORT B
PORT C
PORT D
PA[7:0]
PB[7:0]
PC[7:0]
PD[3:0]
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
5
ATtiny828 provides the following features:
z
8K bytes of in-system programmable Flash
z
512 bytes of SRAM data memory
z
256 bytes of EEPROM data memory
z
28 general purpose I/O lines
z
32 general purpose working registers
z
An 8-bit timer/counter with two PWM channels
z
A16-bit timer/counter with two PWM channels
z
Internal and external interrupts
z
A 10-bit ADC with 4 internal and 28 external chanels
z
An ultra-low power, programmable watchdog timer with internal oscillator
z
A programmable USART with start frame detection
z
A slave, I2C compliant Two-Wire Interface (TWI)
z
A master/slave Serial Peripheral Interface (SPI)
z
A calibrated 8MHz oscillator
z
A calibrated 32kHz, ultra low power oscillator
z
Three software selectable power saving modes.
The device includes the following modes for saving power:
z
Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI, TWI, and interrupt
system to continue functioning
z
ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping the CPU and all I/O
modules except the ADC
z
Power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or
hardware reset
The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash program memory can
be re-programmed in-system through a serial interface, by a conventional non-volatile memory programmer or by an onchip boot code, running on the AVR core. The boot program can use any interface to download the application program
to the Flash memory. Software in the boot section of the Flash executes while the application section of the Flash is
updated, providing true read-while-write operation.
The ATtiny828 AVR is supported by a full suite of program and system development tools including: C compilers, macro
assemblers, program debugger/simulators and evaluation kits.
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
6
3.
General Information
3.1
Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for
download at http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code
examples assume that the part specific header file is included before compilation. Be aware that not all C compiler
vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with
the C compiler documentation for more details.
3.3
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years
at 85°C or 100 years at 25°C.
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
7
4.
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0xFF)
Reserved
–
–
–
–
–
–
–
–
(0xFE)
Reserved
–
–
–
–
–
–
–
–
(0xFD)
Reserved
–
–
–
–
–
–
–
–
(0xFC)
Reserved
–
–
–
–
–
–
–
–
(0xFB)
Reserved
–
–
–
–
–
–
–
–
(0xFA)
Reserved
–
–
–
–
–
–
–
–
(0xF9)
Reserved
–
–
–
–
–
–
–
–
(0xF8)
Reserved
–
–
–
–
–
–
–
–
(0xF7)
Reserved
–
–
–
–
–
–
–
–
(0xF6)
Reserved
–
–
–
–
–
–
–
–
(0xF5)
Reserved
–
–
–
–
–
–
–
–
(0xF4)
Reserved
–
–
–
–
–
–
–
–
(0xF3)
Reserved
–
–
–
–
–
–
–
–
(0xF2)
Reserved
–
–
–
–
–
–
–
–
(0xF1)
OSCTCAL0B
Oscillator Temperature Compensation Register B
(0xF0)
OSCTCAL0A
Oscillator Temperature Compensation Register A
(0xEF)
Reserved
–
–
–
–
–
–
–
–
Page(s)
Page 33
Page 33
(0xEE)
Reserved
–
–
–
–
–
–
–
–
(0xED)
Reserved
–
–
–
–
–
–
–
–
(0xEC)
Reserved
–
–
–
–
–
–
–
–
(0xEB)
Reserved
–
–
–
–
–
–
–
–
(0xEA)
Reserved
–
–
–
–
–
–
–
–
(0xE9)
TOCPMSA1
TOCC7S1
TOCC7S0
TOCC6S1
TOCC6S0
TOCC5S1
TOCC5S0
TOCC4S1
TOCC4S0
Page 127
(0xE8)
TOCPMSA0
TOCC3S1
TOCC3S0
TOCC2S1
TOCC2S0
TOCC1S1
TOCC1S0
TOCC0S1
TOCC0S0
Page 127
(0xE7)
Reserved
–
–
–
–
–
–
–
–
(0xE6)
Reserved
–
–
–
–
–
–
–
–
(0xE5)
Reserved
–
–
–
–
–
–
–
–
(0xE4)
Reserved
–
–
–
–
–
–
–
–
(0xE3)
Reserved
–
–
–
–
–
–
–
–
(0xE2)
TOCPMCOE
TOCC7OE
TOCC6OE
TOCC5OE
TOCC4OE
TOCC3OE
TOCC2OE
TOCC1OE
TOCC0OE
(0xE1)
Reserved
–
–
–
–
–
–
–
–
Page 128
(0xE0)
Reserved
–
–
–
–
–
–
–
–
(0xDF)
DIDR3
–
–
–
–
ADC27D
ADC26D
ADC25D
ADC24D
Page 154
(0xDE)
DIDR2
ADC23D
ADC22D
ADC21D
ADC20D
ADC19D
ADC18D
ADC17D
ADC16D
Page 154
(0xDD)
Reserved
–
–
–
–
–
–
–
–
(0xDC)
Reserved
–
–
–
–
–
–
–
–
(0xDB)
Reserved
–
–
–
–
–
–
–
–
(0xDA)
Reserved
–
–
–
–
–
–
–
–
(0xD9)
Reserved
–
–
–
–
–
–
–
–
(0xD8)
Reserved
–
–
–
–
–
–
–
–
(0xD7)
Reserved
–
–
–
–
–
–
–
–
(0xD6)
Reserved
–
–
–
–
–
–
–
–
(0xD5)
Reserved
–
–
–
–
–
–
–
–
(0xD4)
Reserved
–
–
–
–
–
–
–
–
(0xD3)
Reserved
–
–
–
–
–
–
–
–
(0xD2)
Reserved
–
–
–
–
–
–
–
–
(0xD1)
Reserved
–
–
–
–
–
–
–
–
(0xD0)
Reserved
–
–
–
–
–
–
–
–
(0xCF)
Reserved
–
–
–
–
–
–
–
–
(0xCE)
Reserved
–
–
–
–
–
–
–
–
(0xCD)
Reserved
–
–
–
–
–
–
–
–
(0xCC)
Reserved
–
–
–
–
–
–
–
–
(0xCB)
Reserved
–
–
–
–
–
–
–
–
(0xCA)
Reserved
–
–
–
–
–
–
–
–
(0xC9)
Reserved
–
–
–
–
–
–
–
–
(0xC8)
Reserved
–
–
–
–
–
–
–
–
(0xC7)
Reserved
–
–
–
–
–
–
–
–
(0xC6)
UDR
(0xC5)
UBRRH
(0xC4)
UBRRL
USART Data Register
–
–
–
–
Pages 184, 195
USART Baud Register High
Page 189, 198
USART Baud Rate Register Low
Page 189, 198
(0xC3)
UCSRD
RXSIE
RXS
SFDE
–
–
–
–
–
Page 188
(0xC2)
UCSRC
UMSEL1
UMSEL0
UPM1
UPM0
USBS
UCSZ1/UDO
UCSZ0/UCP
UCPOL
Page 186, 197
(0xC1)
UCSRB
RXCIE
TXCIE
UDRIE
RXEN
TXEN
UCSZ2
RXB8
TXB8
Page 185, 196
(0xC0)
UCSRA
RXC
TXC
UDRE
FE
DOR
UPE
U2X
MPCM
Page 184, 196
(0xBF)
Reserved
–
–
–
–
–
–
–
–
(0xBE)
Reserved
–
–
–
–
–
–
–
–
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
8
Address
Name
(0xBD)
TWSD
Bit 7
Bit 6
Bit 5
TWI Slave Data Register
Bit 4
Bit 3
Bit 2
Bit 1
Page 211
(0xBC)
TWSA
TWI Slave Address Register
Page 210
TWI Slave Address Mask Register
Bit 0
Page(s)
(0xBB)
TWSAM
(0xBA)
TWSSRA
TWDIF
TWASIF
TWCH
TWRA
TWC
TWBE
TWDIR
TWAE
TWAS
Page 209
(0xB9)
TWSCRB
–
–
–
–
–
TWAA
TWCMD1
TWCMD0
Page 208
(0xB8)
TWSCRA
TWSHE
–
TWDIE
TWASIE
TWEN
TWSIE
TWPME
TWSME
Page 207
(0xB7)
Reserved
–
–
–
–
–
–
–
–
(0xB6)
Reserved
–
–
–
–
–
–
–
–
(0xB5)
Reserved
–
–
–
–
–
–
–
–
(0xB4)
Reserved
–
–
–
–
–
–
–
–
(0xB3)
Reserved
–
–
–
–
–
–
–
–
(0xB2)
Reserved
–
–
–
–
–
–
–
–
(0xB1)
Reserved
–
–
–
–
–
–
–
–
(0xB0)
Reserved
–
–
–
–
–
–
–
–
(0xAF)
Reserved
–
–
–
–
–
–
–
–
(0xAE)
Reserved
–
–
–
–
–
–
–
–
(0xAD)
Reserved
–
–
–
–
–
–
–
–
(0xAC)
Reserved
–
–
–
–
–
–
–
–
(0xAB)
Reserved
–
–
–
–
–
–
–
–
(0xAA)
Reserved
–
–
–
–
–
–
–
–
(0xA9)
Reserved
–
–
–
–
–
–
–
–
(0xA8)
Reserved
–
–
–
–
–
–
–
–
(0xA7)
Reserved
–
–
–
–
–
–
–
–
(0xA6)
Reserved
–
–
–
–
–
–
–
–
(0xA5)
Reserved
–
–
–
–
–
–
–
–
(0xA4)
Reserved
–
–
–
–
–
–
–
–
(0xA3)
Reserved
–
–
–
–
–
–
–
–
(0xA2)
Reserved
–
–
–
–
–
–
–
–
(0xA1)
Reserved
–
–
–
–
–
–
–
–
(0xA0)
Reserved
–
–
–
–
–
–
–
–
(0x9F)
Reserved
–
–
–
–
–
–
–
–
(0x9E)
Reserved
–
–
–
–
–
–
–
–
(0x9D)
Reserved
–
–
–
–
–
–
–
–
(0x9C)
Reserved
–
–
–
–
–
–
–
–
(0x9B)
Reserved
–
–
–
–
–
–
–
–
(0x9A)
Reserved
–
–
–
–
–
–
–
–
(0x99)
Reserved
–
–
–
–
–
–
–
–
(0x98)
Reserved
–
–
–
–
–
–
–
–
(0x97)
Reserved
–
–
–
–
–
–
–
–
(0x96)
Reserved
–
–
–
–
–
–
–
–
(0x95)
Reserved
–
–
–
–
–
–
–
–
(0x94)
Reserved
–
–
–
–
–
–
–
–
(0x93)
Reserved
–
–
–
–
–
–
–
–
(0x92)
Reserved
–
–
–
–
–
–
–
–
(0x91)
Reserved
–
–
–
–
–
–
–
–
(0x90)
Reserved
–
–
–
–
–
–
–
–
(0x8F)
Reserved
–
–
–
–
–
–
–
–
(0x8E)
Reserved
–
–
–
–
–
–
–
–
(0x8D)
Reserved
–
–
–
–
–
–
–
–
(0x8C)
Reserved
–
–
–
–
–
–
–
–
(0x8B)
OCR1BH
Timer/Counter1 – Output Compare Register B High Byte
Page 128
(0x8A)
OCR1BL
Timer/Counter1 – Output Compare Register B Low Byte
Page 128
(0x89)
OCR1AH
Timer/Counter1 – Output Compare Register A High Byte
Page 128
(0x88)
OCR1AL
Timer/Counter1 – Output Compare Register A Low Byte
Page 128
(0x87)
ICR1H
Timer/Counter1 – Input Capture Register High Byte
Page 129
(0x86)
ICR1L
Timer/Counter1 – Input Capture Register Low Byte
Page 129
(0x85)
TCNT1H
Timer/Counter1 – Counter Register High Byte
Page 128
Timer/Counter1 – Counter Register Low Byte
Page 211
(0x84)
TCNT1L
(0x83)
Reserved
–
–
–
(0x82)
TCCR1C
FOC1A
FOC1B
–
–
–
–
–
–
Page 127
(0x81)
TCCR1B
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
Page 125
(0x80)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
–
–
WGM11
WGM10
Page 123
(0x7F)
DIDR1
ADC15D
ADC14D
ADC13D
ADC12D
ADC11D
ADC10D
ADC9D
ADC8D
Page 154
Pages 136, 154
–
–
Page 128
–
–
–
(0x7E)
DIDR0
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
(0x7D)
ADMUXB
–
–
REFS
–
–
–
–
MUX5
Page 150
(0x7C)
ADMUXA
–
–
–
MUX4
MUX3
MUX2
MUX1
MUX0
Page 149
(0x7B)
ADCSRB
–
–
–
–
ADLAR
ADTS2
ADTS1
ADTS0
Page 153
(0x7A)
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
Page 151
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
9
Address
Name
(0x79)
ADCH
Bit 7
Bit 6
Bit 5
ADC – Conversion Result High Byte
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page(s)
(0x78)
ADCL
ADC – Conversion Result Low Byte
(0x77)
Reserved
–
–
–
–
–
–
–
–
(0x76)
Reserved
–
–
–
–
–
–
–
–
(0x75)
Reserved
–
–
–
–
–
–
–
–
(0x74)
Reserved
–
–
–
–
–
–
–
–
(0x73)
PCMSK3
–
–
–
–
PCINT27
PCINT26
PCINT25
PCINT24
(0x72)
Reserved
–
–
–
–
–
–
–
–
(0x71)
Reserved
–
–
–
–
–
–
–
–
(0x70)
Reserved
–
–
–
–
–
–
–
–
(0x6F)
TIMSK1
–
–
ICIE1
–
–
OCIE1B
OCIE1A
TOIE1
Page 129
(0x6E)
TIMSK0
–
–
–
–
–
OCIE0B
OCIE0A
TOIE0
Page 102
(0x6D)
PCMSK2
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
Page 54
(0x6C)
PCMSK1
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
Page 54
(0x6B)
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
Page 55
(0x6A)
Reserved
–
–
–
–
–
–
–
–
(0x69)
EICRA
–
–
–
–
ISC11
ISC10
ISC01
ISC00
Page 55
(0x68)
PCICR
–
–
–
–
PCIE3
PCIE2
PCIE1
PCIE0
Page 56
Page 151
Page 151
Page 54
(0x67)
OSCCAL1
–
–
–
–
–
–
CAL11
CAL10
Page 33
(0x66)
OSCCAL0
CAL07
CAL06
CAL05
CAL04
CAL03
CAL02
CAL01
CAL00
Page 32
(0x65)
Reserved
–
–
–
–
–
–
–
–
(0x64)
PRR
PRTWI
–
PRTIM0
–
PRTIM1
PRSPI
PRUSART0
PRADC
(0x63)
Reserved
–
–
–
–
–
–
–
–
(0x62)
Reserved
–
–
–
–
–
–
–
–
(0x61)
CLKPR
–
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Page 31
(0x60)
WDTCSR
WDIF
WDIE
WDP3
–
WDE
WDP2
WDP1
WDP0
Page 46
0x3F (0x5F)
SREG
I
T
H
S
V
N
Z
C
Page 15
0x3E (0x5E)
SPH
–
–
–
–
–
–
SP9
SP8
Page 14
0x3D (0x5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
Page 14
0x3C (0x5C)
Reserved
–
–
–
–
–
–
–
–
0x3B (0x5B)
Reserved
–
–
–
–
–
–
–
–
0x3A (0x5A)
Reserved
–
–
–
–
–
–
–
–
0x39 (0x59)
Reserved
–
–
–
–
–
–
–
–
0x38 (0x58)
Reserved
–
–
–
–
–
–
–
–
0x37 (0x57)
SPMCSR
SPMIE
RWWSB
RSIG
RWWSRE
RWFLB
PGWRT
PGERS
SPMEN
Page 223
0x36 (0x56)
CCP
0x35 (0x55)
MCUCR
–
–
–
–
–
–
IVSEL
–
Page 53
0x34 (0x54)
MCUSR
–
–
–
–
WDRF
BORF
EXTRF
PORF
Page 45
0x33 (0x53)
SMCR
–
–
–
–
–
SM1
SM0
SE
Page 37
0x32 (0x52)
Reserved
–
–
–
–
–
–
–
–
ACIE
ACIC
ACIS1
ACIS0
Page 134
ACNMUX1
ACNMUX0
ACPMUX1
ACPMUX0
Page 135
Page 37
CPU Change Protection Register
0x31 (0x51)
DWDR
0x30 (0x50)
ACSRA
ACD
ACPMUX2
ACO
HSEL
HLEV
ACLP
Page 14
debugWire Data Register
ACI
Page 213
0x2F (0x4F)
ACSRB
0x2E (0x4E)
SPDR
0x2D (0x4D)
SPSR
SPIF
WCOL
–
0x2C (0x4C)
SPCR
SPIE
SPE
DORD
0x2B (0x4B)
GPIOR2
General Purpose I/O Register 2
Page 25
0x2A (0x4A)
GPIOR1
General Purpose I/O Register 1
Page 25
0x29 (0x49)
Reserved
0x28 (0x48)
OCR0B
Timer/Counter0 – Output Compare Register B
Page 102
0x27 (0x47)
OCR0A
Timer/Counter0 – Output Compare Register A
Page 102
0x26 (0x46)
TCNT0
Timer/Counter0 – Counter Register
0x25 (0x45)
TCCR0B
FOC0A
FOC0B
–
–
WGM02
CS02
CS01
CS00
SPI Data Register
Page 163
–
–
–
–
SPI2X
Page 162
MSTR
CPOL
CPHA
SPR1
SPR0
Page 161
Page 101
Page 100
0x24 (0x44)
TCCR0A
COM0A1
COM0A0
COM0B1
COM0B0
–
–
WGM01
WGM00
Page 97
0x23 (0x43)
GTCCR
TSM
–
–
–
–
–
–
PSR
Page 132
0x22 (0x42)
Reserved
0x21 (0x41)
EEARL
EEPROM Address Register Low Byte
Page 23
0x20 (0x40)
EEDR
EEPROM Data Register
Page 24
0x1F (0x3F)
EECR
0x1E (0x3E)
GPIOR0
–
–
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
Page 24
0x1D (0x3D)
EIMSK
–
–
–
–
–
INT1
INT0
Page 56
0x1C (0x3C)
EIFR
–
–
–
–
–
–
INT1
INTF0
Page 57
0x1B (0x3B)
PCIFR
–
–
–
–
PCIF3
PCIF2
PCIF1
PCIF0
Page 57
0x1A (0x3A)
Reserved
–
–
–
–
–
–
–
–
0x19 (0x39)
Reserved
–
–
–
–
–
–
–
–
0x18 (0x38)
Reserved
–
–
–
–
–
–
–
–
0x17 (0x37)
Reserved
–
–
–
–
–
–
–
–
0x16 (0x36)
TIFR1
–
–
ICF1
–
–
OCF1B
OCF1A
TOV1
General Purpose I/O register 0
–
Page 26
Page 130
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
10
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page(s)
0x15 (0x35)
TIFR0
–
–
–
–
–
OCF0B
OCF0A
TOV0
Page 103
0x14 (0x34)
PHDE
–
–
–
–
–
PHDEC
–
–
Page 81
0x13 (0x33)
Reserved
–
–
–
–
–
–
–
–
0x12 (0x32)
Reserved
–
–
–
–
–
–
–
–
0x11 (0x31)
Reserved
–
–
–
–
–
–
–
–
0x10 (0x30)
Reserved
–
–
–
–
–
–
–
–
0x0F (0x2F)
PUED
–
–
–
–
PUED3
PUED2
PUED1
PUED0
0x0E (0x2E)
PORTD
–
–
–
–
PORTD3
PORTD2
PORTD1
PORTD0
Page 82
0x0D (0x2D)
DDRD
–
–
–
–
DDD3
DDD2
DDD1
DDD0
Page 82
Page 82
0x0C (0x2C)
PIND
–
–
–
–
PIND3
PIND2
PIND1
PIND0
Page 83
0x0B (0x2B)
PUEC
PUEC7
PUEC6
PUEC5
PUEC4
PUEC3
PUEC2
PUEC1
PUEC0
Page 83
0x0A (0x2A)
PORTC
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
Page 83
0x09 (0x29)
DDRC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
Page 83
0x08 (0x28)
PINC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
Page 84
0x07 (0x27)
PUEB
PUEB7
PUEB6
PUEB5
PUEB4
PUEB3
PUEB2
PUEB1
PUEB0
Page 84
0x06 (0x26)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
Page 84
0x05 (0x25)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
Page 84
0x04 (0x24)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
Page 85
0x03 (0x23)
PUEA
PUEA7
PUEA6
PUEA5
PUEA4
PUEA3
PUEA2
PUEA1
PUEA0
Page 85
0x02 (0x22)
PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
Page 85
0x01 (0x21)
DDRA
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
Page 85
0x00 (0x20)
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
Page 86
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and
SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status
Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
11
5.
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Add with Carry two Registers
Rd ← Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd ← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd ← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd ← Rd - Rr - C
Z,C,N,V,H
1
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd ← Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S
2
1
AND
Rd, Rr
Logical AND Registers
Rd ← Rd • Rr
Z,N,V
ANDI
Rd, K
Logical AND Register and Constant
Rd ← Rd • K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd ← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd ← Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd ← Rd ⊕ Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd ← 0xFF − Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd ← 0x00 − Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd ← Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd ← Rd • (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd ← Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd ← 0xFF
None
1
Relative Jump
PC ← PC + k + 1
None
2
Indirect Jump to (Z)
PC ← Z
None
2
Relative Subroutine Call
PC ← PC + k + 1
None
3
BRANCH INSTRUCTIONS
RJMP
k
IJMP
RCALL
k
ICALL
Indirect Call to (Z)
PC ← Z
None
3
RET
Subroutine Return
PC ← STACK
None
4
RETI
Interrupt Return
PC ← STACK
I
if (Rd = Rr) PC ← PC + 2 or 3
None
4
CPSE
Rd,Rr
Compare, Skip if Equal
1/2/3
CP
Rd,Rr
Compare
Rd − Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd − K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC ← PC + 2 or 3
None
1/2/3
1
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC ← PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC ← PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC ← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC←PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC←PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ← PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ← PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ← PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ← PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ← PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) ← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
12
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ← T
None
1
1
SEC
Set Carry
C←1
C
CLC
Clear Carry
C←0
C
1
SEN
Set Negative Flag
N←1
N
1
CLN
Clear Negative Flag
N←0
N
1
SEZ
Set Zero Flag
Z←1
Z
1
CLZ
Clear Zero Flag
Z←0
Z
1
SEI
Global Interrupt Enable
I←1
I
1
CLI
Global Interrupt Disable
I←0
I
1
1
SES
Set Signed Test Flag
S←1
S
CLS
Clear Signed Test Flag
S←0
S
1
SEV
Set Twos Complement Overflow.
V←1
V
1
CLV
Clear Twos Complement Overflow
V←0
V
1
SET
Set T in SREG
T←1
T
1
CLT
Clear T in SREG
T←0
T
1
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H←1
H←0
H
H
1
1
Rd ← Rr
Rd+1:Rd ← Rr+1:Rr
None
1
None
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
LDI
Rd, K
Load Immediate
Rd ← K
None
1
LD
Rd, X
Load Indirect
Rd ← (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd ← (X), X ← X + 1
None
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X ← X - 1, Rd ← (X)
None
2
LD
Rd, Y
Load Indirect
Rd ← (Y)
None
2
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd ← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y ← Y - 1, Rd ← (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd ← (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd ← (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd ← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z ← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd ← (Z + q)
None
2
2
LDS
Rd, k
Load Direct from SRAM
Rd ← (k)
None
ST
X, Rr
Store Indirect
(X) ← Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) ← Rr, X ← X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X ← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y) ← Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y) ← Rr, Y ← Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y ← Y - 1, (Y) ← Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ← Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z) ← Rr, Z ← Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z ← Z - 1, (Z) ← Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) ← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k) ← Rr
None
2
Load Program Memory
R0 ← (Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd ← (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd ← (Z), Z ← Z+1
None
3
Store Program Memory
(Z) ← R1:R0
None
-
In Port
Rd ← P
None
1
SPM
IN
Rd, P
OUT
P, Rr
Out Port
P ← Rr
None
1
PUSH
Rr
Push Register on Stack
STACK ← Rr
None
2
POP
Rd
Pop Register from Stack
Rd ← STACK
None
2
MCU CONTROL INSTRUCTIONS
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
BREAK
Watchdog Reset
Break
(see specific descr. for WDR/timer)
For On-chip Debug Only
None
None
1
N/A
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
13
6.
Ordering Information
6.1
ATtiny828
Speed (MHz) (1)
Supply Voltage (V) (1)
Temperature Range
Package (2)
Accuracy (3)
Ordering Code (4)
±10%
ATtiny828-AU
±2%
ATtiny828R-AU
±10%
ATtiny828-AUR
±2%
ATtiny828R-AUR
±10%
ATtiny828-MU
±2%
ATtiny828R-MU
±10%
ATtiny828-MUR
±2%
ATtiny828R-MUR
32A
20 MHz
1.7 – 5.5V
Industrial (5)
(-40°C to +85°C)
32M1-A
Notes: 1. For speed vs. supply voltage, see section “Speed” on page 249.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of
Hazardous Substances (RoHS).
3. Indicates accuracy of internal oscillator. See “Accuracy of Calibrated Internal Oscillator” on page 249.
4. Code indicators:
z
U: matte tin
z
R: tape & reel
5. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering
information and minimum quantities.
Package Type
32A
32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
32M1-A
32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm, Quad Flat No-Lead (QFN)
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
14
7.
Packaging Information
7.1
32A
PIN 1 IDENTIFIER
PIN 1
e
B
E1
E
D1
D
C
0°~7°
A1
A2
A
L
COMMON DIMENSIONS
(Unit of measure = mm)
SYMBOL
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
8.75
9.00
9.25
D1
6.90
7.00
7.10
E
8.75
9.00
9.25
E1
6.90
7.00
7.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
2010-10-20
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32A, 32-lead, 7 x 7mm body size, 1.0mm body thickness,
0.8mm lead pitch, thin profile plastic quad flat package (TQFP)
DRAWING NO.
REV.
32A
C
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
15
7.2
32M1-A
D
D1
1
2
3
0
Pin 1 ID
E1
SIDE VIEW
E
TOP VIEW
A3
A2
A1
A
K
0.08 C
P
D2
1
2
3
P
Pin #1 Notch
(0.20 R)
K
e
SYMBOL
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
–
0.02
0.05
A2
–
0.65
1.00
A3
E2
b
COMMON DIMENSIONS
(Unit of Measure = mm)
L
BOTTOM VIEW
0.20 REF
b
0.18
0.23
0.30
D
4.90
5.00
5.10
D1
4.70
4.75
4.80
D2
2.95
3.10
3.25
E
4.90
5.00
5.10
E1
4.70
4.75
4.80
E2
2.95
3.10
3.25
e
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
NOTE
0.50 BSC
L
0.30
0.40
0.50
P
–
–
0.60
12o
0
–
K
0.20
–
–
–
5/25/06
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32M1-A, 32-pad, 5 x 5 x 1.0mm Body, Lead Pitch 0.50mm,
3.10mm Exposed Pad, Micro Lead Frame Package (MLF)
DRAWING NO.
32M1-A
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
REV.
E
16
8.
Errata
The revision letters in this section refer to the revision of the corresponding ATtiny828 device.
8.1
Rev. A
z Port Pin Restrictions When ULP Oscillator Is Disabled
1. Port Pin Restrictions When ULP Oscillator Is Disabled
Port pin PD3 is not guaranteed to perform as a reliable input when the Ultra Low Power (ULP) oscillator is not running. In addition, the pin is pulled down internally when ULP oscillator is disabled. TWI and SPI use may be limited
when ULP is not running since pin PD3 is used by SCL and SCK signals.
Problem Fix / Workaround
The ULP oscillator is automatically activated when required. To use PD3 as an input or clock signal of TWI/SPI,
activate the watchdog timer. The watchdog timer automatically enables the ULP oscillator.
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
17
9.
Revision History
Doc. Rev.
Date
8371A
08/2012
Comments
Initial document release.
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
18
ATtiny828 [DATASHEET]
8371AS–AVR–08/12
19
Atmel Corporation
1600 Technology Drive
Atmel Asia Limited
Unit 01-5 & 16, 19F
Atmel Munich GmbH
Business Campus
Atmel Japan G.K.
16F Shin-Osaki Kangyo Bldg
San Jose, CA 95110
BEA Tower, Millennium City 5
Parkring 4
1-6-4 Osaki, Shinagawa-ku
USA
418 Kwun Tong Roa
D-85748 Garching b. Munich
Tokyo 141-0032
Tel: (+1) (408) 441-0311
Kwun Tong, Kowloon
GERMANY
JAPAN
Fax: (+1) (408) 487-2600
HONG KONG
Tel: (+49) 89-31970-0
Tel: (+81) (3) 6417-0300
www.atmel.com
Tel: (+852) 2245-6100
Fax: (+49) 89-3194621
Fax: (+81) (3) 6417-0370
Fax: (+852) 2722-1369
© 2012 Atmel Corporation. All rights reserved. / Rev.: 8371AS–AVR–08/12
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this
document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES
NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF
INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time
without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in,
automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
Similar pages