Features • Utilizes the ARM7TDMI™ ARM® Thumb® Processor Core • • • • • • • • • • • • • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (In-circuit Emulation) 8K Bytes Internal SRAM Fully-programmable External Bus Interface (EBI) – 128 M Bytes of Maximum External Address Space – 8 Chip Selects – Software Programmable 8-/16-bit External Databus 8-level Priority, Individually Maskable, Vectored Interrupt Controller – 8 External Interrupts, Including a High-priority, Low-latency Interrupt Request 58 Programmable I/O Lines 6-channel 16-bit Timer/Counter – Six External Clock Inputs – Two Multi-purpose I/O Pins per Channel Three USARTs Master/Slave SPI Interface – 8-bit to 16-bit Programmable Data Length – Four External Slave Chip Selects Programmable Watchdog Timer 8-channel 10-bit ADC 2-channel 10-bit DAC Clock Generator with On-chip Main Oscillator and PLL for Multiplication – 3 MHz to 20 MHz Frequency Range Main Oscillator Real-time Clock with On-chip 32 kHz Oscillator – Battery Backup Operation and External Alarm 8-channel Peripheral Data Controller for USARTs and SPIs Advanced Power Management Controller (APMC) – Normal, Wait, Slow, Standby and Power-down Modes IEEE 1149.1 JTAG Boundary-scan on All Digital Pins Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range at VDDCORE = 3.0 V, 85°C 2.7V to 3.6V Core Operating Range 2.7V to 5.5V I/O Operating Range 2.7V to 3.6V Analog Operating Range 1.8V to 3.6V Backup Battery Operating Range 2.7V to 3.6V Oscillator and PLL Operating Range -40°C to +85°C Temperature Range Available in a 176-lead TQFP or 176-ball BGA Package AT91 ARM® Thumb® Microcontroller AT91M55800A Electrical Characteristics Description The AT91M55800A is a member of the Atmel AT91 16-/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The fully-programmable External Bus Interface provides a direct connection to off-chip memory in as fast as one clock cycle for a read or write operation. An eight-level priority vectored interrupt controller in conjunction with the Peripheral Data Controller significantly improve the real-time performance of the device. The device is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with an on-chip SRAM and a wide range of peripheral functions, analog interfaces and low-power oscillators on a monolithic chip, Rev. 1727E–ATARM–01/04 1 the Atmel AT91M55800A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many ultra low-power applications. Absolute Maximum Ratings* Operating Temperature (Industrial).......-40°C to +85°C Storage Temperature............................-60°C to + 150°C Voltage on VDDBU Powered Input Pins with Respect to Ground: ...........................-0.3V to +3.9V Voltage on Any Other Input Pin with Respect to Ground......................... ...-0.3V to +5.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage (VDDCORE, VDDA, VDDPLL and VDDBU) ......................... 3.6V Maximum Operating Voltage (VDDIO) ....................... 5.5V DC Output Current (VDDIO)...................................... 4 mA DC Output Current (VDDBU)..................................... 6 mA 2 AT91M55800A 1727E–ATARM–01/04 AT91M55800A DC Characteristics The following characteristics are applicable to the Operating Temperature range: TA = -40°C to 85°C, unless otherwise specified and are certified for a Junction Temperature up to TJ = 100°C. Table 1. DC Characteristics Symbol Parameter VDDBU DC Supply Backup Battery VDDCORE DC Supply Core VDDPLL Conditions Min Max Units 1.8 3.6 V 2.7 3.6 V DC Supply Oscillator and PLL VDDCORE 3.6 V VDDA DC Supply Analog I/Os VDDCORE 3.6 V VDDIO DC Supply Digital I/Os VDDCORE VDDCORE + 2.0 or 5.5 V NRSTBU and WAKEUP pins -0.3 VIL Input Low-level Voltage 0.3 x VDDBU Other pins -0.3 0.8 VIH Input High-level Voltage 0.7 x VDDBU VDDBU + 0.3 2 VDD + 0.3(1) NRSTBU and WAKEUP pins VOL VOH ILEAK IPULL CIN Other pins Output Low-level Voltage SHDN pin: VDDBU = 3.0V IOL = 0.3 mA(2) 0.4 0.2 SHDN pin: VDDBU = 3.0V IOH = 0.3 mA(2) VDDBU - 0.1 V VDD - 0.4(1) VDD - 0.2(1) Input Leakage Current Input Capacitance V V Other pins: IOH = 4 mA(2) IOH = 0 mA(2 Input Pull-up Current V GNDBU + 0.1 Other pins: IOL = 4 mA(2) IOL = 0 mA(2) Output High-level Voltage Typ 392 Blocks powered by VDDBU, VDDBU = 3.6V, VIN = 0 352 Blocks powered by VDDIO, VDDA and VDDPLL, VDD = 3.6V(1), VIN = 0 280 nA µA 176-TQFP Package 6 pF (1) ISC Notes: VDD = VDDCORE = 3.6V, MCK = 0 Hz TA = 25°C 25 All inputs driven TMS, TDI, TCK, NRST = 1 TA = 85°C 500 Static Current µA 1. VDD is applicable to VDDIO, VDDA and VDDPLL. 2. IO = Output Current. 3 1727E–ATARM–01/04 Power Consumption The values in the following tables are measured values in the operating conditions indicated (i.e., V DDIO = 3.3V, V DDCORE = 3.3V, TA = 25°C) on the AT91EB55 Evaluation Board. They represent the power consumption on the VDDCORE power supply unless otherwise specified. Table 2. Power Consumption Mode Conditions Consumption Fetch in ARM mode out of internal SRAM All peripheral clocks activated 6.55 Fetch in ARM mode out of internal SRAM All peripheral clocks deactivated 4.59 All peripheral clocks activated 3.85 All peripheral clocks deactivated 1.78 Unit Normal mW/MHz Idle Table 3. Power Consumption per Peripheral Peripheral Consumption PIO Controller 0.22 Timer/Counter Channel 0.15 Timer/Counter Block (3 Channels) 0.42 USART 0.40 SPI 0.40 ADC 0.23 DAC 0.29 PLL (1) (2) 2.6 Notes: Unit mW/MHz mW 1. Power consumption on the VDDPLL power supply. 2. With a reference frequency equal to 16 MHz, output frequency of 32 MHz and R = 287Ω, C1 = 680 pF, C2 = 68 pF as loop filter. Table 4. Battery Supply Voltage Consumption Condition VDDBU = 3.0 V Power consumption on the VDDBU Power Supply. Without any capacitor connected to the RTC oscillator pins (XIN32, XOUT32) 4 Consumption Unit 0.9 µA AT91M55800A 1727E–ATARM–01/04 AT91M55800A Thermal and Reliability Considerations Thermal Data In Table 5, the device lifetime is estimated with the MIL-217 standard in the “moderately controlled” environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device Junction Temperature. (For details see the section “Junction Temperature” on page 6.) Note that the user must be extremely cautious with this MTBF calculation: as the MIL217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). The life test results that have been measured are always better than the predicted ones. Table 5. MTBF Versus Junction Temperature Junction Temperature (TJ) (°C) Estimated Lifetime (MTBF) (Year) 100 25 125 14 150 8 175 5 Table 6 summarizes the thermal resistance data related to the package of interest. Table 6. Thermal Resistance Data Symbol Parameter θJA Junction-to-ambient thermal resistance θJC Reliability Data Condition Package Typ TQFP176 21 PBGA176 66 TQFP176 9.2 PBGA176 20.1 Unit Still Air °C/ W Junction-to-case thermal resistance The number of gates and the device die size are provided for the user to calculate reliability data with another standard and/or in another environmental model. Table 7. Reliability Data Parameter Data Unit Number of Logic Gates 524 K gates Number of Memory Gates 400 K gates Device Die Size 29.0 mm2 5 1727E–ATARM–01/04 Junction Temperature The average chip-junction temperature TJ in °C can be obtained from the following: 1. T J = T A + ( P D × θ JA ) 2. T J = T A + ( P D × ( θ HEATSINK + θ JC ) ) Where: • θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 6 on page 5. • θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 6 on page 5. • θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet. • PD = device power consumption (W) estimated from data provided in the section “Power Consumption” on page 4. • TA = ambient temperature (°C). From the first equation, the user can derive the estimated lifetime of the chip and thereby decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chipjunction temperature TJ in °C. 6 AT91M55800A 1727E–ATARM–01/04 AT91M55800A Conditions Timing Results The delays are given as typical values in the following conditions: • VDDIO = 5V • VDDCORE = 3.3V • Ambient Temperature = 25°C • Load Capacitance is 0 pF. • The output level change detection is (0.5 x VDDIO). • The input level is (0.3 x VDDIO) for a low-level detection and is (0.7 x VDDIO) for a high level detection. • The Master Clock (MCK) source is a crystal oscillator connected to the XIN input. The minimum and maximum values given in the AC characteristics tables of this datasheet take into account the process variation and the design. In order to obtain the timing for other conditions, the following equation should be used. t = δ T° × ( ( δ VDDCORE × t DATASHEET ) + ( δ VDDIO × ∑ ( CSIGNAL × δ CSIGNAL ) ) ) where: • δT° is the derating factor in temperature given in Figure 1. • δVDDCORE is the derating factor for the Core Power Supply given in Figure 2 on page 8. • tDATASHEET is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pF. • δVDDIO is the derating factor for the IO Power Supply given in Figure 3 on page 9. • CSIGNAL is the capacitance load on the considered output pin. (1) • δCSIGNAL is the load derating factor depending on the capacitance load on the related output pins given in Min and Max in this datasheet. The input delays are given as typical values. Note: 1. The user must take into account the package capacitance load contribution (CIN) described in Table 1 on page 3. 7 1727E–ATARM–01/04 Temperature Derating Factor Figure 1. Derating Curve for Different Operating Temperatures 1.3 1.2 1.1 1 0.9 Typ Case Derating Factor is 1 0.8 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Operating Temperature (°C) Core Voltage Derating Factor Figure 2. Derating Curve for Different Core Supply Voltages 3 Derating Factor 2.5 Typ Case Derating Factor is 1 2 1.5 1 0.5 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 Core Supply Voltage (V) 8 AT91M55800A 1727E–ATARM–01/04 AT91M55800A IO Voltage Derating Factor Figure 3. Derating Curve for Different IO Supply Voltages 1.55 1.50 1.45 Typ Case Derating Factor is 1 Derating Factor 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 IO Supply Voltage (V) Note: The derating factor in this example is applicable only to timings related to output pins. 9 1727E–ATARM–01/04 Crystal Oscillator Characteristics Table 8. RTC Oscillator Characteristics Symbol Parameter 1/(tCPRTC) Crystal Oscillator Frequency CL1, CL2 Internal Load Capacitance (CL1 = CL2) CL Equivalent Load Capacitance CL1 = CL2 = 12 pF Duty Cycle Measured at the MCKO output pin Startup Time tST Conditions Min 45 Typ Max Unit 32.768 KHz 12 pF 6 pF 50 55 % Without any additional load capacitance and an ESR Max = 50 kΩ 300 ms With 13 pF external capacitor per pin and an ESR Max = 50 kΩ 700 ms Table 9. Main Oscillator Characteristics Symbol Parameter 1/(tCPMAIN) Crystal Oscillator Frequency CL1, CL2 Internal Load Capacitance (CL1 = CL2) CL Equivalent Load Capacitance Conditions Notes: 10 Startup Time Typ Max Unit 3 16 20 MHz CL1 = CL2 = 25 pF Duty Cycle tST Min 45 25 pF 12.5 pF 50 55 % With 10 pF external capacitor per pin and a 3 MHz crystal (1) 13 ms With 10 pF external capacitor per pin and a 8 MHz crystal (2) 4.2 ms With 10 pF external capacitor per pin and a 16 MHz crystal (3) 1.4 ms With 10 pF external capacitor per pin and a 20 MHz crystal (3) 1 ms 1. With ESR (Electrical Serie Resistor) maximum equal to 200 Ω, CS maximum = 3 pF. 2. With ESR maximum equal to 100 Ω, CS maximum = 7 pF. 3. With ESR maximum equal to 50 Ω, CS maximum = 7 pF. AT91M55800A 1727E–ATARM–01/04 AT91M55800A Clock Waveforms Table 10. Master Clock Waveform Parameters Symbol Parameter Conditions Min Max Units 1/(tCPMCK) Master Clock Frequency 41.8 MHz tCPMCK Master Clock Period tCHMCK Master Clock High Half-period 0.45 x tCPMCK 0.55 x tCPMCK ns tCLMCK Master Clock Low Half-period 0.45 x tCPMCK 0.55 x tCPMCK ns 23.9 ns Table 11. Clock Propagation Times Symbol Parameter tCDLH (1) MCK Rising to MCKO Rising Edge tCDHL (1) MCK Falling to MCKO Falling Edge Note: Conditions Min Max Units CMCKO = 0 pF 7.5 11.7 ns 0.053 0.083 ns/pF 7.7 12.1 ns 0.059 0.092 ns/pF CMCKO derating CMCKO = 0 pF CMCKO derating 1. Applicable only when MCKO outputs Master Clock. Figure 4. Clock Waveform tCLMCK MCK tCHMCK tCPMCK 0.5 VDDIO MCKO 0.5 VDDIO tCDLH tCDHL 11 1727E–ATARM–01/04 APMC Characteristics Table 12. Master Clock Source Switch Times MCK Source Switch Time From To Min Typ RTC Oscillator Output PLL Output PLL Output RTC Oscillator Output Main Oscillator Output PLL Output 5 x tCPRTC + 3 x tCPPLL PLL Output Main Oscillator Output 4 x tCPRTC + 3 x tCPMAIN RTC Oscillator Output Main Oscillator Output 3 x tCPRTC + 3 x tCPMAIN Main Oscillator Output RTC Oscillator Output 5 x tCPRTC PLL Output Freq. 1 PLL Output Freq. 2 Max 4 x tCPRTC + 3 x tCPPLL 5 x tCPRTC 7 x tCPRTC + 3 x tCPPLL2 Backup Battery Reset Signal Internally to the device, the NRSTBU signal is maintained low for RSTBU1 time after the rising edge of the external signal. Therefore, the NRSTBU signal needs to be asserted only during the VDDBU power ramp up by the user. This feature covers the requirement of an NRSTBU signal assertion of 10(tCPRTC) at a minimum at VDDBU power up. Table 13. Backup Battery Reset Signal Internal Assertion Delay Symbol Parameter RSTBU1 NRSTBU Internal Assertion Delay Typical Internal Delay Units 1 s Figure 5. NRSTBU Assertion Sequence VDDBU VDDBU 0V RTC Oscillator Output MCKO (1) External Signal NRSTBU RSTBU1 Internal Signal Note: 12 1. The MCKO Signal is certified to be valid at the NRSTBU Internal Signal rising edge. AT91M55800A 1727E–ATARM–01/04 AT91M55800A Wake Up Signal Table 14. Wake Up Minimum Pulse Width Symbol Parameter WK1 Wake Up Minimum Pulse Width Min Pulse Width Units 46 µs Figure 6. Wake Up Signal Wake Up WK1 13 1727E–ATARM–01/04 Analog Characteristics ADC Table 15. Channel Conversion Time Relative to ADC Clock Parameter Min Typ Channel Conversion Time Max Units 11 ADC Clock Frequency cycle 800 kHz Table 16. External Voltage Reference Input Symbol VREF Parameter Min Max Units ADVREF Input Voltage Range 2.4 VDDA V ADVREF Input Resistance 12 24 kΩ Typ Max Units 0 VREF V -0.1 0.1 µA 30 pF Max Units Table 17. Analog Inputs Parameter Min Input Voltage Range Input Leakage Current Input Capacitance Table 18. Dynamic Performance Parameter Conditions Min Signal-to-noise Ratio dB Total Harmonic Distortion dB Inter-modulation Distortion dB Channel-to-Channel Isolation dB Table 19. Transfer Characteristics Parameter Conditions Min Resolution Integral Non-linearity 14 VDDA = 3.3V ±10%, ADVREF = VDDA Max Units 10 Bit ADC Clock = 500 kHz ±3 ADC Clock = 800 kHz ±4 LSB AT91M55800A 1727E–ATARM–01/04 AT91M55800A Table 19. Transfer Characteristics Parameter Conditions Differential Non-linearity VDDA = 3.3V ±10%, ADVREF = VDDA Min Max ADC Clock = 500 kHz ±2 ADC Clock = 800 kHz ±4 Units LSB Offset Error ±2 LSB Gain Error ±4 LSB DAC Table 20. DAC Timing Characteristics Parameter Conditions Channel Setting Time 0.85V to 1.85V or 1.85V to 0.85V Min Max Units 6 µs Table 21. External Voltage Reference Input Symbol Parameter Min Max Units VREF DAVREF Input Voltage Range 2.4 VDDA V DAVREF Input Resistance 12 24 kΩ Min Max Units 0 VREF V Input Offset Voltage 10 mV Output Source Current 5 mA Output Sink Current 5 mA Table 22. Output Op Amp Characteristics Parameter Conditions Output Voltage Range Slew Rate Rise or Fall 0.2 V/µs Startup Time Load = 50 pF /10 kΩ (in parallel) 100 µs Overshoot 100 mV@ vcm 20 % Max Units TBD dB Table 23. Dynamic Performance Parameter Total Harmonic Distortion Conditions Min 15 1727E–ATARM–01/04 Table 24. Transfer Characteristics Parameter Conditions Resolution 16 Min Max Units 10 Bit Integral Non-linearity VDDA = 3.3V ±10%, DAVREF > 2.4V 4 LSB Differential Non-linearity VDDA = 3.3V ±10%, DAVREF > 2.4V 4 LSB Offset Error 2 LSB Gain Error 4 LSB AT91M55800A 1727E–ATARM–01/04 AT91M55800A AC Characteristics EBI Signals Relative to MCK The following tables show timings relative to operating condition limits defined in the section “Timing Results” on page 7 Table 25. General-purpose EBI Signals Symbol Parameter Conditions Min Max Units EBI1 MCK Falling to NUB Valid CNUB = 0 pF 8.9 17 ns 0.053 0.092 ns/pF EBI2 MCK Falling to NLB/A0 Valid 8.3 14.8 ns 0.053 0.092 ns/pF EBI3 MCK Falling to A1 - A23 Valid 8 15.2 ns 0.053 0.092 ns/pF EBI4 MCK Falling to Chip Select Change 8.2 15.6 ns 0.053 0.092 ns/pF EBI5 NWAIT Setup before MCK Rising -0.4 ns EBI6 NWAIT Hold after MCK Rising 5.9 ns CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating 17 1727E–ATARM–01/04 . Table 26. EBI Write Signals Symbol Parameter Conditions Min Max Units MCK Rising to NWR Active (No Wait States) CNWR = 0 pF 8.2 13 ns EBI7 0.059 0.092 ns/pF MCK Rising to NWR Active (Wait States) 9 14.1 ns EBI8 0.059 0.092 ns/pF MCK Falling to NWR Inactive (No Wait States) 8.6 13.5 ns EBI9 0.053 0.083 ns/pF MCK Rising to NWR Inactive (Wait States) 8.9 13.9 ns EBI10 0.053 0.083 ns/pF 8.3 15.4 ns EBI11 MCK Rising to D0 - D15 Out Valid 0 0.086 ns/pF 4.8 9.6 ns EBI12 NWR High to NUB Change 0.053 0.092 ns/pF 4.6 7.4 ns EBI13 NWR High to NLB/A0 Change 0.059 0.092 ns/pF 4.4 8.1 ns EBI14 NWR High to A1 - A23 Change 0.059 0.092 ns/pF 4.4 8.6 ns 0.053 0.083 ns/pF EBI15 CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CDATA = 0 pF CDATA derating CNUB = 0 pF CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD = derating NWR High to Chip Select Inactive CNCS = 0 pF CNCS derating C = 0 pF EBI16 Data Out Valid before NWR High (No Wait States) (1) tCHMCK - 1.9 ns CDATA derating - 0.086 ns/pF CNWR derating 0.083 ns/pF n x tCPMCK - 1.5 (2) ns CDATA derating -0.086 ns/pF CNWR derating 0.083 ns/pF 4.4 ns tCHMCK + 0.3 ns C = 0 pF EBI17 Data Out Valid before NWR High (Wait States) (1) EBI18 Data Out Valid after NWR High EBI19 NWR Minimum Pulse Width (No Wait States) (1) EBI20 Notes: 18 NWR Minimum Pulse Width (Wait States) (1) CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating -0.009 n x tCPMCK - 0.2 -0.009 ns/pF (2) ns ns/pF 1. The derating factor is not to be applied to tCHMCK or tCPMCK. 2. n = number of standard wait states inserted. AT91M55800A 1727E–ATARM–01/04 AT91M55800A Table 27. EBI Read Signals Symbol Parameter Conditions Min Max Units EBI21 MCK Falling to NRD Active (1) CNRD = 0 pF 8.5 14.5 ns 0.059 0.092 ns/pF EBI22 MCK Rising to NRD Active (2) 7.7 14.2 ns 0.059 0.092 ns/pF EBI23 MCK Falling to NRD Inactive (1) 8.3 14.5 ns 0.053 0.083 ns/pF EBI24 MCK Falling to NRD Inactive (2) 7.9 12.4 ns 0.053 0.083 ns/pF EBI25 D0-D15 in Setup before MCK Falling (5) -2.2 ns EBI26 D0-D15 in Hold after MCK Falling (5) 6.8 ns EBI27 NRD High to NUB Change EBI28 NRD High to NLB/A0 Change EBI29 NRD High to A1-A23 Change EBI30 NRD High to Chip Select Inactive EBI31 Data Setup before NRD High (5) EBI32 Data Hold after NRD High (5) CNRD derating CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating CNUB = 0 pF CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating EBI33 NRD Minimum Pulse Width (1) (3) EBI34 (2) (3) CNRD = 0 pF CNRD derating CNRD = 0 pF NRD Minimum Pulse Width CNRD derating Notes: 1. 2. 3. 4. 5. 5 9.6 ns 0.053 0.092 ns/pF 4.7 7.4 ns 0.059 0.092 ns/pF 4.5 8 ns 0.059 0.092 ns/pF 4.4 8.5 ns 0.053 0.083 ns/pF 11 ns 0.083 ns/pF -3.6 ns -0.053 (n +1) x tCPMCK - 1.5 ns/pF (4) ns -0.009 ns/pF n x tCPMCK + (tCHMCK - 1.7)(4) ns -0.009 ns/pF Early Read Protocol. Standard Read Protocol. The derating factor is not to be applied to tCHMCK or tCPMCK. n =number of standard Wait States inserted. Only one of these two timings needs to be met. 19 1727E–ATARM–01/04 Table 28. EBI Read and Write Control Signals. Capacitance Limitation Symbol Parameter TCPLNRD(1) Master Clock Low Due to NRD Capacitance TCPLNWR(2) Master CLock Low Due to NWR Capacitance Notes: 20 Conditions Min Max Units CNRD = 0 pF 11.2 ns CNRD derating 0.083 ns/pF CNWR = 0 pF 10.3 ns CNWR derating 0.083 ns/pF 1. If this condition is not met, the action depends on the read protocol intended for use. • Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle. • Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state. 2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be programmed. AT91M55800A 1727E–ATARM–01/04 AT91M55800A Figure 7. EBI Signals Relative to MCK MCK EBI4 EBI4 NCS EBI3 A1 - A23 EBI5 EBI6 NWAIT EBI1/EBI2 NUB/NLB/A0 EBI21 EBI23 EBI33 EBI27-30 NRD(1) EBI22 NRD(2) EBI31 EBI24 EBI34 EBI32 EBI25 EBI26 D0 - D15 Read EBI9 EBI7 EBI12-15 EBI19 NWR (No Wait States) EBI8 EBI10 EBI20 NWR (Wait States) EBI17 EBI11 EBI16 EBI18 EBI18 D0 - D15 to Write No Wait Notes: Wait 1. Early Read Protocol. 2. Standard Read Protocol. 21 1727E–ATARM–01/04 Peripheral Signals USART Signals The inputs must meet the minimum pulse width and period constraints shown in Table 29 and Table 30, and represented in Figure 8. Table 29. USART Input Minimum Pulse Width Symbol Parameter US1 SCK/RXD Minimum Pulse Width Min Pulse Width Units 5(tCPMCK/2) ns Min Input Period Units 9(tCPMCK/2) ns Table 30. USART Minimum Input Period Symbol Parameter US2 SCK Minimum Input Period Figure 8. USART Signals US1 RXD US2 US1 SCK 22 AT91M55800A 1727E–ATARM–01/04 AT91M55800A SPI Signals The inputs must meet the minimum pulse width and period constraints shown in Table 31 and Table 32 and as represented in Figure 9. Table 31. SPI Input Minimum Pulse Width Symbol Parameter SPI1 SPK/MISO/MOSI/NSS Minimum Pulse Width Min Pulse Width Units 3(tCPMCK/2) ns Min Input Period Units 5(tCPMCK/2) ns Table 32. SPI Minimum Input Period Symbol Parameter SPI2 SPCK Minimum Input Period Figure 9. SPI Signals SPI1 SPCK/MISO/ MOSI/NSS SPI2 SPI1 SPCK 23 1727E–ATARM–01/04 Timer/Counter Signals Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event. This delay is 3(tCPMCK) in Waveform Event Detection mode and 4(tCPMCK) in Waveform Total-count Detection mode. The inputs must meet the minimum pulse width and minimum input period shown in Table 33 and Table 34, and as represented in Figure 10. Table 33. Timer Input Minimum Pulse Width Symbol Parameter TC1 TCLK/TIOA/TIOB Minimum Pulse Width Min Pulse Width Units 3(tCPMCK/2) ns Min Input Period Units 5(tCPMCK/2) ns Table 34. Timer Input Minimum Period Symbol TC2 Parameter TCLK/TIOA/TIOB Minimum Input Period Figure 10. Timer Input TC2 3(tCPMCK/2) 3(tCPMCK/2) MCK TC1 TIOA/ TIOB/ TCLK Reset Signals A minimum pulse width is necessary, as shown in Table 35 and as represented in Figure 11. Table 35. Reset Minimum Pulse Width Symbol Parameter RST1 NRST Minimum Pulse Width Min Pulse Width Units 310 µs Figure 11. Reset Signal RST1 NRST Only the NRST rising edge is synchronized with MCK. The falling edge is asynchronous. 24 AT91M55800A 1727E–ATARM–01/04 AT91M55800A Advanced Interrupt Controller Signals Inputs must meet the minimum pulse width and minimum input period shown in Table 36 and Table 37, and represented in Figure 12. Table 36. AIC Input Minimum Pulse Width Symbol Parameter AIC1 FIQ/IRQ[6:0] Minimum Pulse Width Min Pulse Width Units 3(tCPMCK/2) ns Min Input Period Units 5(tCPMCK/2) ns Table 37. AIC Input Minimum Period Symbol Parameter AIC2 AIC Minimum Input Period Figure 12. AIC Signals AIC2 MCK AIC1 FIQ/IRQ [6:0]Input Parallel I/O Signals The inputs must meet the minimum pulse width shown in Table 38 and represented in Figure 13. Table 38. PIO Input Minimum Pulse Width Symbol Parameter PIO1 PIO Input Minimum Pulse Width Min Pulse Width Units 3(tCPMCK/2) ns Figure 13. PIO Signal PIO1 PIO Inputs 25 1727E–ATARM–01/04 ICE Interface Signals Table 39. ICE Interface Timing Specifications Symbo l Parameter ICE0 NTRST Minimum Pulse Width 19.3 ns ICE1 NTRST High Recovery to TCK High 0.4 ns ICE2 NTRST High Removal from TCK High 0.5 ns ICE3 TCK Low Half-period 42.3 ns ICE4 TCK High Half-period 40.3 ns ICE5 TCK Period 82.5 ns ICE6 TDI, TMS, Setup before TCK High 0.9 ns ICE7 TDI, TMS, Hold after TCK High 0.7 ns 6.4 ns ICE8 TDO Hold Time 0 ns/pF ICE9 TCK Low to TDO Valid Conditions Min CTDO = 0 pF CTDO derating CTDO = 0 pF CTDO derating Max Units 14 ns 0.092 ns/pF Figure 14. ICE Interface Signal ICE0 NTRST ICE1 ICE2 ICE5 TCK ICE3 ICE4 TMS/TDI ICE6 ICE7 TDO ICE8 ICE9 26 AT91M55800A 1727E–ATARM–01/04 AT91M55800A JTAG Interface Signals Table 40. JTAG Interface Timing Specifications Symbo l Parameter JTAG0 NTRST Minimum Pulse Width 19.3 ns JTAG1 NTRST High Recovery to TCK Toggle -0.1 ns JTAG2 NTRST High Removal from TCK Toggle 2.7 ns JTAG3 TCK Low Half-period 10.9 ns JTAG4 TCK High Half-period 3 ns JTAG5 TCK Period 13.8 ns JTAG6 TDI, TMS Setup before TCK High 1.5 ns JTAG7 TDI, TMS Hold after TCK High 1.9 ns 3.8 ns JTAG8 TDO Hold Time 0 ns/pF Conditions CTDO = 0 pF CTDO derating Min CTDO = 0 pF Max Units 8.5 ns 0.086 ns/pF JTAG9 TCK Low to TDO Valid JTAG10 Device Inputs Setup Time -0.4 ns JTAG11 Device Inputs Hold Time 3.4 ns 5.3 ns 0 ns/pF CTDO derating COUT = 0 pF JTAG12 JTAG13 Device Outputs Hold Time TCK to Device Outputs Valid COUT derating COUT = 0 pF 12.6 ns COUT derating 0.086 ns/pF 27 1727E–ATARM–01/04 Figure 15. JTAG Interface Signal JTAG0 NTRST JTAG1 JTAG2 JTAG5 TCK JTAG3 JTAG4 TMS/TDI JTAG6 JTAG7 JTAG10 JTAG11 TDO JTAG8 JTAG9 Device Inputs Device Outputs JTAG12 JTAG13 28 AT91M55800A 1727E–ATARM–01/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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