AT25F4096 - Mature

Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet describes Mode 0 Operation
• 33 MHz Clock Rate
• Byte Mode and 256-byte Page Mode for Program Operations
• Sector Architecture:
•
•
•
•
•
•
•
•
•
– Eight Sectors with 64K Bytes Each (4M)
– 256 Pages per Sector
Product Identification Mode
Low-voltage Operation
– 2.7 (VCC = 2.7V to 3.6V)
Sector Write Protection
– Protect 1/8, 1/4, 1/2 or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
Self-timed Program Cycle (30 µs/Byte Typical)
Self-timed Sector Erase Cycle (1 second/Sector Typical)
Single Cycle Reprogramming (Erase and Program) for Status Register
High Reliability
– Endurance: 10,000 Write Cycles Typical
– Data Retention: 20 Years
8-lead EIAJ SOIC and 8-lead Small Array Package (SAP)
4Mbit High
Speed SPI
Serial Flash
Memory
4M (524,288 x 8)
AT25F4096
Description
The AT25F4096 provides 4,194,304 bits of serial reprogrammable Flash memory
organized as 524,288 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT25F4096 is available in a space-saving 8-lead EIAJ SOIC and 8lead SAP packages.
Table 1. Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial
Input
8-lead EIAJ SOIC
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-lead SAP
___
VCC 8
_____
HOLD 7
SCK 6
SI 5
1
2
3
4
CS
SO
___
WP
GND
Bottom View
2454G–SFLSH–5/06
The AT25F4096 is enabled through the Chip Select pin (CS) and accessed via a 3-wire
interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK). All write cycles are completely self-timed.
Block Write protection for top 1/8, top 1/4, top 1/2 or the entire memory array is enabled
by programming the status register. Separate write enable and write disable instructions
are provided for additional data protection. Hardware data protection is provided via the
WP pin to protect against inadvertent write attempts to the status register. The HOLD
pin may be used to suspend any serial communication without resetting the serial
sequence.
Absolute Maximum Ratings*
Operating Temperature....................................–40°C to +85°C
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +5.0V
Maximum Operating Voltage ............................................ 4.2V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
524,288 x 8
2
AT25F4096
2454G–SFLSH–5/06
AT25F4096
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +3.6V (unless otherwise noted)
Symbol
Test Conditions
COUT
Output Capacitance (SO)
CIN
Note:
Max
Units
Conditions
8
pF
VOUT = 0V
6
pF
VIN = 0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics (Preliminary – Subject to Change)
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +2.7V to +3.6V,
TAC = 0°C to +70°C, VCC = +2.7V to +3.6V (unless otherwise noted)
Symbol
Parameter
Max
Units
VCC
Supply Voltage
3.6
V
ICC1
Supply Current
VCC = 3.6V at 33 MHz, SO = Open Read
10.0
17.0
mA
ICC2
Supply Current
VCC = 3.6V at 33 MHz, SO = Open Write
15.0
45.0
mA
ISB
Standby Current
VCC = 2.7V, CS = VCC
2.0
10.0
µA
IIL
Input Leakage
VIN = 0V to VCC
-3.0
3.0
µA
IOL
Output Leakage
VIN = 0V to VCC, TAC = 0°C to 70°C
-3.0
3.0
µA
VIL(1)
Input Low Voltage
-0.6
VCC x 0.3
V
VIH(1)
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output Low Voltage
0.2
V
VOH
Output High Voltage
Note:
Test Condition
Min
Typ
2.7
2.7V ≤ VCC ≤ 3.6V
IOL = 0.15 mA
IOH = -100 µA
VCC - 0.2
V
1. VIL and VIH max are reference only and are not tested.
3
2454G–SFLSH–5/06
Table 4. AC Characteristics (Preliminary – Subject to Change)
Applicable over recommended operating range from TA = –40°C to +85°C, VCC = +2.7V to +3.6V
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
fSCK
SCK Clock Frequency
tRI
Max
Units
33
MHz
Input Rise Time
20
ns
tFI
Input Fall Time
20
ns
tWH
SCK High Time
9
ns
tWL
SCK Low Time
9
ns
tCS
CS High Time
25
ns
tCSS
CS Setup Time
25
ns
tCSH
CS Hold Time
10
ns
tSU
Data In Setup Time
5
ns
tH
Data In Hold Time
5
ns
tHD
Hold Setup Time
15
ns
tCD
Hold Hold Time
15
ns
tV
Output Valid
tHO
Output Hold Time
tLZ
Hold to Output Low Z
200
ns
tHZ
Hold to Output High Z
200
ns
tDIS
Output Disable Time
100
ns
tEC
Erase Cycle Time per Sector
1.0
s
tSR
Status Register Write Cycle Time
40
100
ms
30
50
µs
tBPC
Byte Program Cycle Time
(2)
Endurance
Notes:
4
Min
Typ
0
8
0
(1)
ns
ns
10K
Write Cycles(3)
1. The programming time for n bytes will be equal to n x tBPC.
2. This parameter is ensured by characterization at 3.0V, 25°C only.
3. One write cycle consists of erasing a sector, followed by programming the same sector.
AT25F4096
2454G–SFLSH–5/06
AT25F4096
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25F4096 always
operates as a slave.
TRANSMITTER/RECEIVER: The AT25F4096 has separate pins designated for data
transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25F4096, and the serial output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25F4096 is selected when the CS pin is low. When the device is
not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will
remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25F4096.
When the device is selected and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device without resetting the serial
sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT: The 25F4096 has a write lockout feature that can be activated by
asserting the write protect pin (WP). When the lockout feature is activated, locked-out
sectors will be READ only. The write protect pin will allow normal read/write operations
when held high. When the WP is brought low and WPEN bit is “1”, all write operations to
the status register are inhibited. WP going low while CS is still low will interrupt a write to
the status register. If the internal status register write cycle has already been initiated,
WP going low will have no effect on any write operation to the status register. The WP
pin function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25F4096 in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to “1”.
5
2454G–SFLSH–5/06
Figure 2. SPI Serial Interface
MASTER:
MICROCONTROLLER
DATA OUT (MOSI)
DATA IN (MISO)
SERIAL CLOCK (SPI CK)
SS0
SS1
SS2
SS3
SLAVE:
AT25F4096
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
6
AT25F4096
2454G–SFLSH–5/06
AT25F4096
Functional
Description
The AT25F4096 is designed to interface directly with the synchronous serial peripheral
interface (SPI) of the 6800 type series of microcontrollers.
The AT25F4096 utilizes an 8-bit instruction register. The list of instructions and their
operation codes are contained in Table 5. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low transition.
Write is defined as program and/or erase in this specification. The following commands,
Program, Sector Erase, Chip Erase, and WRSR are write instructions for AT25F4096.
Table 5. Instruction Set for the AT25F4096
Instruction Name
Instruction
Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
PROGRAM
0000 X010
Program Data Into Memory Array
SECTOR ERASE
0101 X010
Erase One Sector in Memory Array
CHIP ERASE
0110 X010
Erase All Sectors in Memory Array
RDID
0001 X101
Read Manufacturer and Product ID
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC
is applied. All write instructions must therefore be preceded by the WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI
instruction disables all write commands. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the status register. The Ready/Busy and Write Enable status of the device can be determined
by the RDSR instruction. Similarly, the block write protection bits indicate the extent of
protection employed. These bits are set by using the WRSR instruction. During internal
write cycles, all other commands will be ignored except the RDSR instruction.
Table 6. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
BP2
BP1
BP0
WEN
RDY
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2454G–SFLSH–5/06
Table 7. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the
write cycle is in progress.
Bit 1 (WEN)
Bit 1 = “0” indicates the device is not WRITE ENABLED. Bit 1 = “1”
indicates the device is WRITE ENABLED.
Bit 2 (BP0)
See Table 8.
Bit 3 (BP1)
See Table 8.
Bit 4 (BP2)
See Table 8.
Bits 5-6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 9.
Bits 0-7 are 1s during an internal write cycle.
READ PRODUCT ID (RDID): The RDID instruction allows the user to read the manufacturer and product ID of the device. The first byte after the instruction will be the
manufacturer code (1FH = ATMEL), followed by the device code 64H.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of five levels of protection for the AT25F4096. The AT25F4096 is divided into eight
sectors where the top 1/8, top quarter (1/4), top half (1/2), or all of the memory sectors
can be protected (locked out) from write. Any of the locked-out sectors will therefore be
read only. The locked-out sector and the corresponding status register control bits are
shown in Table 8 on page 8.
The four bits, BP0, BP1, BP2 and WPEN, are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, tWC, RDSR).
Table 8. Block Write Protect Bits
Status Register Bits
AT25F4096
BP2
BP1
BP0
Array Addresses
Locked Out
Locked-out Sector(s)
0(none)
0
0
0
None
None
1(1/8)
0
0
1
070000 - 07FFFF
Sector 8
2(1/4)
0
1
0
060000 - 07FFFF
Sector 7, 8
3(1/2)
0
1
1
040000 - 07FFFF
Sector 5, 6, 7, 8
4(all)
1
x
x
000000 - 07FFFF
All sectors
(1 - 8)
Level
Note:
1. x = don’t care
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the write protect enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hardware write protected, writes to the status register, including the block protect bits and the
WPEN bit, and the locked-out sectors in the memory array are disabled. Write is only
allowed to sectors of the memory which are not locked out. The WRSR instruction is
self-timed to automatically erase and program BP0, BP1, BP2 and WPEN bits. In order
8
AT25F4096
2454G–SFLSH–5/06
AT25F4096
to write the status register, the device must first be write enabled via the WREN instruction. Then, the instruction and data for the four bits are entered. During the internal write
cycle, all instructions will be ignored except RDSR instructions. The AT25F4096 will
automatically return to write disable state at the completion of the WRSR cycle.
Note:
When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as
long as the WP pin is held low.
Table 9. WPEN Operation
WPEN
WP
WEN
ProtectedBlocks
UnprotectedBlocks
Status Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
READ (READ): Reading the AT25F4096 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a device, the Read instruction
is transmitted via the SI line followed by the byte address to be read (Refer to Table 10).
Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The Read instruction can be continued since the byte address is automatically incremented and data will continue to be
shifted out of the AT25F4096 until the highest address is reached, the address counter
will roll over to the lowest address allowing the entire memory to be read in one continuous Read instruction.
PROGRAM (PROGRAM): In order to program the AT25F4096, two separate instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then the Program instruction can be executed. Also, the address of the
memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal self-timed
programming cycle, all commands will be ignored except the RDSR instruction.
The Program instruction requires the following sequence. After the CS line is pulled low
to select the device, the Program instruction is transmitted via the SI line followed by the
byte address and the data (D7-D0) to be programmed (Refer to Table 6). Programming
will start after the CS pin is brought high. The low-to-high transition of the CS pin must
occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a RDSR instruction. If Bit 0 = “1”, the program cycle is still in progress. If Bit 0 = “0”, the program cycle
has ended. Only the RDSR instruction is enabled during the program cycle.
A single Program instruction programs 1 to 256 consecutive bytes within a page if it is
not write protected. The starting byte could be anywhere within the page. When the end
of the page is reached, the address will wrap around to the beginning of the same page.
If the data to be programmed are less than a full page, the data of all other bytes on the
same page will remain unchanged. If more than 256 bytes of data are provided, the
address counter will roll over on the same page and the previous data provided will be
replaced. The same byte cannot be reprogrammed without erasing the whole sector
9
2454G–SFLSH–5/06
first. The AT25F4096 will automatically return to the write disable state at the completion
of the Program cycle.
Note:
If the device is not write enabled (WREN), the device will ignore the Write instruction and
will return to the standby state, when CS is brought high. A new CS falling edge is
required to re-initiate the serial communication.
Table 10. Address Key
Address
AT25F4096
AN
A18 - A0
Don’t Care Bits
A23 - A19
SECTOR ERASE (SECTOR ERASE): Before a byte can be reprogrammed, the sector
which contains the byte must be erased. In order to erase the AT25F4096, two separate
instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then the Sector Erase instruction can be executed.
Table 11. Sector Addresses
Sector Address
AT25F4096 Sector
000000 to 00FFFF
Sector 1
010000 to 01FFFF
Sector 2
020000 to 02FFFF
Sector 3
030000 to 03FFFF
Sector 4
040000 to 04FFFF
Sector 5
050000 to 05FFFF
Sector 6
060000 to 06FFFF
Sector 7
070000 to 07FFFF
Sector 8
The Sector Erase instruction erases every byte in the selected sector if the sector is not
locked out. Sector address is automatically determined if any address within the sector
is selected. The Sector Erase instruction is internally controlled; it will automatically be
timed to completion. During this time, all commands will be ignored, except RDSR
instruction. The AT25F4096 will automatically return to the write disable state at the
completion of the Sector Erase cycle.
CHIP ERASE (CHIP ERASE): As an alternative to the Sector Erase, the Chip Erase
instruction will erase every byte in all sectors that are not locked out. First, the device
must be write enabled via the WREN instruction. Then the Chip Erase instruction can be
executed. The Chip Erase instruction is internally controlled; it will automatically be
timed to completion. The Chip Erase cycle time typically is 8 seconds. During the internal erase cycle, all instructions will be ignored except RDSR. The AT25F4096 will
automatically return to the write disable state at the completion of the Chip Erase cycle.
10
AT25F4096
2454G–SFLSH–5/06
AT25F4096
Timing Diagrams (for SPI Mode 0 (0, 0))
Figure 3. Synchronous Data Timing
t CS
VIH
CS
VIL
t CSH
t CSS
VIH
t WH
SCK
t WL
VIL
tH
t SU
VIH
SI
VALID IN
VIL
tV
VOH
SO
HI-Z
t HO
t DIS
HI-Z
VOL
Figure 4. WREN Timing
Figure 5. WRDI Timing
11
2454G–SFLSH–5/06
Figure 6. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
INSTRUCTION
SI
SO
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
MSB
Figure 7. WRSR Timing
Figure 8. READ Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 28 29 30 31 32 33 34 35 36 37 38 39
SCK
3-BYTE ADDRESS
SI
SO
12
INSTRUCTION
HIGH IMPEDANCE
23 22 21 ...
3
2
1
0
7
6
5
4
3
2
1
0
AT25F4096
2454G–SFLSH–5/06
AT25F4096
Figure 9. PROGRAM Timing
4
5
6
7
8
9
10 11 28 29 30 31 32 33 34
2079
3
2078
2
2077
1
2076
0
2075
CS
SCK
256th BYTE DATA-IN
1st BYTE DATA-IN
3-BYTE ADDRESS
SI
INSTRUCTION
23 22 21
3
2
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
Figure 10. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
SO
tLZ
Figure 11. SECTOR ERASE Timing
X
X = Don’t Care bit
13
2454G–SFLSH–5/06
Figure 12. CHIP ERASE Timing
CS
SCK
X
SI
HIGH IMPEDANCE
SO
X = Don’t Care bit
Figure 13. RDID Timing
CS
4
5
6
7 8
1 X
1
0
1
0 1
2 3
0
0
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
SO
14
0
HIGH IMPEDANCE
MANUFACTURER 7
CODE (ATMEL)
DATA OUT
5 4 3 2
DEVICE CODE
6
1
0
AT25F4096
2454G–SFLSH–5/06
AT25F4096
Ordering Information
Ordering Code
Package
AT25F4096W-10SU-2.7
AT25F4096Y4-10YH-2.7(1)
8S2
8Y4
Note:
Operation Range
Lead-Free/Halogen-Free/
Industrial Temperature
(–40°C to 85°C)
1. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.
Package Type
8S2
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8Y4
8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP)
Options
–2.7
Low Voltage (2.7V to 3.6V)
15
2454G–SFLSH–5/06
Package Information
8S2 – EIAJ SOIC
C
1
E
E1
L
N
Top View
∅
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
Side View
NOM
MAX
NOTE
1.70
2.16
A1
0.05
0.25
b
0.35
0.48
5
C
0.15
0.35
5
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
∅
0°
8°
e
Notes: 1.
2.
3.
4.
5.
MIN
A
2, 3
1.27 BSC
4
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
Mismatch of the upper and lower dies and resin burrs are not included.
It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
Determines the true geometric position.
Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
10/7/03
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
DRAWING NO.
8S2
REV.
C
AT25F4096
2454G–SFLSH–5/06
AT25F4096
8Y4-SAP
PIN 1 INDEX AREA
A
D1
PIN 1 ID
D
E1
L
A1
E
e
b
e1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
NOM
MAX
A
–
–
0.90
A1
0.00
–
0.05
D
5.80
6.00
6.20
E
4.70
4.90
5.10
D1
2.85
3.00
3.15
E1
2.85
3.00
3.15
b
0.35
0.40
0.45
SYMBOL
e
1.27 TYP
e1
L
NOTE
3.81 REF
0.50
0.60
0.70
5/24/04
R
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package
(SAP) Y4
DRAWING NO.
REV.
8Y4
A
17
2454G–SFLSH–5/06
Revision History
18
Doc. Rev.
Comments
2454G
•Changed ordering part number from AT25F4096Y4-10YU-2.7 to
AT25F4096Y4-10YH-2.7
•Added Note 1: “H” designates Green Package + RoHS Compliant, with
NiPdAu Lead Finish to ordering information
•Removed ‘Preliminary’ from all pages
AT25F4096
2454G–SFLSH–5/06
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
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