AT91M40800 - Electrical Characteristics

Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor Core
•
•
•
•
•
•
•
•
•
•
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– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-Circuit Emulation)
8K Bytes On-chip SRAM
– 32-bit Data Bus
– Single-clock Cycle Access
Fully-programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to 8 Chip Selects
– Software Programmable 8-/16-bit External Data Bus
8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
32 Programmable I/O Lines
3-channel 16-bit Timer/Counter
– 3 External Clock Inputs
– 2 Multi-purpose I/O Pins per Channel
2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
Programmable Watchdog Timer
Advanced Power-saving Features
– CPU and Peripheral Can be Deactivated Individually
Fully Static Operation: 0 Hz to 40 MHz Internal Frequency Range at 3.0 V, 85°C
1.8V to 3.6V Operating Range
Available in a 100-lead TQFP Package
AT91
ARM® Thumb®
Microcontrollers
AT91M40800
Electrical
Characterisitics
Description
The AT91M40800 microcontroller is a member of the Atmel AT91 16-/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a
high-performance 32-bit RISC architecture with a high-density 16-bit instruction set
and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time
control applications.
The AT91M40800 microcontroller features a direct connection to off-chip memory,
including Flash, through the fully-programmable External Bus Interface (EBI). An
eight-level priority vectored interrupt controller, in conjunction with the Peripheral Data
Controller, significantly improves the real-time performance of the device.
The device is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with on-chip high-speed memory and a wide range
of peripheral functions on a monolithic chip, the AT91M40800 is a powerful microcontroller that offers a flexible, cost-effective solution to many compute-intensive
embedded control applications.
1393C–ATARM–19-Nov-04
Absolute Maximum Ratings*
Operating Temperature (Industrial) .. -40° C to + 85° C
*NOTICE:
Storage Temperature ..................... -60° C to + 150° C
Voltage on Any Input Pin
with Respect to Ground ......................-0.5V to + 5.5V
Maximum Operating Voltage ................................4.6V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or other conditions beyond
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
DC Output Current ..............................................6 mA
The following characteristics are applicable to the Operating Temperature range: TA = -40° C to +85° C, unless otherwise
specified and are certified for a Junction Temperature up to TJ = 100°C.
Table 1. DC Characteristics
Symbol
Parameter
VDD
DC Supply
VIL
Input Low Voltage
VDD = 3.3V
VIH
Input High Voltage
VDD = 3.3V
VOL
Output Low Voltage
IOL = 2.0 mA, VDD = 3.3V
VOH
Output High Voltage
IOH = 2.0 mA, VDD = 3.3V
ILEAK
Input Leakage Current
IPULL
Input Pull-up Current
C IN
Input Capacitance
ISC
Static Current
2
Conditions
Min
1.8
Max
Units
3.6
V
0.8
V
2.0
V
0.4
2.4
VDD = 3.6V, V IN = 0V
VDD = 3.6V; MCKI = 0 Hz
All inputs driven
TMS, TDI, TCK, NRST = 1
Typ
V
V
4
µA
350
µA
6.6
pF
TA = 25° C
12.5
TA = 85° C
250
µA
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
AT91M40800 Electrical Characteristics
Power Consumption
The values in the following tables are measured values in the operating conditions indicated (i.e., VDD = 3.3V or 2.0V, TA = 25° C) on the AT91EB40 Evaluation Board.
Table 2. Power Consumption
VDD
Mode
Conditions
2.0V
3.3V
0.06
0.10
Fetch in ARM mode out of internal
SRAM
All peripheral clocks activated
1.38
4.63
Fetch in ARM mode out of internal
SRAM
All peripheral clocks deactivated
1.04
3.44
All peripheral clocks activated
0.61
2.06
All peripheral clocks deactivated
0.19
0.79
Reset
Unit
Normal
mW/MHz
Idle
Table 3. Power Consumption per Peripheral
VDD
Peripheral
2.0V
3.3V
PIO Controller
0.01
0.16
Timer/Counter Channel
0.01
0.15
Timer/Counter Block (3 Channels)
0.02
0.35
USART
0.03
0.40
Unit
mW/MHz
3
1393C–ATARM–19-Nov-04
Thermal and Reliability
Considerations
Thermal Data
In Table 4, the device lifetime is estimated with the MIL-217 standard in the “moderately
controlled” environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device Junction
Temperature. (For details see the section “Junction Temperature” on page 5.)
Note that the user must be extremely cautious with this MTBF calculation: as the MIL217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). The life test results that have been
measured are always better than the predicted ones.
Table 4. MTBF Versus Junction Temperature
Junction Temperature (TJ) (°C)
Estimated Lifetime (MTBF) (Year)
100
40
125
22
150
12
175
7
Table 5 summarizes the thermal resistance data related to the package of interest.
Table 5. Thermal Resistance Data
Reliability Data
Symbol
Parameter
θ JA
Junction-to-ambient thermal
resistance
θ JC
Junction-to-case thermal resistance
Condition
Package
Typ
Still Air
TQFP100
40
Unit
°C/
W
TQFP100
6.4
The number of gates and the device die size are provided for the user to calculate reliability data with another standard and/or in another environmental model.
Table 6. Reliability Data
4
Parameter
Data
Unit
Number of Logic Gates
272
K gates
Number of Memory Gates
400
K gates
Device Die Size
17.6
mm2
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
AT91M40800 Electrical Characteristics
Junction Temperature
The average chip-junction temperature TJ in °C can be obtained from the following:
1.
T J = T A + ( P D × θ JA )
2.
T J = T A + ( P D × ( θ HEATSINK + θ JC ) )
Where:
•
θ JA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 5
on page 4.
•
θ JC = package thermal resistance, Junction-to-case thermal resistance (°C/W),
provided in Table 5 on page 4.
•
θ HEAT SINK = cooling device thermal resistance (°C/W), provided in the device
datasheet.
•
PD = device power consumption (W) estimated from data provided in the section
“Power Consumption” on page 3.
•
TA = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and
thereby decide if a cooling device is necessary or not. If a cooling device is to be fitted
on the chip, the second equation should be used to compute the resulting average chipjunction temperature TJ in °C.
5
1393C–ATARM–19-Nov-04
Conditions
Timing Results
The delays are given as typical values in the following conditions:
•
•
VDD = 3.3V
Ambient Temperature = 25° C
•
Load Capacitance = 0 pF
•
The output level change detection is 0.5 x V DD
•
The input level is 0.3 x VDD for a low-level detection and is 0.7 x VDD for a high level
detection.
The minimum and maximum values given in the AC characteristics tables of this
datasheet take into account the process variation and the design.
In order to obtain the timing for other conditions, the following equation should be used:
t = δT ° × δVDD × ( t DATASHEET + ∑( C SIGNAL × δCSIGNAL ) )
Where:
•
•
•
δT° is the derating factor in temperature given in Figure 1.
δVDD is the derating factor for the Power Supply given in Figure 2.
tDATASHEET is the minimum or maximum timing value given in this datasheet for a load
capacitance of 0 pF.
•
CSIGNAL is the capacitance load on the considered output pin.(1)
•
δCSIGNAL is the load derating factor depending on the capacitance load on the related
output pins given in Min and Max values in this datasheet.
The input delays are given as typical values.
The input delays are given as typical value.
Note:
Temperature Derating
Factor
1. The user must take into account the package capacitance load contribution (CIN)
described in Table 1 on page 2.
Figure 1. Derating Curve for Different Operating Temperatures
1.3
Derating Factor
1.2
1.1
1
Derating Factor for
Typ Case is 1
0.9
0.8
-60
-40
-20
0
20
40
60
80
100
120
140
160
Operating Temperature (˚C)
6
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
AT91M40800 Electrical Characteristics
Figure 2. Derating Curve for Different Supply Voltages
Derating Factor
Supply Voltage Derating
Factor
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
Typical Derating Factor
for Typ Case is 1
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Supply Voltage (V)
Note:
This derating factor is applicable only to timings related to output pins.
7
1393C–ATARM–19-Nov-04
Clock Waveforms
Table 7. Master Clock Waveform Parameters
Symbol
Parameter
Conditions
Min
Max
Units
1/(t CP)
Oscillator Frequency
47.7
MHz
tCP
Oscillator Period
21.0
ns
tCH
High Half-period
9.1
ns
tCL
Low Half-period
9.4
ns
Table 8. Clock Propagation Times
Symbol
Parameter
tCDLH
Rising Edge Propagation Time
tCDHL
Falling Edge Propagation Time
Conditions
Min
Max
Units
CMCKO = 0 pF
4.2
6.6
ns
0.034
0.053
ns/pF
4.5
7.1
ns
0.042
0.066
ns/pF
CMCKO derating
CMCKO = 0 pF
CMCKO derating
Figure 3. Clock Waveform
tCH
MCKI
0.7 VDD
0.3 VDD
tCL
tCP
MCKO
tCDLH
8
0.5 VDD
0.5 VDD
tCDHL
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
AT91M40800 Electrical Characteristics
Table 9. NRST to MCKO
Symbol
Parameter
tD
NRST Rising Edge to MCKO Valid
Time
Min
Max
Units
3(tCP/2)
7(tCP/2)
ns
Figure 4. MCKO Relative to NRST
NRST
tD
MCKO
9
1393C–ATARM–19-Nov-04
AC Characteristics
EBI Signals Relative to MCKI
The following tables show timings relative to operating condition limits defined in the section “Timing Results” on page 6.
See Figure 5 on page 14.
Table 10. General-purpose EBI Signals
Symbol
Parameter
EBI1
MCKI Falling to NUB Valid
EBI2
MCKI Falling to NLB/A0 Valid
EBI3
MCKI Falling to A1 - A23 Valid
EBI4
MCKI Falling to Chip Select
Change
EBI5
NWAIT Setup before MCKI Rising
0.6
ns
EBI6
NWAIT Hold after MCKI Rising
3.2
ns
10
Conditions
Min
Max
Units
CNUB = 0 pF
5.4
11.7
ns
0.034
0.066
ns/pF
4.3
8.7
ns
0.038
0.062
ns/pF
4.2
10.0
ns
0.038
0.066
ns/pF
4.6
10.4
ns
0.038
0.057
ns/pF
CNUB derating
CNLB = 0 pF
CNLB derating
CADD = 0 pF
CADD = derating
CNCS = 0 pF
CNCS derating
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
AT91M40800 Electrical Characteristics
Table 11. EBI Write Signals
Symbol
Parameter
EBI7
MCKI Rising to NWR Active (No Wait States)
EBI8
MCKI Rising to NWR Active (Wait States)
EBI9
MCKI Falling to NWR Inactive (No Wait States)
EBI10
MCKI Rising to NWR Inactive (Wait States)
EBI11
MCKI Rising to D0 - D15 Out Valid
EBI12
NWR High to NUB Change
EBI13
NWR High to NLB/A0 Change
EBI14
NWR High to A1 - A23 Change
EBI15
NWR High to Chip Select Inactive
Conditions
Min
Max
Units
CNWR = 0 pF
4.3
7.1
ns
0.042
0.066
ns/pF
5.0
8.2
ns
0.042
0.066
ns/pF
4.9
8.0
ns
0.034
0.053
ns/pF
5.0
8.2
ns
0.034
0.053
ns/pF
4.1
8.6
ns
0
0.066
ns/pF
3.3
7.6
ns
0.034
0.066
ns/pF
2.8
4.6
ns
0.042
0.066
ns/pF
2.7
6.5
ns
0.042
0.066
ns/pF
3.2
6.4
ns
0.034
0.066
ns/pF
CNWR derating
CNWR = 0 pF
CNWR derating
CNWR = 0 pF
CNWR derating
CNWR = 0 pF
CNWR derating
CDATA = 0 pF
CDATA derating
CNUB = 0 pF
CNUB derating
CNLB = 0 pF
CNLB derating
CADD = 0 pF
CADD derating
CNCS = 0 pF
CNCS derating
C = 0 pF
EBI16
Data Out Valid before NWR High (No Wait States)
(1)
tCH - 0.9
ns
CDATA derating
-0.066
ns/pF
CNWR derating
0.053
ns/pF
n x tCP - 0.8(2)
ns
CDATA derating
-0.066
ns/pF
CNWR derating
0.053
ns/pF
2.1
ns
tCH + 0.4
ns
C = 0 pF
EBI17
Data Out Valid before NWR High (Wait States)
(1)
EBI18
Data Out Valid after NWR High
EBI19
NWR Minimum Pulse Width (No Wait States)(1)
EBI20
Notes:
CNWR = 0 pF
CNWR derating
NWR Minimum Pulse Width (Wait States)(1)
CNWR = 0 pF
CNWR derating
-0.013
ns/pF
(2)
n x tCP - 0.4
-0.013
ns
ns/pF
1. The derating factor should not be applied to tCH or tCP.
2. n = number of standard wait states inserted.
11
1393C–ATARM–19-Nov-04
Table 12. EBI Read Signals
Symbol
Parameter
EBI21
MCKI Falling to NRD Active(1)
EBI22
MCKI Rising to NRD Active(2)
EBI23
MCKI Falling to NRD Inactive(1)
EBI24
MCKI Falling to NRD Inactive(2)
EBI25
D0 - D15 In Setup before MCKI Falling Edge(5)
Max
Units
CNRD = 0 pF
5.0
9.0
ns
0.042
0.066
ns/pF
4.1
8.6
ns
0.042
0.066
ns/pF
5.2
9.4
ns
0.034
0.053
ns/pF
4.9
7.7
ns
0.034
0.053
ns/pF
CNRD = 0 pF
CNRD derating
CNRD = 0 pF
CNRD derating
CNRD = 0 pF
CNRD derating
D0 - D15 In Hold after MCKI Falling Edge
EBI27
NRD High to NUB Change
EBI28
NRD High to NLB/A0 Change
EBI29
NRD High to A1 - A23 Change
EBI30
NRD High to Chip Select Inactive
EBI31
Data Setup before NRD High(5)
EBI32
Data Hold after NRD High(5)
(5)
CNUB = 0 pF
0.066
ns/pF
3.3
5.2
ns
CNLB derating
0.042
0.066
ns/pF
CADD = 0 pF
3.2
7.1
ns
0.042
0.066
ns/pF
3.6
6.9
ns
0.034
0.066
ns/pF
CNLB = 0 pF
CNCS = 0 pF
CNRD = 0 pF
CNRD = 0 pF
CNRD derating
CNRD = 0 pF
CNRD = 0 pF
9.0
ns
0.053
ns/pF
-2.4
ns
-0.034
ns/pF
(4)
(n +1) tCP - 0.7
CNRD derating
ns
-0.013
ns/pF
n x tCP + (tCH - 0.9)(4)
ns
-0.013
ns/pF
CNRD derating
1.
2.
3.
4.
5.
ns
0.034
CNRD derating
NRD Minimum Pulse Width(2)(3)
4.0
ns
CNCS derating
EBI34
ns
8.4
CADD derating
NRD Minimum Pulse Width(1)(3)
-0.3
4.1
CNUB derating
EBI33
12
Min
CNRD derating
EBI26
Notes:
Conditions
Early Read Protocol.
Standard Read Protocol.
The derating factor should not be applied to tCH or tCP.
n = number of standard wait states inserted.
Only one of these two timings needs to be met.
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
AT91M40800 Electrical Characteristics
Table 13. EBI Read and Write Control Signals. Capacitance Limitation
Symbol
Parameter
TCPLNRD (1)
Master Clock Low Due to NRD Capacitance
TCPLNWR (2)
Master CLock Low Due to NWR Capacitance
Notes:
Conditions
Min
CNRD = 0 pF
10.8
ns
CNRD derating
0.053
ns/pF
8.6
ns
0.053
ns/pF
CNWR = 0 pF
CNWR derating
Max
Units
1. If this condition is not met, the action depends on the read protocol intended for use.
• Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle.
• Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state.
2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be
programmed.
13
1393C–ATARM–19-Nov-04
Figure 5. EBI Signals Relative to MCKI
MCKI
EBI4
EBI4
NCS
CS
EBI3
A1 - A23
EBI5
EBI6
NWAIT
EBI1/EBI2
NUB/NLB/A0
EBI21
NRD(1)
EBI23
EBI27 - 30
EBI33
EBI22
NRD(2)
EBI24
EBI34
EBI31
EBI32
EBI25
EBI26
D0 - D15 Read
EBI12 - 15
EBI9
EBI7
EBI19
NWR (No Wait States)
EBI8
EBI10
EBI20
NWR (Wait States)
EBI11
EBI17
EBI16
EBI18
EBI18
D0 - D15 to Write
No Wait
Notes:
14
Wait
1. Early Read Protocol.
2. Standard Read Protocol.
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
AT91M40800 Electrical Characteristics
Peripheral Signals
USART Signals
The inputs have to meet the minimum pulse width and period constraints shown in
Table 14 and Table 15, and represented in Figure 6.
Table 14. USART Input Minimum Pulse Width
Symbol
Parameter
US1
SCK/RXD Minimum Pulse Width
Min Pulse Width
Units
5(tCP/2)
ns
Min Input Period
Units
9(tCP/2)
ns
Table 15. USART Minimum Input Period
Symbol
Parameter
US2
SCK Minimum Input Period
Figure 6. USART Signals
US1
RXD
US2
US1
SCK
15
1393C–ATARM–19-Nov-04
Timer/Counter Signals
Due to internal synchronization of input signals, there is a delay between an input event
and a corresponding output event. This delay is 3(tCP) in Waveform Event Detection
mode and 4(tCP) in Waveform Total-count Detection mode. The inputs have to meet the
minimum pulse width and minimum input period shown in Table 16 and Table 17, and
as represented in Figure 7.
Table 16. Timer Input Minimum Pulse Width
Symbol
Parameter
TC1
TCLK/TIOA/TIOB Minimum Pulse Width
Min Pulse Width
Units
3(tCP/2)
ns
Min Input Period
Units
5(tCP/2)
ns
Table 17. Timer Input Minimum Period
Symbol
Parameter
TC2
TCLK/TIOA/TIOB Minimum Input Period
Figure 7. Timer Input
3(tCP/2)
TC2
3(tCP/2)
MCKI
TC1
TIOA/
TIOB/
TCLK
16
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
AT91M40800 Electrical Characteristics
Reset Signals
A minimum pulse width is necessary, as shown in Table 18 and as represented in Figure 8.
Table 18. Reset Minimum Pulse Width
Symbol
Parameter
RST1
NRST Minimum Pulse Width
Min Pulse-width
Units
10(tCP)
ns
Figure 8. Reset Signal
RST1
NRST
O n ly the N RST risin g e dg e is syn ch ron ize d w ith MC KI. The fa lling e dg e is
asynchronous.
17
1393C–ATARM–19-Nov-04
Advanced Interrupt Controller
Signals
Inputs have to meet the minimum pulse width and minimum input period shown in Table
19 and Table 20 and represented in Figure 9.
Table 19. AIC Input Minimum Pulse Width
Symbol
Parameter
AIC1
FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse Width
Min Pulse Width
Units
3(tCP/2)
ns
Min Input Period
Units
5(tCP/2)
ns
Table 20. AIC Input Minimum Period
Symbol
Parameter
AIC2
AIC Minimum Input Period
Figure 9. AIC Signals
AIC2
MCKI
AIC1
FIQ/
IRQ0/IRQ1/
IRQ2/IRQ3
Input
Parallel I/O Signals
The inputs have to meet the minimum pulse width shown in Table 21 and represented in Figure 10.
Table 21. PIO Input Minimum Pulse Width
Symbol
Parameter
PIO1
PIO Input Minimum Pulse Width
Min Pulse Width
Units
3(tCP/2)
ns
Figure 10. PIO Signal
PIO1
PIO
Inputs
18
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
AT91M40800 Electrical Characteristics
ICE Interface Signals
Table 22. ICE Interface Timing Specifications
Symbol
Parameter
Conditions
ICE0
NTRST Minimum Pulse Width
18.8
ns
ICE1
NTRST High Recovery to TCK High
1.2
ns
ICE2
NTRST High Removal from TCK
High
-0.2
ns
ICE3
TCK Low Half-period
41.7
ns
ICE4
TCK High Half-period
40.9
ns
ICE5
TCK Period
82.5
ns
ICE6
TDI, TMS Setup before TCK High
0.5
ns
ICE7
TDI, TMS Hold after TCK High
0.6
ns
5.2
ns
ICE8
TDO Hold Time
0
ns/pF
ICE9
TCK Low to TDO Valid
CTDO = 0 pF
CTDO derating
Min
Max
Units
CTDO = 0 pF
10.2
ns
CTDO derating
0.063
ns/pF
Figure 11. ICE Interface Signal
ICE0
NTRST
ICE1
ICE2
ICE5
TCK
ICE3
ICE4
TMS/TDI
ICE6
ICE7
TDO
ICE8
ICE9
19
1393C–ATARM–19-Nov-04
Document Details
Title
AT91M40800 Electrical Characteristics
Literature Number
Lit# 1393B
Revision History
Version A
Publication Date: Sep, 2000
Version B
Publication Date: 10-Dec-2001
Revisions Since Previous Version published on Intranet
Page: 1
“Features” “Fully Static Operation: 0 Hz to 40 MHz Internal Frequency Range at 3.0 V,
85°C” ..... frequency and range modified
Page: 4
“Reliability Data” paragraph modified and new table inserted. “Table 6 Reliability Data”
Page: 6
“Timing Results” Cross reference added to CSIGNAL part of equation.
Page: 8
Table 7. Master Clock Waveform Parameters. Values have been changed for Oscillator
Frequency and Oscillator Period. Some master clock parameters deleted.
Page: 10
Table 10. General-purpose EBI Signals. EBI4, Conditions are changed.
Page: 13
New table inserted. Table 13. Read and Write Control Signals. Capacitance Limitation.
This table adds understanding to EBI Signals Relative to MCK.
Version C
Publication Date: 19-Nov-2004
Page 8
Changes in Table 7: new figures for tCH and tCL, removed references to tr and tf. Updated
Figure 3 on page 8.
20
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Atmel Corporation
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