AT17F32A - Complete

Features
• Programmable 33,554,432 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
• 3.3V Output Capability
• 5V Tolerant I/O Pins
• Program Support using the Atmel ATDH2200E System or Industry Third Party
Programmers
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Altera® FLEX®, Excalibur™, Stratix™, Cyclone™ and APEX™ Devices
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Low-power CMOS FLASH Process
Available in 44 PLCC Packages
Emulation of Atmel’s AT24Cxxx Serial EEPROMs
Low-power Standby Mode
Single Device Capable of Holding 4 Individual Bit Stream Files Allowing Simple System
Reconfiguration
• Endurance: 10,000 Write Cycles Typical
• Green (Lead and Halide-Free/ROHS Compliant) Package Options Available
•
•
•
•
•
•
•
•
•
FPGA
Configuration
Flash Memory
AT17F32A
1. Description
The AT17FxxA Series of In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field
Programmable Gate Arrays. The AT17FxxA Series device is packaged in the 44-lead
PLCC see Table 1-1. The AT17FxxA Series Configurator uses a simple serial-access
procedure to configure one or more FPGA devices.
The AT17FxxA Series Configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1.
Package
44-lead PLCC
AT17FxxA Series Packages
AT17F32A
Yes
3489C–CNFG–08/07
2. Pin Configuration
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
NC
SER_EN
NC
NC
READY
NC
PAGESEL1
NC
NC
NC
NC
NC
GND
PAGESEL0
NC
NC
NC
NC
NC
NC
NC
nCASC/A2
NC
DCLK
NC
NC
NC
NC
NC
NC
NC
RESET/OE
nCS
6
5
4
3
2
1
44
43
42
41
40
NC
NC
NC
NC
DATA
PAGE_EN
NC
NC
NC
VCC
NC
44-lead PLCC
2
AT17F32A
3489C–CNFG–08/07
AT17F32A
3. Block Diagram
READY
PAGE_EN
PAGESEL0
PAGESEL1
Power-on
Reset
Reset
Clock/Oscillator
Logic
nCASC(A2)
Config. Page
Select
Serial Download Logic
2-wire Serial Programming
Flash
Memory
DCLK
CE/WE/OE
Data
Address
DATA
nCS
Control Logic
RESET/OE
SER_EN
4. Device Description
The control signals for the configuration memory device (nCS, RESET/OE and DCLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration device without requiring an external
intelligent controller.
The RESET/OE and nCS pins control the tri-state buffer on the DATA output pin and enable the
address counter. When RESET/OE is driven Low, the configuration device resets its address
counter and tri-states its DATA pin. The nCS pin also controls the output of the AT17FxxA
Series Configurator. If nCS is held High after the RESET/OE reset pulse, the counter is disabled
and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the
DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is
reset and the DATA output pin is tri-stated, regardless of the state of nCS.
When the configurator has driven out all of its data and nCASC is driven Low, the device tristates the DATA pin to avoid contention with other configurators. Upon power-up, the address
counter is automatically reset.
3
3489C–CNFG–08/07
5. Pin Description
AT17F32A
Name
I/O
44
PLCC
DATA
I/O
2
DCLK
I/O
8
PAGE_EN
I
1
PAGESEL0
I
20
PAGESEL1
I
33
RESET/OE
I
16
nCS
I
17
GND
–
19
nCASC
O
A2
I
READY
O
35
SER_EN
I
38
VCC
–
41
28
5.1
DATA(1)
Three-state DATA output for FPGA configuration. Open-collector bi-directional pin for configuration programming.
5.2
DCLK(1)
Three-state clock. Functions as an input when the Configurator is in programming mode (i.e.
SER_EN is Low) and as an output during FPGA configuration.
5.3
PAGE_EN(2)
Input used to enable page download mode. When PAGE_EN is high the configuration download
address space is partitioned into 4 equal pages. This gives users the ability to easily store and
retrieve multiple configuration bitstreams from a single configuration device. This input works in
conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired.
When SER_EN is Low (ISP mode) this pin has no effect.
Notes:
1. This pin has an internal 20 KΩ pull-up resistor.
2. This pin has an internal 30 KΩ pull-down resistor.
4
AT17F32A
3489C–CNFG–08/07
AT17F32A
5.4
PAGESEL[1:0](2)
Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial
configuration download. The address space for each of the pages is shown in Table 5-1. When
SER_EN is Low (ISP mode) these pins have no effect.
Table 5-1.
5.5
Address Space
Paging Decodes
AT17F32A (32 Mbits)
PAGESEL = 00, PAGE_EN = 1
000000 – 07FFFFh
PAGESEL = 01, PAGE_EN = 1
080000 – 0FFFFFh
PAGESEL = 10, PAGE_EN = 1
100000 – 17FFFFh
PAGESEL = 11, PAGE_EN = 1
180000 – 1FFFFFh
PAGESEL = XX, PAGE_EN = 0
000000 – 1FFFFFh
RESET/OE(1)
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with nCS Low) enables the
data output driver.
5.6
nCS(1)
Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the
address counter and enables the data output driver. A High level on nCS disables both the
address and bit counters and forces the device into a low-power standby mode. Note that this
pin will not enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low).
5.7
GND
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
5.8
nCASC
Cascade Select Output (when SER_EN is High). This output goes Low when the internal
address counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value is the highest address in the selected partition. The PAGESEL[1:0] inputs are used
to make the 4 partition selections. If the PAGE_EN input is set Low, the device is not partitioned
and the address maximum value is the highest address in the device, see Table 5-1 on page 5.
In a daisy chain of AT17FxxA Series devices, the nCASC pin of one device must be connected
to the nCS input of the next device in the chain. It will stay Low as long as nCS is Low and OE is
High. It will then follow nCS until OE goes Low; thereafter, nCASC will stay High until the entire
EEPROM is read again.
Notes:
1. This pin has an internal 20 KΩ pull-up resistor.
2. This pin has an internal 30 KΩ pull-down resistor.
5
3489C–CNFG–08/07
5.9
A2(1)
Device selection input, (when SER_EN Low). The input is used to enable (or chip select) the
device during programming (i.e., when SER_EN is Low). Refer to the AT17FxxA Programming
Specification available on the Atmel web site for additional details.
5.10
READY
Open collector reset state indicator. Driven Low during power-up reset, released when power-up
is complete. (recommended 4.7 kΩ pull-up on this pin if used).
5.11
SER_EN(1)
The serial enable input must remain High during FPGA configuration operations. Bringing
SER_EN Low enables the 2-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to VCC.
5.12
VCC
+3.3V (±10%).
Notes:
1. This pin has an internal 20 KΩ pull-up resistor.
2. This pin has an internal 30 KΩ pull-down resistor.
6
AT17F32A
3489C–CNFG–08/07
AT17F32A
6. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17FxxA Serial Configuration PROM has been
designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as
Altera applications.
7. Control of Configuration
Most connections between the FPGA device and the AT17FxxA Serial Configurator PROM are
simple and self-explanatory.
• The DATA output of the AT17FxxA Series Configurator drives DIN of the FPGA devices.
• The DCLK output of the AT17FxxA device drives the DCLK input data of the FPGA.
• The nCASC output of a AT17FxxA Series Configurator drives the nCS input of the next
Configurator in a cascade chain of configurator devices.
• SER_EN must be at logic High level (internal pull-up resistor provided) except during ISP.
• The READY pin is available as an open-collector indicator of the device’s reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
• PAGE_EN must remain Low if download paging is not desired. If paging is desired,
PAGE_EN must be High and the PAGESEL pins must be set to High or Low such that the
desired page is selected, see Table 5-1 on page 5.
8. Cascading Serial Configuration Devices
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration
memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its
nCASC output Low and disables its DATA line driver. The second configurator recognizes the
Low level on its nCS input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if
the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be
tied to its inactive (High) level.
9. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming
super voltages are generated inside the chip. The AT17FxxA parts are read/write at 3.3V nominal. Refer to the AT17FxxA Programming Specification available on the Atmel web site
(www.atmel.com) for more programming details. AT17FxxA devices are supported by the Atmel
ATDH2200 programming system along with many third party programmers.
7
3489C–CNFG–08/07
10. Standby Mode
The AT17FxxA Series Configurators enter a low-power standby mode whenever SER_EN is
High and nCS is asserted High. In this mode, the AT17FxxA Configurator typically consumes
less than 1 mA of current at 3.3V. The output remains in a high-impedance state regardless of
the state of the OE input.
11. Absolute Maximum Ratings*
Operating Temperature.................................... -40°C to +85 °C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground ..............................-0.5V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +4.0V
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods of time may affect device reliability.
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
12. Operating Conditions
AT17FxxA Series
Configurator
Symbol
Description
Min
Max
Units
Commercial
Supply voltage relative to GND
-0°C to +70°C
2.97
3.63
V
Industrial
Supply voltage relative to GND
-40°C to +85°C
2.97
3.63
V
VCC
13. DC Characteristics
AT17F32A
Symbol
Description
Min
Max
Units
VIH
High-level Input Voltage
2.0
VCC
V
VIL
Low-level Input Voltage
0
0.8
V
VOH
High-level Output Voltage (IOH = -2.5 mA)
VOL
Low-level Output Voltage (IOL = +3 mA)
VOH
High-level Output Voltage (IOH = -2 mA)
VOL
Low-level Output Voltage (IOL = +3 mA)
0.4
V
ICCA
Supply Current, Active Mode at Freq. Max.
50
mA
IL
Input or Output Leakage Current (VIN = VCC or GND)
10
µA
Commercial
3
mA
ICCS
Supply Current, Standby Mode
Industrial
3
mA
8
2.4
V
Commercial
0.4
2.4
V
V
Industrial
-10
AT17F32A
3489C–CNFG–08/07
AT17F32A
14. AC Characteristics
nCS
TSCE
TSCE
THCE
RESET/OE
TLC
THOE
THC
CLK
TOE
TOH
TCAC
TDF
TCE
DATA
TOH
15. AC Characteristics when Cascading
RESET/OE
nCS
CLK
TCDF
DATA
FIRST BIT
LAST BIT
TOCK
TOCE
TOOE
nCASC
TOCE
9
3489C–CNFG–08/07
16. AC Characteristics
AT17F32A
Symbol
Description
TOE(2)
OE to Data Delay
TCE(2)
nCS to Data Delay
TCAC(2)
DCLK to Data Delay
TOH
Data Hold from nCS, OE, or DCLK
TDF(3)
nCS or OE to Data Float Delay
TLC
DCLK Low Time
THC
DCLK High Time
TSCE
Min
Typ
Max
Units
50
ns
Industrial
55
ns
Commercial
55
ns
Industrial
60
ns
Commercial
30
ns
30
ns
Commercial
(1)
(1)
(1)
Industrial
Commercial
0
ns
Industrial(1)
0
ns
Commercial
(1)
Industrial
15
ns
15
ns
Commercial
15
ns
Industrial(1)
15
ns
Commercial
15
ns
Industrial
15
ns
nCS Setup Time to DCLK
(to guarantee proper counting)
Commercial
20
ns
Industrial
25
ns
nCS Hold Time from DCLK
(to guarantee proper counting)
Commercial
0
ns
THCE
Industrial
0
ns
RESET/OE Low Time
(guarantees counter is reset)
Commercial
20
ns
THOE
20
ns
Maximum Input Clock Frequency
SEREN = 0
Commercial
FMAX
TWR
Write Cycle Time(4)
TEC
Erase Cycle Time(4)
Notes:
(1)
(1)
(1)
(1)
Industrial
(1)
Industrial
10
MHz
10
MHz
Commercial
12
µs
Industrial(1)
12
µs
Commercial
50
s
50
s
(1)
Industrial
1. Preliminary specifications for military operating range only.
2. AC test lead = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady-state active levels.
4. See the AT17F Programming Specfication for procedural information.
5. The times given are per byte (typical).
10
AT17F32A
3489C–CNFG–08/07
AT17F32A
AC Characteristics When Cascading
AT17F32A
Symbol
Description
TCDF(3)
DCLK to Data Float Delay
TOCK(2)
DCLK to nCASC Delay
TOCE(2)
nCS to nCASC Delay
TOOE(2)
RESET/OE to nCASC Delay
Notes:
Min
Max
Units
Commercial
50
ns
Industrial
50
ns
Commercial
50
ns
Industrial
55
ns
Commercial
35
ns
Industrial
40
ns
Commercial
35
ns
Industrial
35
ns
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
17. Thermal Resistance Coefficients
Package Type
44J
Note:
Plastic Leaded Chip Carrier (PLCC)
AT17F32A
θJC [°C/W]
θJA [°C/W]
(1)
–
–
1. Airflow = 0 ft/min.
11
3489C–CNFG–08/07
18. Ordering Information
Memory Size
Ordering Code
Package
Operation Range
AT17F32A-30BJI
44J-44PLCC
Industrial
(-40°C to 85°C)
AT17F32A-30BJU
44J-44PLCC
LHF Industrial
(-40°C to 85°C)
32-Mbit
Note:
1. The last time buy date is December 29, 2006 for the shaded parts.
Package Type
44J
12
44-lead, Plastic J-leaded Chip Carrier (PLCC)
AT17F32A
3489C–CNFG–08/07
AT17F32A
19. Packaging Information
19.1
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
17.399
–
17.653
D1
16.510
–
16.662
E
17.399
–
17.653
E1
16.510
–
16.662
D2/E2
14.986
–
16.002
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
44J
B
13
3489C–CNFG–08/07
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3489C–CNFG–08/07
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