ATPL250A - Datasheet

ATPL250A
ATPL Series Power Line Communications Device
DATASHEET
Description
ATPL250A is a G3-PLC modem for Power Line Communication. ATPL250A flexible architecture, composed of hardware accelerators and coprocessors, achieves a very efficient G3 PHY
layer implementation.
ATPL250A is therefore a compact and high-efficient device for a wide range of Smart Grid
applications such as Smart Metering (Smart Meters and Data Concentrators), Lighting, Industrial/Home Automation, Home and Building Energy Management Systems, Solar Energy and
Plug-in Hybrid Electric Vehicle (PHEV) Charging Stations.
ATPL250A has been conceived to be bundled with an external Atmel® MCU. Atmel provides a
G3 PHY layer library which is used by the external MCU to take control of ATPL250A PHY
layer device.
ATMEL provides high-efficient, reduced BOM reference designs for different coupling options,
targeting common configurations in standard frequency bands complying with existing regulations (CENELEC, FCC, ARIB).
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
1.
Features

G3-PLC modem

Implements G3 CENELEC-A, FCC and ARIB profiles (ITU-T G.9903, June ´14)

Power Line Carrier Modem for 50 Hz and 60 Hz mains

G3-PLC coherent and differential modulation schemes available

Automatic Gain Control and continuous amplitude tracking in signal reception

1 SPI peripheral (slave) to external MCU

Zero cross detection

Embedded PLC Analog Front End (AFE), requires only external discrete high efficient Class D Line Driver for
signal injection

TA range -40ºC to +85ºC

Package

1.1
80-lead LQFP
ATPL250A Application Block Diagram
ATPL250A has been conceived to be easily managed by an external microcontroller through a 5-line interface. This
interface is comprised of a 4-line standard Serial Peripheral Interface (SPI) and an additional line used as interrupt
from the ATPL250A to the external microcontroller. The external microcontroller can fully manage and control the
ATPL250A (Phy layer, MAC coprocessing, etc.) by accessing the internal peripheral registers.
Figure 1-1. ATPL250A application example
L
N
Power
Supply
CS
EMIT [0:11]
TXRX [0:1]
SCK
MOSI
MISO
External
Microcontroller
EINT
(Optional)
ATPL250A
AGC [0:5]
RST(1)
VIPA
VRC
CLKOUT
VIMA
VZ CROSS
Note:
2
1.
PLC
Coupling
Zero Crossing
External Circuit
There are several RST signals (ARST, SRST and PLL INIT), for more details see Section 3. ”Signal
Description”.
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
2.
Block Diagram
Figure 2-1. ATPL250A Functional Block Diagram
Interleaver
SPI
RAW
DATA
TXRXB
EMITCTRL
Converter/PAD
Preamble
Interpolator
Analog
Front-End
Control
Convolutional
Encoder
Scrambler
Repeater
IFFT
INOUTB
Modulator
CLOCK &
RESET
INTERFACE
CD
VDDIO
VDDOUT
VDDPLL
VDDIN
VDDIN AN
VDDOUT AN
GND
AGND
BER
RSSI
EVM
POWER
SPI
RAW
DATA
Combiner
Reed-Solomon
Coprocessor
Demodulator
Scrambler
Viterbi
CS
SCK
MOSI
MISO
EINT
SPI
INTERFACE
RMS
ZERO CROSS
DETECTOR
MANAGEMENT
Interleaver
TXRX0
TXRX1
TX
Reed-Solomon
Coprocessor
ARST
SRST
PLL INIT
CLKEA
CLKEB
CLKOUT
EMIT(0 :11)
INOUTB
FFT
SYNCM
Detector
TXRXB
Decimator
Syncro
Preamble
AGC
DC block
Converter
VZ CROSS
AGC(0:5)
VIMA
VIPA
VRP
VRM
VRC
RX
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
3
3.
Signal Description
Table 3-1.
Signal Description List
Signal Name
Type
Function
Active
Level
Voltage
reference
Comments
Power Supplies
VDDIO
3.3V digital supply. Digital power supply must be
decoupled by external capacitors
Power
3.0V to 3.6V
VDDIN
3.3V Digital LDO input supply
Power
3.0V to 3.6V
VDDIN AN
3.3V Analog LDO input supply
Power
3.0V to 3.6V
VDDOUT AN
1.2V Analog LDO output. A capacitor in the range
0.1 μF - 10 μF must be connected to each pin
Power
1.2V
VDDOUT
1.2V Digital LDO output. A capacitor in the range
0.1 μF - 10 μF must be connected to each pin
Power
1.2V
VDDPLL
1.2V PLL supply. It must be decoupled by a 100nF
external capacitor, and connected to VDDOUT
through a filter (Cut off frequency: 25 kHz)
Power
1.2V
GND(1)
Digital Ground
Power
Analog Ground
Power
(1)
AGND
Clocks, Oscillators and PLLs
(2)
CLKEA
External Clock Oscillator
• CLKEA must be connected to one terminal of a
crystal (when a crystal is being used) or used
as input for external clock signal
Input
VDDIO
CLKEB(2)
External Clock Oscillator
• CLKEB must be connected to one terminal of a
crystal (when a crystal is being used) or must
be floating when an external clock signal is
connected through CLKEA
I/O
VDDIO
CLKOUT
12 MHz CLK Output
Output
VDDIO
Reset/Test
ARST
Asynchronous Reset
Input
Low
VDDIO
Internal pull up(3)
SRST
Synchronous Reset
Input
Low
VDDIO
Internal pull up(3)
PLL INIT
PLL Initialization Signal
Input
Low
VDDIO
Internal pull up(3)
GPLC (G3 Power Line Communications) Transceiver
(4)
4
EMIT [0:11]
PLC Tri-state Transmission ports
Output
VDDIO
AGC [0:5]
Automatic Gain Control:
• These digital tri-state outputs are managed by
AGC hardware logic to drive external circuitry
when input signal attenuation is needed
Output
VDDIO
TXRX0
Analog Front-End Transmission/Reception for
TXDRV0
• This digital output is used to modify external
coupling behavior in Transmission/Reception.
The suitable value depends on the external
circuitry configuration. The polarity of this pin
can be inverted by software
Output
VDDIO
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
Table 3-1.
Signal Description List
Type
Active
Level
Voltage
reference
Signal Name
Function
TXRX1
Analog Front-End Transmission/Reception for
TXDRV1
• This digital output is used to modify external
coupling behavior in Transmission/Reception.
The suitable value depends on the external
circuitry configuration. The polarity of this pin
can be inverted by software
Output
VDDIO
VZ CROSS(5)
Mains Zero-Cross Detection Signal:
• This input detects the zero-crossing of the
mains voltage
Input
VDDIO
VIMA
Negative Differential Voltage Input
Input
VDDOUT AN
VIPA
Positive Differential Voltage Input
Input
VDDOUT AN
VRP
Internal Reference “Plus” Voltage. Connect an
external decoupling capacitor between VRP and
VRM (1nF - 100nF)
Output
VDDOUT AN
VRM
Internal Reference “Minus” Voltage. Connect an
external decoupling capacitor between VRP and
VRM (1nF - 100nF)
Output
VDDOUT AN
VRC
Common-mode Voltage. Bypass to analog ground
with an external decoupling capacitor (100pF 1nF)
Output
VDDOUT AN
Comments
Internal pull down(3)
Serial Peripheral Interface - SPI
CS
SPI CS
• SPI bridge Slave Select
Input
SCK
SPI SCK
• SPI bridge Clock signal
MOSI
VDDIO
Internal pull up(3)
Input
VDDIO
Internal pull up(3)
SPI MOSI
• SPI bridge Master Out Slave In
Input
VDDIO
Internal pull up(3)
MISO
SPI MISO
• SPI bridge Master In Slave Out
Output
VDDIO
EINT
PHY Layer External Interrupt
Output
Low
Low
VDDIO
Notes: 1. Separate pins are provided for GND and AGND grounds. Layout considerations should be taken into account to
reduce interference. Ground pins should be connected as shortly as possible to the system ground plane. For
more details about EMC Considerations, please refer to AVR040 application note.
2. The crystal should be located as close as possible to CLKEA and CLKEB pins. See Table 6-7 on page 19.
3. See Table 6-5 on page 16.
4. Different configurations allowed depending on external topology and net behavior.
5. Depending on whether an isolated or a non-isolated power supply is being used, isolation of this pin should be
taken into account in the circuitry design. Please refer to the Reference Design for further information.
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
5
4.
Package and Pinout
4.1
80-Lead LQFP Package Outline
The 80-lead LQFP package has a 0.5 mm pitch and respects Green standards.
Figure 4-1 shows the orientation of the 80-lead LQFP package. Refer to the section “Mechanical Characteristics” for
the 80-lead LQFP package mechanical drawing.
Figure 4-1. Orientation of the 80-Lead LQFP Package
60
41
61
40
80
21
1
4.2
80-Lead LQFP Pinout
Table 4-1.
6
20
80 - Lead LQFP Pinout
1
NC
21
VDDIO
41
GND
61
GND
2
NC
22
NC
42
EMIT8
62
AGND
3
NC
23
CLKOUT
43
EMIT9
63
VDDOUT AN
4
ARST
24
CS
44
EMIT10
64
VIMA
5
PLL INIT
25
SCK
45
EMIT11
65
VIPA
6
GND
26
MOSI
46
VDDIO
66
VDDOUT AN
7
CLKEA
27
MISO
47
GND
67
AGND
8
GND
28
VDDIO
48
VDDOUT
68
VRP
9
CLKEB
29
GND
49
TXRX0
69
VRM
10
VDDIO
30
EMIT0
50
TXRX1
70
VRC
11
GND
31
EMIT1
51
GND
71
VDDIN AN
12
VDDPLL
32
EMIT2
52
AGC2
72
AGND
13
GND
33
EMIT3
53
AGC5
73
AGND
14
VDDIN
34
VDDIO
54
AGC1
74
VDDIN AN
15
VDDIN
35
GND
55
AGC4
75
GND
16
GND
36
EMIT4
56
AGC0
76
VDDIO
17
VDDOUT
37
EMIT5
57
AGC3
77
VZ CROSS
18
GND
38
EMIT6
58
VDDIO
78
NC
19
NC
39
EMIT7
59
GND
79
NC
20
SRST
40
VDDIO
60
EINT
80
NC
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
5.
Analog Front-End
5.1
PLC coupling circuitry description
Atmel PLC coupling reference designs have been designed to achieve high performance, low cost and simplicity.
With these values on mind, Atmel has developed a set of PLC couplings covering frequencies below 500 kHz
compliant with different applicable regulations.
Atmel PLC technology is purely digital and does not require external DAC/ADC, thus simplifying the external required
circuitry. Generally Atmel PLC coupling reference designs make use of few passive components plus a Class D
amplification stage for transmission.
All PLC coupling reference designs are generally composed by the same sub-circuits:

Transmission Stage

Reception Stage

Filtering Stage

Coupling Stage
Figure 5-1. PLC coupling block diagram
RECEPTION
STAGE
AGC0
AGC1
AGC2
AGC3
AGC4
AGC5
VIPA
VRC
VIMA
VDD
TO MAINS
COUPLING STAGE
FILTERING STAGE
TRANSMISSION
STAGE
EMIT0
EMIT1
EMIT2
EMIT3
EMIT4
EMIT5
TXRX0
ATPL250A
A particular reference design can contain more than one sub-circuit of the same kind (i.e.: two transmission stages).
5.1.1
Transmission Stage
The transmission stage adapts the EMIT signals and amplifies them if required. It can be composed by:

Driver: A group of resistors which adapt the EMIT signals to either control the Class-D amplifier or to be filtered
by the next stage.

Amplifier: If required, a Class-D amplifier which generates a square waveform from 0 to VDD is included.

Bias and protection: A couple of resistors and a couple of Schottky barrier diodes provide a DC component and
provide protection from received disturbances.
Transmission stage shall be always followed by a filtering stage.
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
7
5.1.2
Filtering Stage
The filtering stage is composed by band-pass filters which have been designed to achieve high performance in field
deployments complying at the same time with the proper normative and standards.
The in-band flat response filtering stage does not distort the injected signal, reduces spurious emission to the limits
set by the corresponding regulation and blocks potential interferences from other transmission channels.
The Filtering stage has three aims:

Band-pass filtering of high frequency components of the square waveform generated by the Transmission
Stage.

Adapt Input/Output impedances for optimal reception/transmission. This is controlled by TXRX signal.

In some cases, Band-pass filtering for received signals.
When the system is intended to be connected to a physical channel with high voltage or which is not electrically
referenced to the same point then the filtering stage must be always followed by a coupling stage.
5.1.3
Coupling Stage
The coupling stage blocks the DC component of the line to/from which the signal is injected/received (i.e.: 50/60 Hz of
the mains). This is carried out by a high voltage capacitor.
Coupling stage could also electrically isolate the coupling circuitry from the external world by means of a 1:1
transformer.
5.1.4
Reception Stage
The reception stage adapts the received analog signal to be properly captured by the ATPL250A internal reception
chain. Reception circuit is independent of the PLC channel which is being used. It basically consists of:

Anti aliasing filter (RC Filter)

Automatic Gain Control (AGC) circuit

Driver of the internal ADC
The AGC circuit avoids distortion on the received signal that may arise when the input signal is high enough to
polarize the protective diodes in direct region.
The driver to the internal ADC comprises a couple of resistors and a couple of capacitors. This driver provides a DC
component and adapts the received signal to be properly converted by the internal reception chain.
8
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
5.1.5
Generic PLC Coupling
Please consider that this is a generic PLC Coupling design for a particular application please refer to Atmel doc43052
“PLC Coupling Reference Designs”.
Figure 5-2. PLC Coupling block diagram detailed
RECEPTION STAGE
VIPA
AGC5
AGC2
AGC4
AGC1
AGC3
AGC0
VRC
VIMA
3V3
TRANSMISSION STAGE
VDD
3V3
VDD
EMIT0
EMIT1
FILTERING STAGE
COUPLING STAGE
EMIT2
L
3V3
EMIT3
N
EMIT4
EMIT5
3V3
VDD
3V3
TXRX
+
5.2
ATPLCOUP reference designs
Atmel provides PLC coupling reference designs for different applications and frequency bands up to 500 kHz. Please
refer to Atmel doc43052 “PLC Coupling Reference Designs” for a detailed description.
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
9
5.3
Zero-crossing detector
5.3.1
Overview
Zero Crossing Detector block works predicting future zero crossing in function of the past zero crossings. To achieve
this, the system embeds a configurable Input Signal Management (ISM) block and a PLL, both of which manage Zero
Crossing Detector Input Signal to calculate Zero Crossing Output Flag. The zero-cross detection of waves of 50 Hz
and 60 Hz with ±10% of error is supported.
The PLL block interprets its input signal such a way that it indicates a zero cross in the middle of a positive pulse. It is
important to note that depending on the external circuit which implements the Zero Crossing Detector Input Signal this
interpretation is not always correct. So for these cases it is required to transform the Input Signal in a signal where the
middle of a positive pulse corresponds to a truly zero cross. This transformation is implemented through the Input
Signal Management (ISM) configured by MODE_INV and MODE_REP fields in ZC_CONFIG register.
Zero Crossing Detector Input Signal (VZ CROSS) must fulfil some requirements. The first requirement is that VZ
CROSS signal must be a pulse train which its duty cycle must be >60% or <40% (polarity is configurable). In addition,
if we have to detect Ascent or Descent zero-crossing, Zero Crossing Detector Input Signal period must be equal than
period of the wave we need to obtain zero-crossing. Ascent and Descent Zero Crossing Detection are configured by
setting MODE_MUX and MODE_ASC fields in ZC_CONFIG register.
Figure 5-3. Typical circuit, using a bidirectional optocoupler and a Schmitt trigger
Mains Signal
ZC signal provided
to VZ CROSS
The input signal “VZ CROSS”(wider line) generated by this circuit for Zero Cross Detection of the wave “L”-“N” (finer
line) is plotted in next figure. The digital signal at output of Input Signal Management (ISM) (dashed line) is also
plotted:
10
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
For this circuit, Zero Cross Internal registers should be configured this way:
ZC_CONFIG.MODE_MUX = ‘0’
ZC_CONFIG.MODE_ASC = ‘0’
ZC_CONFIG.MODE_INV = ‘1’
ZC_CONFIG.MODE_REP = ‘0’
ZC_CONFIG.FILTER_BP = ‘0’
Some situations (for example in some protocols like G3) could require only ascent (or descent) mains signal zerocrossings to be detected. When we have to detect Ascent or Descent Zero Cross of the wave (finer line), the circuit
should generate an input signal “VZ CROSS” (wider line) with the same period, as specified in next figure. This could
be easily implemented by using an unidirectional optocoupler or a Zener diode topology in the external circuitry.
Figure 5-4. Typical circuit, using a unidirectional optocoupler and a Schmitt trigger
Mains Signal
ZC signal provided
to VZ CROSS
The digital signal at output of Input Signal Management (ISM) (dashed line) is also plotted:
For this case, Zero Cross Internal registers should be configured this way:
ZC_CONFIG.MODE_MUX = ‘1’
ZC_CONFIG.MODE_ASC = ‘0’(ascent) or ‘1’(descent)
ZC_CONFIG.MODE_INV = ‘1’
ZC_CONFIG.MODE_REP = ‘1’
ZC_CONFIG.FILTER_BP = ‘0’
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
11
5.3.2
Zero Crossing Config register
Name:
ZC_CONFIG
Address:
0x4A0
Access:
Read/Write
Reset:
0x00023210
31
-
30
-
29
-
28
-
27
-
26
-
25
-
24
-
23
-
22
-
21
-
20
-
19
-
18
Reserved
17
PEAK2_ZC
_EN
16
PEAK1_ZC
_EN
15
-
14
13
12
11
FILTER_NUM [6:0]
10
9
8
7
-
6
-
5
-
4
FILTER_BP
2
MODE_INV
1
MODE_AS
C
0
MODE_MU
X
3
MODE_RE
P
• MODE_MUX: Zero Crossing Mode
‘0’: Selection of both ascent and descent zero-crossing
‘1’: Selection of ascent or descent zero-crossing
• MODE_ASC: Ascent-Descent Mode
‘0’: If MODE_MUX is 1, Ascent Zero Crossing
‘1’: If MODE_MUX is 1, Descent Zero Crossing
• MODE_INV: Inversion Mode
‘0’: No effect.
‘1’: Zero Crossing Detector Input Signal is inverted.
• MODE_REP: Repetition Mode
‘0’: No effect.
‘1’: Zero Crossing Detector Input Signal period is down by half.
• FILTER_BP: Zero Crossing Input Signal Filter Enable
‘0’: Filter enabled.
‘1’: Filter not enabled.
• FILTER_NUM[6:0]: Zero Crossing Input Signal Filter Parameter
Time (counted in number of clock cycles) that the Zero Crossing Input Signal (1-bit) must be constant to set that
value as the input signal for Zero Crossing Detection. Used to refuse fast transitions in Zero Crossing Input Signal.
• PEAK1_ZC_EN: indicates if PEAK_ZC_TIME updates its value with the last ZC_TIME when a PEAK1 is detected.
It is active high.
• PEAK2_ZC_EN: indicates if PEAK_ZC_TIME updates its value with the last ZC_TIME when a PEAK2 is detected.
It is active high.
12
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
6.
Electrical characteristics
6.1
Absolute Maximum Ratings
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions given in the Recommended Operating Conditions section. Exposure to the Absolute
Maximum Conditions for extended periods may affect device reliability.
Table 6-1.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Supply Voltage
VDDIO
-0.5 to 4.0
Input Voltage
VI
-0.5 to VDDIO +0.5 (≤ 4.0V)
Output Voltage
VO
-0.5 to VDDIO +0.5 (<4.0V)
Storage Temperature
TST
-55 to 125
Unit
V
ºC
Junction Temperature
TJ
-40 to 125
Output Current(1)
IO
±10(2)
Notes: 1.
2.
mA
DC current that continuously flows for 10 ms or more, or average DC current.
Applies to all the pins except EMIT pins. EMIT pins should be only used according to circuit configurations recommended by Atmel.
ATTENTION observe EDS precautions
Precautions for handling electrostatic sensitive devices
should be taken into account to avoid malfunction.
Charged devices and circuit boards can discharge
without detection.
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
13
6.2
Recommended Operating Conditions
Table 6-2.
Recommended Operating Conditions
Rating
Parameter
Symbol
Unit
Min
Typ
Max
VDDIO
3.00
3.30
3.60
VDDIN AN
3.00
3.30
3.60
VDDIN
3.00
3.30
3.60
VDDPLL
1.08
1.20
1.32
Junction Temperature
TJ
-40
25
125
Ambient Temperature
TA
-40
-
85
Supply Voltage
V
ºC
Table 6-3.
Thermal Data
Conditions
Parameter
Symbol
LQFP80
PCB Layers
2
Thermal resistance junction-to-ambient steady
state
RTheta-ja
4
Unit
Air Speed
0 m/s
64
1 m/s
56
3 m/s
48
0 m/s
43
1 m/s
40
3 m/s
36
ºC/W
Theta-ja is calculated based on a standard JEDEC defined environment and is not reliable indicator of a device’s
thermal performance in a non-JEDEC environment. The customer should always perform their own
calculations/simulations to ensure that their system’s thermal performance is sufficient.
14
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
6.3
Electrical Pinout
Table 6-4.
80 - Lead LQFP Electrical Pinout
Pin No
Pin Name
I/O
I(mA)
Res
HY
Pin No
Pin Name
1
NC
-
-
-
-
41
GND
2
NC
-
-
-
-
42
EMIT8
3
NC
-
-
-
-
43
EMIT9
4
ARST
I
-
PU
Y
44
EMIT10
5
PLL INIT
I
-
PU
Y
45
6
GND
P
-
-
-
46
7
CLKEA
I
-
-
-
I/O
I(mA)
Res
HY
P
-
-
-
OT
± 16
-
-
OT
± 16
-
-
OT
± 16
-
-
EMIT11
OT
± 16
-
-
VDDIO
P
-
-
-
47
GND
P
-
-
-
8
GND
P
-
-
-
48
VDDOUT
P
-
-
-
9
CLKEB
I/O
-
-
-
49
TXRX0
O
±8
-
-
10
VDDIO
P
-
-
-
50
TXRX1
O
±8
-
-
11
GND
P
-
-
-
51
GND
P
-
-
-
12
VDDPLL
P
-
-
-
52
AGC2
OT
± 16
-
Y
13
GND
P
-
-
-
53
AGC5
OT
± 16
-
Y
14
VDDIN
P
-
-
-
54
AGC1
OT
±6
-
Y
15
VDDIN
P
-
-
-
55
AGC4
OT
±6
-
Y
16
GND
P
-
-
-
56
AGC0
OT
±4
-
Y
17
VDDOUT
P
-
-
-
57
AGC3
OT
±4
-
Y
18
GND
P
-
-
-
58
VDDIO
P
-
-
-
19
NC
-
-
-
-
59
GND
P
-
-
-
20
SRST
I
-
PU
Y
60
EINT
O
±4
-
-
21
VDDIO
P
-
-
-
61
GND
P
-
-
-
22
NC
-
-
-
-
62
AGND
P
-
-
-
23
CLKOUT
O
±8
-
-
63
VDDOUT AN
P
-
-
-
24
CS
I
-
PU
Y
64
VIMA
I
-
-
-
25
SCK
I
-
PU
Y
65
VIPA
I
-
-
-
26
MOSI
I
-
PU
Y
66
VDDOUT AN
P
-
-
-
27
MISO
O
±6
-
-
67
AGND
P
-
-
-
28
VDDIO
P
-
-
-
68
VRP
O
-
-
-
29
GND
P
-
-
-
69
VRM
O
-
-
-
30
EMIT0
OT
± 16
-
-
70
VRC
O
-
-
-
31
EMIT1
OT
± 16
-
-
71
VDDIN AN
P
-
-
-
32
EMIT2
OT
± 16
-
-
72
AGND
P
-
-
-
33
EMIT3
OT
± 16
-
-
73
AGND
P
-
-
-
34
VDDIO
P
-
-
-
74
VDDIN AN
P
-
-
-
35
GND
P
-
-
-
75
GND
P
-
-
-
36
EMIT4
OT
± 16
-
-
76
VDDIO
P
-
-
-
37
EMIT5
OT
± 16
-
-
77
VZ CROSS
I
-
PD
Y
38
EMIT6
OT
± 16
-
-
78
NC
-
-
-
-
39
EMIT7
OT
± 16
-
-
79
NC
-
-
-
-
40
VDDIO
P
-
-
-
80
NC
-
-
-
-
I/O = pin direction:
I = input, O = output, T = tri-state, P = power
I(mA) = nominal current:
+ = source, - = sink, X = fixed by external resistor. See “V-I curves”
Res = pin pull up/pull down resistor:
PU = pull up, PD = pull down (15 - 70 kΩ, typical 33 kΩ)
HY = Input Hysteresis:
Y = yes
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
15
6.4
DC Characteristics
Table 6-5.
ATPL250A DC Characteristics
Rating
Parameter
Condition
Symbol
Unit
Min
Typ
Max
VDDIO
3.00
3.30
3.60
H-level Input Voltage (3.3V CMOS)
VIH
2.0
-
VDDIO +0.3
L-level Input Voltage (3.3V CMOS)
VIL
-0.3
-
0.8
VOH
VDDIO -0.2
-
VDDIO
VOL
0
-
0.2
Supply Voltage
H-level Output Voltage
L-level Output Voltage
H-level Output V - I Characteristics
L-level Output V - I Characteristics
3.3V I/O
IOH = -100 μA
3.3V I/O
IOL = 100 μA
3.3V I/O
VDDIO=3.3±0.3
3.3V I/O
VDDIO=3.3±0.3
IOH
See “V-I curves” section
IOL
See “V-I curves” section
V
mA
Internal Pull-up Resistor(1)
3.3V I/O
Rpu
15
33
70
Internal Pull-down Resistor(1)
3.3V I/O
Rpd
15
33
70
kΩ
Note:
16
1.
Only applicable to pins with internal pulling.
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
6.4.1
V-I curves
V-I Characteristics 3.3V standard CMOS IO L, M type
Apply to pins EINT, AGC0, AGC3
Condition:
MIN
Process = Slow
TJ = 125°C
VDDIO = 3.0V
TYP
Process = Typical
TJ = 25°C
VDDIO = 3.3V
MAX
Process = Fast
TJ = -40°C
VDDIO = 3.6V
Figure 6-1. V-I curves for pins EINT, AGC0, AGC3
Apply to pins MISO, AGC1, AGC4
Condition:
MIN
Process = Slow
TJ = 125°C
VDDIO = 3.0V
TYP
Process = Typical
TJ = 25°C
VDDIO = 3.3V
MAX
Process = Fast
TJ = -40°C
VDDIO = 3.6V
Figure 6-2. V-I curves for pins MISO, AGC1, AGC4
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
17
Apply to pins CLKOUT, TXRX0, TXRX1
Condition:
MIN
Process = Slow
TJ = 125°C
VDDIO = 3.0V
TYP
Process = Typical
TJ = 25°C
VDDIO = 3.3V
MAX
Process = Fast
TJ = -40°C
VDDIO = 3.6V
Figure 6-3. V-I curves for pins CLKOUT, TXRX0, TXRX1
Apply to pins EMIT [0:11], AGC2, AGC5
Condition:
MIN
Process = Slow
TJ = 125°C
VDDIO = 3.0V
TYP
Process = Typical
TJ = 25°C
VDDIO = 3.3V
MAX
Process = Fast
TJ = -40°C
VDDIO = 3.6V
Figure 6-4. V-I curves for pins EMIT [0:11], AGC2, AGC5
18
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
6.5
Power Consumption
Table 6-6.
Power Consumption
Rating
Parameter
Condition
Symbol
Unit
Min
Typ
Max
-
245
-
TJ = 25ºC
VDDIO = 3.3V
Power Consumption
VDDIN = 3.3V
P25
VDDIN AN = 3.3V
mW
TJ = 125ºC
VDDIO = 3.6V
Power Consumption (worst case)
VDDIN = 3.6V
P125
-
-
330
VDDIN AN = 3.6V
6.6
Oscillator
Table 6-7.
ATPL250A 24 MHz Crystal Oscillator Characteristics
Rating
Parameter
Test Condition
Symbol
Unit
Min
Crystal Oscillator frequency
Fundamental
Xtal
Typ
Max
24
MHz
CXTAL
-
18
-
CX
-
27
-
CPARA24M
-
4
-
H-level Input Voltage
XVIH
2
-
VDDIO +0.3
L-level Input Voltage
XVIL
-0.3
-
0.8
External Oscillator Capacitance(2)(3)
External capacitor on CLKEA and CLKEB(2)(3)
Internal parasitic capacitance
Between CLKEA and CLKEB
pF
V
External Oscillator Parallel Resistance
Rp
External Oscillator Series Resistance
Rs
not needed
Ω
Notes: 1.
-
220
-
The crystal should be located as close as possible to CLKEB and CLKEA pins.
2.
Recommended value for Cx is 27 pF and Rs 220 Ω. These values may depend on the specific crystal
characteristics and PCB layout. See example below. For further information please refer to Atmel
doc43084 “Crystal Selection Guidelines” application note.
3.
As a requirement of G3 specification, the System Clock tolerance from which transmit frequency and
symbol timing are derived shall be ± 25 ppm maximum. Crystal Stability/Tolerance/Ageing values must
be selected according to standard G3 requirements.
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
19
Figure 6-5. 24 MHz Crystal Oscillator Schematic
ATPL250A
CPARA24M
CLKEA
CLKEB
RS
C PCB
CX
C PCB
CX
CX = 2 x (CXTAL – CPARA24M – CPCB / 2)
where CPCB is the ground referenced parasitic capacitance of the printed circuit board (PCB) on CLKEA and CLKEB
tracks.
As a practical example, taking the following crystal part number:
Manufacturer: TXC CORPORATION
PartNumber: 9C-24.000MEEJ-T
Frequency: 24.000 MHz
Tolerance: 10 ppm (as low as possible to fullfil G3 specification requirements)
CXTAL = 18 pF
Working in a typical layout / substrate with CPCB = 1 pF
The value of the external capacitors on CLKEA and CLKEB should be CX = 2 x (18 - 4 - 0.5) = 27 pF
It is strongly recommended to use capacitors with the lowest temperature stability possible. In this practical example,
a suitable part number could be:
Manufacturer: MURATA
PartNumber: GRM1885C1H270FA01D
Capacitance: 27 pF
Tolerance: 1 %
Dielectric: C0G / NP0 (0 drift)
20
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
6.7
Power On Considerations
During power-on, PLL INIT pin should be tied to ground during 4 μs at least, in order to ensure proper system start up.
After releasing PLL INIT, the system will start no later than 612 μs.
After power-up system can be restarted by means of low active pulse (min 1.65 μs) in ARST or SRST. System full
operation starts after 410 μs (ARST pulse) or after 0.9 μs (SRST pulse).
In case of simultaneous tie down of more than one initialization pin the longest time for operation must be respected.
Figure 6-6. Power On timing diagram
> 4us
> 612us
PLL INIT
> 1.65us*
ARST
> 410us
> 1.65us*
> 0.9us
SRST
FULL OPERATION
SYSTEM
(*) 1.65us = 33*tclk
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
21
7.
Mechanical Characteristics
7.1
LQFP80 Mechanical Characteristics
Figure 7-1. 80 LQFP package dimensions
Table 7-1.
LQFP Package Reference
JEDEC Drawing Reference
Table 7-2.
MS-026
LQFP Package Characteristics
Moisture Sensitivity Level
3
This package respects the recommendations of the NEMI User Group.
22
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
8.
Recommended mounting conditions
8.1
Conditions of Standard Reflow
Table 8-1.
Recommended mounting conditions of Standard Reflow
Items
Method
Times
Floor Life
Floor Life Condition
Contents
IR (Infrared Reflow) / Convection
2
Please use within 2 years after
Before unpacking
production
From unpacking to second reflow
Within 8 days
Baking with 125ºC +/- 3ºC for 24hrs
+2hrs/-0hrs is required. Then please
In case over period of floor life
use within 8 days (please remember
baking is up to 2 times).
Between 5ºC and 30ºC and also below 70% RH required. (It is preferred lower
humidity in the required temp. range).
Figure 8-1. LQFP80 package soldering profile
Note:
H rank: 260ºC Max
a: Average ramp-up rate:
1ºC/s to 4ºC/s
b: Preheat & Soak:
170ºC to 190ºC, 60s to 180s
c: Average ramp-up rate:
1ºC/s to 4ºC/s
d: Peak temperature:
260ºC Max, up to 255ºC within 10s
d’: Liquidous temperature:
Up to 230ºC within 40s or
Up to 225ºC within 60s or
Up to 220ºC within 80s
e: Cooling:
Natural cooling or forced cooling
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
23
8.2
Manual Soldering
Table 8-2.
Recommended mounting conditions of Manual Soldering
Items
Contents
Before unpacking
Please use
production
From unpacking to Manual Soldering
Within 2 years after production (No
control required for moisture adsorption
because it is partial heating)
Floor life
Floor life condition
Solder Condition
24
within
2
years
after
Between 5°C and 30°C and also below 70% RH required. (It is preferred lower
humidity in the required temp. range).
Temperature of soldering iron: Max 400°C, Time: Within 5 seconds/pin.
*Be careful for touching package body with iron.
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
9.
Ordering Information
Table 9-1.
Ordering Information
Atmel Ordering Code
ATPL250A-AKU-Y
ATPL250A-AKU-R
Package
80 LQFP
80 LQFP
AT
Atmel Designator
AT = Atmel
Product Family
PL = Power Line Communications
Device Designator
Device Revision
Package Type
Pb-Free
Pb-Free
PL
250 A - A K U - X
Temperature Range
Industrial (-40ºC to 85ºC)
Industrial (-40ºC to 85ºC)
xx
Customer marking
xx = “ ”
Shipping Carrier Option
Y = Tray
R = Tape and Reel
Package Device Grade or
Wafer/Die Thickness
U = Lead free (Pb-free)
Industrial temperature range
(-40ºC to +85ºC)
Package Option
AK = 80 LQFP
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
25
10.
Revision History
In the table that follows, the most recent version of the document appears first.
Doc. Rev. Comments
43079
E
Section 5.3 ”Zero-crossing detector”: updated.
D
Format changes according to new templates.
C
Section 6.6 ”Oscillator” updated: modified Figure 6-5, added equation and information after the figure.
Table 6-7 updated: added the values of CXTAL and CPARA24M . Modified the notes below the table.
Chapters order redefined.
Modified Section 1.1 ”ATPL250A Application Block Diagram” (was Section 8. “Application
information”).
B
Figure 1-1 updated: RST and CLKOUT signals introduced.
Table 6-6 updated the values of Power Consumption and Power Consumption (worst case).
Modified Section 5. ”Analog Front-End” (was “PLC coupling circuitry description”).
Deleted Section “Power Considerations”: the information of this section is in Section 3. ”Signal
Description”.
A
26
First Issue.
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
Change
Request
Ref.
Table of Contents
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1
ATPL250A Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
4.2
80-Lead LQFP Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
80-Lead LQFP Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5. Analog Front-End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1
5.2
5.3
PLC coupling circuitry description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ATPLCOUP reference designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Zero-crossing detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power On Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
14
15
16
19
19
21
7. Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1
LQFP80 Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8. Recommended mounting conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1
8.2
Conditions of Standard Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Manual Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ATPL250A [DATASHEET]
Atmel-43079E-ATPL250A-Datasheet_22-Feb-16
27
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